[PATCH v3 1/5] drm:amdgpu: enable IH RB ring1 for IH v6.0

[PATCH v3 1/5] drm:amdgpu: enable IH RB ring1 for IH v6.0

[Sunil Khatri]

We need IH ring1 for handling the pagefault
interrupts which are overflowing the default
ring for specific usecases.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
index ad4ad39f128f..26dc99232eb6 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
@@ -549,8 +549,15 @@ static int ih_v6_0_sw_init(void *handle)
 	adev->irq.ih.use_doorbell = true;
 	adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
 
-	adev->irq.ih1.ring_size = 0;
-	adev->irq.ih2.ring_size = 0;
+	if (!(adev->flags & AMD_IS_APU)) {
+		r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE,
+					use_bus_addr);
+		if (r)
+			return r;
+
+		adev->irq.ih1.use_doorbell = true;
+		adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
+	}
 
 	/* initialize ih control register offset */
 	ih_v6_0_init_register_offset(adev);
-- 
2.34.1

[PATCH v3 2/5] drm:amdgpu: Enable IH ring1 for IH v6.1

[Sunil Khatri]

We need IH ring1 for handling the pagefault
interrupts which over flow in default
ring for specific usecases.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
index b8da0fc29378..73dba180fabd 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
@@ -550,8 +550,15 @@ static int ih_v6_1_sw_init(void *handle)
 	adev->irq.ih.use_doorbell = true;
 	adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
 
-	adev->irq.ih1.ring_size = 0;
-	adev->irq.ih2.ring_size = 0;
+	if (!(adev->flags & AMD_IS_APU)) {
+		r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE,
+					use_bus_addr);
+		if (r)
+			return r;
+
+		adev->irq.ih1.use_doorbell = true;
+		adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
+	}
 
 	/* initialize ih control register offset */
 	ih_v6_1_init_register_offset(adev);
-- 
2.34.1

Re: [PATCH v3 2/5] drm:amdgpu: Enable IH ring1 for IH v6.1

[Friedrich Vock]

On 16.04.24 15:34, Sunil Khatri wrote:
> We need IH ring1 for handling the pagefault
> interrupts which over flow in default
> ring for specific usecases.
>
> Signed-off-by: Sunil Khatri<sunil.khatri@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 11 +++++++++--
>   1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> index b8da0fc29378..73dba180fabd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> @@ -550,8 +550,15 @@ static int ih_v6_1_sw_init(void *handle)
>   	adev->irq.ih.use_doorbell = true;
>   	adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
>
> -	adev->irq.ih1.ring_size = 0;
> -	adev->irq.ih2.ring_size = 0;
> +	if (!(adev->flags & AMD_IS_APU)) {

Why restrict this to dGPUs? Page faults can overflow the default ring on
APUs too (e.g. for Vangogh).

Regards,
Friedrich

> +		r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE,
> +					use_bus_addr);
> +		if (r)
> +			return r;
> +
> +		adev->irq.ih1.use_doorbell = true;
> +		adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
> +	}
>
>   	/* initialize ih control register offset */
>   	ih_v6_1_init_register_offset(adev);

Re: [PATCH v3 2/5] drm:amdgpu: Enable IH ring1 for IH v6.1

[Christian König]

Am 17.04.24 um 08:43 schrieb Friedrich Vock:
> On 16.04.24 15:34, Sunil Khatri wrote:
>> We need IH ring1 for handling the pagefault
>> interrupts which over flow in default
>> ring for specific usecases.
>>
>> Signed-off-by: Sunil Khatri<sunil.khatri@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 11 +++++++++--
>>   1 file changed, 9 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c 
>> b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
>> index b8da0fc29378..73dba180fabd 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
>> @@ -550,8 +550,15 @@ static int ih_v6_1_sw_init(void *handle)
>>       adev->irq.ih.use_doorbell = true;
>>       adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
>>
>> -    adev->irq.ih1.ring_size = 0;
>> -    adev->irq.ih2.ring_size = 0;
>> +    if (!(adev->flags & AMD_IS_APU)) {
>
> Why restrict this to dGPUs? Page faults can overflow the default ring on
> APUs too (e.g. for Vangogh).

Because APUs don't have the necessary hw. In other words they have no 
secondary IH ring buffer :(

But we are working on a fw fix for them and Navi 1x and 2x as well.

Regards,
Christian.

>
> Regards,
> Friedrich
>
>> +        r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE,
>> +                    use_bus_addr);
>> +        if (r)
>> +            return r;
>> +
>> +        adev->irq.ih1.use_doorbell = true;
>> +        adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) 
>> << 1;
>> +    }
>>
>>       /* initialize ih control register offset */
>>       ih_v6_1_init_register_offset(adev);

[PATCH v3 3/5] drm/amdgpu: Add IH_RING1_CFG headers for IH v6.0

[Sunil Khatri]

Add offsets, mask and shift macros for IH v6.0
which are needed to configure ring1 client irq
redirection.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 .../drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h |  4 ++++
 .../amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h    | 10 ++++++++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h
index 8b931bbabe70..969e006b859b 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_offset.h
@@ -237,6 +237,10 @@
 #define regSEM_REGISTER_LAST_PART2_BASE_IDX                                                             0
 #define regIH_CLIENT_CFG                                                                                0x0184
 #define regIH_CLIENT_CFG_BASE_IDX                                                                       0
+#define regIH_RING1_CLIENT_CFG_INDEX                                                                    0x0185
+#define regIH_RING1_CLIENT_CFG_INDEX_BASE_IDX                                                           0
+#define regIH_RING1_CLIENT_CFG_DATA                                                                     0x0186
+#define regIH_RING1_CLIENT_CFG_DATA_BASE_IDX                                                            0
 #define regIH_CLIENT_CFG_INDEX                                                                          0x0188
 #define regIH_CLIENT_CFG_INDEX_BASE_IDX                                                                 0
 #define regIH_CLIENT_CFG_DATA                                                                           0x0189
diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h
index f262f44fa68c..a672a91e58f0 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_6_0_0_sh_mask.h
@@ -888,6 +888,16 @@
 //IH_CLIENT_CFG
 #define IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT                                                                0x0
 #define IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK                                                                  0x0000003FL
+//IH_RING1_CLIENT_CFG_INDEX
+#define IH_RING1_CLIENT_CFG_INDEX__INDEX__SHIFT                                                               0x0
+#define IH_RING1_CLIENT_CFG_INDEX__INDEX_MASK                                                                 0x00000007L
+//IH_RING1_CLIENT_CFG_DATA
+#define IH_RING1_CLIENT_CFG_DATA__CLIENT_ID__SHIFT                                                            0x0
+#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID__SHIFT                                                            0x8
+#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE__SHIFT                                               0x10
+#define IH_RING1_CLIENT_CFG_DATA__CLIENT_ID_MASK                                                              0x000000FFL
+#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MASK                                                              0x0000FF00L
+#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE_MASK                                                 0x00010000L
 //IH_CLIENT_CFG_INDEX
 #define IH_CLIENT_CFG_INDEX__INDEX__SHIFT                                                                     0x0
 #define IH_CLIENT_CFG_INDEX__INDEX_MASK                                                                       0x0000001FL
-- 
2.34.1

[PATCH v3 4/5] drm/amdgpu: enable redirection of irq's for IH V6.0

[Sunil Khatri]

Enable redirection of irq for pagefaults for specific
clients to avoid overflow without dropping interrupts.

So here we redirect the interrupts to another IH ring
i.e ring1 where only these interrupts are processed.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
index 26dc99232eb6..8869aac03b82 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
@@ -346,6 +346,21 @@ static int ih_v6_0_irq_init(struct amdgpu_device *adev)
 			    DELAY, 3);
 	WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);
 
+	/* Redirect the interrupts to IH RB1 fpr dGPU */
+	if (adev->irq.ih1.ring_size) {
+		tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);
+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);
+		WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);
+
+		tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);
+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);
+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);
+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,
+				    SOURCE_ID_MATCH_ENABLE, 0x1);
+
+		WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);
+	}
+
 	pci_set_master(adev->pdev);
 
 	/* enable interrupts */
-- 
2.34.1

Re: [PATCH v3 4/5] drm/amdgpu: enable redirection of irq's for IH V6.0

[Alex Deucher]

On Tue, Apr 16, 2024 at 9:34 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>
> Enable redirection of irq for pagefaults for specific
> clients to avoid overflow without dropping interrupts.
>
> So here we redirect the interrupts to another IH ring
> i.e ring1 where only these interrupts are processed.
>
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> index 26dc99232eb6..8869aac03b82 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> @@ -346,6 +346,21 @@ static int ih_v6_0_irq_init(struct amdgpu_device *adev)
>                             DELAY, 3);
>         WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);
>
> +       /* Redirect the interrupts to IH RB1 fpr dGPU */

fpr -> for

Alex

> +       if (adev->irq.ih1.ring_size) {
> +               tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);
> +               tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);
> +               WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);
> +
> +               tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);
> +               tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);
> +               tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);
> +               tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,
> +                                   SOURCE_ID_MATCH_ENABLE, 0x1);
> +
> +               WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);
> +       }
> +
>         pci_set_master(adev->pdev);
>
>         /* enable interrupts */
> --
> 2.34.1
>

Re: [PATCH v3 4/5] drm/amdgpu: enable redirection of irq's for IH V6.0

[Khatri, Sunil]

On 4/16/2024 7:56 PM, Alex Deucher wrote:
> On Tue, Apr 16, 2024 at 9:34 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>> Enable redirection of irq for pagefaults for specific
>> clients to avoid overflow without dropping interrupts.
>>
>> So here we redirect the interrupts to another IH ring
>> i.e ring1 where only these interrupts are processed.
>>
>> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 15 +++++++++++++++
>>   1 file changed, 15 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
>> index 26dc99232eb6..8869aac03b82 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
>> @@ -346,6 +346,21 @@ static int ih_v6_0_irq_init(struct amdgpu_device *adev)
>>                              DELAY, 3);
>>          WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);
>>
>> +       /* Redirect the interrupts to IH RB1 fpr dGPU */
> fpr -> for

Sure will fix it when pushing the change to staging branch.

Regards
Sunil khatri

>
> Alex
>
>> +       if (adev->irq.ih1.ring_size) {
>> +               tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);
>> +               tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);
>> +               WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);
>> +
>> +               tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);
>> +               tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);
>> +               tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);
>> +               tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,
>> +                                   SOURCE_ID_MATCH_ENABLE, 0x1);
>> +
>> +               WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);
>> +       }
>> +
>>          pci_set_master(adev->pdev);
>>
>>          /* enable interrupts */
>> --
>> 2.34.1
>>

[PATCH v3 5/5] drm/amdgpu: enable redirection of irq's for IH V6.1

[Sunil Khatri]

Enable redirection of irq for pagefaults for specific
clients to avoid overflow without dropping interrupts.

So here we redirect the interrupts to another IH ring
i.e ring1 where only these interrupts are processed.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
index 73dba180fabd..29ed78798070 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
@@ -346,6 +346,21 @@ static int ih_v6_1_irq_init(struct amdgpu_device *adev)
 			    DELAY, 3);
 	WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);
 
+	/* Redirect the interrupts to IH RB1 for dGPU */
+	if (adev->irq.ih1.ring_size) {
+		tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);
+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);
+		WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);
+
+		tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);
+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);
+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);
+		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,
+				    SOURCE_ID_MATCH_ENABLE, 0x1);
+
+		WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);
+	}
+
 	pci_set_master(adev->pdev);
 
 	/* enable interrupts */
-- 
2.34.1

Re: [PATCH v3 1/5] drm:amdgpu: enable IH RB ring1 for IH v6.0

[Christian König]

Am 16.04.24 um 15:34 schrieb Sunil Khatri:
> We need IH ring1 for handling the pagefault
> interrupts which are overflowing the default
> ring for specific usecases.
>
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>

Reviewed-by: Christian König <christian.koenig@amd.com> for the entire 
series.

> ---
>   drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 11 +++++++++--
>   1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> index ad4ad39f128f..26dc99232eb6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> @@ -549,8 +549,15 @@ static int ih_v6_0_sw_init(void *handle)
>   	adev->irq.ih.use_doorbell = true;
>   	adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
>   
> -	adev->irq.ih1.ring_size = 0;
> -	adev->irq.ih2.ring_size = 0;
> +	if (!(adev->flags & AMD_IS_APU)) {
> +		r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE,
> +					use_bus_addr);
> +		if (r)
> +			return r;
> +
> +		adev->irq.ih1.use_doorbell = true;
> +		adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
> +	}
>   
>   	/* initialize ih control register offset */
>   	ih_v6_0_init_register_offset(adev);