From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake
Date: Mon, 4 May 2020 15:52:05 -0700 [thread overview]
Message-ID: <20200504225227.464666-1-matthew.d.roper@intel.com> (raw)
Only minor changes since v1, but patchwork got confused by the updates,
so sending the whole series again to ensure proper CI testing.
v2 changes:
- Drop the cdclk patch. The bspec was updated since I originally wrote
that and now RKL's table is identical to the one we use on TGL and
ICL. No RKL-specific driver changes are necessary now.
- Fix a botched mask in the DPCLKA_CFGCR0 clock selection.
See the cover letter from v1 for other details:
https://lists.freedesktop.org/archives/intel-gfx/2020-May/238498.html
Aditya Swarup (1):
drm/i915/rkl: Don't try to read out DSI transcoders
José Roberto de Souza (1):
drm/i915/rkl: Disable PSR2
Lucas De Marchi (1):
drm/i915/rkl: provide port/phy mapping for vbt
Matt Roper (19):
drm/i915/rkl: Add RKL platform info and PCI ids
x86/gpu: add RKL stolen memory support
drm/i915/rkl: Re-use TGL GuC/HuC firmware
drm/i915/rkl: Load DMC firmware for Rocket Lake
drm/i915/rkl: Add PCH support
drm/i915/rkl: Update memory bandwidth parameters
drm/i915/rkl: Limit number of universal planes to 5
drm/i915/rkl: Add power well support
drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2
drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B
drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout
drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs
drm/i915/rkl: Setup ports/phys
drm/i915/rkl: Add DDC pin mapping
drm/i915/rkl: Don't try to access transcoder D
drm/i915/rkl: Handle comp master/slave relationships for PHYs
drm/i915/rkl: Add DPLL4 support
drm/i915/rkl: Handle HTI
drm/i915/rkl: Add initial workarounds
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/display/intel_bios.c | 72 ++++--
drivers/gpu/drm/i915/display/intel_bw.c | 10 +-
.../gpu/drm/i915/display/intel_combo_phy.c | 55 +++--
drivers/gpu/drm/i915/display/intel_csr.c | 10 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 18 +-
drivers/gpu/drm/i915/display/intel_display.c | 82 +++++--
.../drm/i915/display/intel_display_power.c | 229 ++++++++++++++++--
drivers/gpu/drm/i915/display/intel_dp.c | 8 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 50 +++-
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 22 +-
drivers/gpu/drm/i915/display/intel_psr.c | 15 ++
drivers/gpu/drm/i915/display/intel_sprite.c | 22 +-
drivers/gpu/drm/i915/display/intel_sprite.h | 11 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 4 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 ++++---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 3 +
drivers/gpu/drm/i915/i915_drv.h | 13 +
drivers/gpu/drm/i915/i915_irq.c | 10 +-
drivers/gpu/drm/i915/i915_pci.c | 13 +
drivers/gpu/drm/i915/i915_reg.h | 35 ++-
drivers/gpu/drm/i915/intel_device_info.c | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 2 +
drivers/gpu/drm/i915/intel_pch.c | 8 +-
include/drm/i915_pciids.h | 9 +
26 files changed, 656 insertions(+), 141 deletions(-)
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next reply other threads:[~2020-05-04 22:52 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-04 22:52 Matt Roper [this message]
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 01/22] drm/i915/rkl: Add RKL platform info and PCI ids Matt Roper
2020-05-07 11:18 ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support Matt Roper
2020-05-06 11:51 ` Srivatsa, Anusha
2020-05-19 23:57 ` Lucas De Marchi
2020-05-20 9:30 ` Borislav Petkov
2020-05-20 17:49 ` Lucas De Marchi
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 03/22] drm/i915/rkl: Re-use TGL GuC/HuC firmware Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 04/22] drm/i915/rkl: Load DMC firmware for Rocket Lake Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 05/22] drm/i915/rkl: Add PCH support Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 06/22] drm/i915/rkl: Update memory bandwidth parameters Matt Roper
2020-05-07 12:24 ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 07/22] drm/i915/rkl: Limit number of universal planes to 5 Matt Roper
2020-05-07 12:10 ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 08/22] drm/i915/rkl: Add power well support Matt Roper
2020-05-05 4:50 ` Anshuman Gupta
2020-05-05 14:39 ` Matt Roper
2020-05-05 16:09 ` Imre Deak
2020-05-06 12:13 ` Anshuman Gupta
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 09/22] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B Matt Roper
2020-05-06 13:49 ` Srivatsa, Anusha
2020-05-06 16:49 ` Matt Roper
2020-05-07 11:22 ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 11/22] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs Matt Roper
2020-05-07 11:38 ` Srivatsa, Anusha
2020-05-07 11:59 ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 13/22] drm/i915/rkl: Setup ports/phys Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 14/22] drm/i915/rkl: provide port/phy mapping for vbt Matt Roper
2020-05-07 12:04 ` Ville Syrjälä
2020-05-07 18:05 ` Matt Roper
2020-05-08 9:44 ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 15/22] drm/i915/rkl: Add DDC pin mapping Matt Roper
2020-05-06 9:19 ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 16/22] drm/i915/rkl: Don't try to access transcoder D Matt Roper
2020-05-06 20:34 ` Matt Roper
2020-05-06 21:21 ` [Intel-gfx] [PATCH v3 " Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 17/22] drm/i915/rkl: Don't try to read out DSI transcoders Matt Roper
2020-05-07 11:58 ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 18/22] drm/i915/rkl: Handle comp master/slave relationships for PHYs Matt Roper
2020-05-06 9:20 ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 19/22] drm/i915/rkl: Add DPLL4 support Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 20/22] drm/i915/rkl: Handle HTI Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 21/22] drm/i915/rkl: Disable PSR2 Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 22/22] drm/i915/rkl: Add initial workarounds Matt Roper
2020-05-04 23:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev4) Patchwork
2020-05-04 23:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-05 13:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-05-06 22:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev5) Patchwork
2020-05-06 22:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-07 2:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200504225227.464666-1-matthew.d.roper@intel.com \
--to=matthew.d.roper@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).