From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 03/22] drm/i915/rkl: Re-use TGL GuC/HuC firmware
Date: Mon, 4 May 2020 15:52:08 -0700 [thread overview]
Message-ID: <20200504225227.464666-4-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20200504225227.464666-1-matthew.d.roper@intel.com>
RKL uses the same GuC and HuC as TGL and should load the same firmwares.
Bspec: 50668
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index e1caae93996d..9b6218128d09 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -47,8 +47,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
* TGL 35.2 is interface-compatible with 33.0 for previous Gens. The deltas
* between 33.0 and 35.2 are only related to new additions to support new Gen12
* features.
+ *
+ * Note that RKL uses the same firmware as TGL.
*/
#define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
+ fw_def(ROCKETLAKE, 0, guc_def(tgl, 35, 2, 0), huc_def(tgl, 7, 0, 12)) \
fw_def(TIGERLAKE, 0, guc_def(tgl, 35, 2, 0), huc_def(tgl, 7, 0, 12)) \
fw_def(ELKHARTLAKE, 0, guc_def(ehl, 33, 0, 4), huc_def(ehl, 9, 0, 0)) \
fw_def(ICELAKE, 0, guc_def(icl, 33, 0, 0), huc_def(icl, 9, 0, 0)) \
--
2.24.1
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next prev parent reply other threads:[~2020-05-04 22:52 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 01/22] drm/i915/rkl: Add RKL platform info and PCI ids Matt Roper
2020-05-07 11:18 ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support Matt Roper
2020-05-06 11:51 ` Srivatsa, Anusha
2020-05-19 23:57 ` Lucas De Marchi
2020-05-20 9:30 ` Borislav Petkov
2020-05-20 17:49 ` Lucas De Marchi
2020-05-04 22:52 ` Matt Roper [this message]
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 04/22] drm/i915/rkl: Load DMC firmware for Rocket Lake Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 05/22] drm/i915/rkl: Add PCH support Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 06/22] drm/i915/rkl: Update memory bandwidth parameters Matt Roper
2020-05-07 12:24 ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 07/22] drm/i915/rkl: Limit number of universal planes to 5 Matt Roper
2020-05-07 12:10 ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 08/22] drm/i915/rkl: Add power well support Matt Roper
2020-05-05 4:50 ` Anshuman Gupta
2020-05-05 14:39 ` Matt Roper
2020-05-05 16:09 ` Imre Deak
2020-05-06 12:13 ` Anshuman Gupta
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 09/22] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B Matt Roper
2020-05-06 13:49 ` Srivatsa, Anusha
2020-05-06 16:49 ` Matt Roper
2020-05-07 11:22 ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 11/22] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs Matt Roper
2020-05-07 11:38 ` Srivatsa, Anusha
2020-05-07 11:59 ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 13/22] drm/i915/rkl: Setup ports/phys Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 14/22] drm/i915/rkl: provide port/phy mapping for vbt Matt Roper
2020-05-07 12:04 ` Ville Syrjälä
2020-05-07 18:05 ` Matt Roper
2020-05-08 9:44 ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 15/22] drm/i915/rkl: Add DDC pin mapping Matt Roper
2020-05-06 9:19 ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 16/22] drm/i915/rkl: Don't try to access transcoder D Matt Roper
2020-05-06 20:34 ` Matt Roper
2020-05-06 21:21 ` [Intel-gfx] [PATCH v3 " Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 17/22] drm/i915/rkl: Don't try to read out DSI transcoders Matt Roper
2020-05-07 11:58 ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 18/22] drm/i915/rkl: Handle comp master/slave relationships for PHYs Matt Roper
2020-05-06 9:20 ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 19/22] drm/i915/rkl: Add DPLL4 support Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 20/22] drm/i915/rkl: Handle HTI Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 21/22] drm/i915/rkl: Disable PSR2 Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 22/22] drm/i915/rkl: Add initial workarounds Matt Roper
2020-05-04 23:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev4) Patchwork
2020-05-04 23:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-05 13:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-05-06 22:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev5) Patchwork
2020-05-06 22:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-07 2:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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