intel-gfx.lists.freedesktop.org archive mirror
 help / color / mirror / Atom feed
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
	Lucas De Marchi <lucas.demarchi@intel.com>
Subject: Re: [Intel-gfx] [PATCH v2 14/22] drm/i915/rkl: provide port/phy mapping for vbt
Date: Thu, 7 May 2020 15:04:30 +0300	[thread overview]
Message-ID: <20200507120430.GD6112@intel.com> (raw)
In-Reply-To: <20200504225227.464666-15-matthew.d.roper@intel.com>

On Mon, May 04, 2020 at 03:52:19PM -0700, Matt Roper wrote:
> From: Lucas De Marchi <lucas.demarchi@intel.com>
> 
> RKL uses the DDI A, DDI B, DDI USBC1, DDI USBC2 from the DE point of
> view, so all DDI/pipe/transcoder register use these indexes to refer to
> them. Combo phy and IO functions follow another namespace that we keep
> as "enum phy". The VBT in theory would use the DE point of view, but
> that does not happen in practice.
> 
> Provide a table to convert the child devices to the "correct" port
> numbering we use. Now this is the output we get while reading the VBT:
> 
> DDIA:
> [drm:intel_bios_port_aux_ch [i915]] using AUX A for port A (VBT)
> [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:275:DDI A]
> [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:275:DDI A]
> [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x1 for port A (VBT)
> 
> DDIB:
> [drm:intel_bios_port_aux_ch [i915]] using AUX B for port B (platform default)
> [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:291:DDI B]
> [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x2 for port B (VBT)
> 
> DDI USBC1:
> [drm:intel_bios_port_aux_ch [i915]] using AUX D for port D (VBT)
> [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:295:DDI D]
> [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:295:DDI D]
> [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x3 for port D (VBT)
> 
> DDI USBC2:
> [drm:intel_bios_port_aux_ch [i915]] using AUX E for port E (VBT)
> [drm:intel_dp_init_connector [i915]] Adding DP connector on [ENCODER:306:DDI E]
> [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on [ENCODER:306:DDI E]
> [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x9 for port E (VBT)
> 
> Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Cc: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 72 ++++++++++++++++-------
>  1 file changed, 51 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 839124647202..4f1a72a90b8f 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1619,30 +1619,18 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
>  	return 0;
>  }
>  
> -static enum port dvo_port_to_port(u8 dvo_port)
> +static enum port __dvo_port_to_port(int n_ports, int n_dvo,
> +				    const int port_mapping[][3], u8 dvo_port)
>  {
> -	/*
> -	 * Each DDI port can have more than one value on the "DVO Port" field,
> -	 * so look for all the possible values for each port.
> -	 */
> -	static const int dvo_ports[][3] = {
> -		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1},
> -		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1},
> -		[PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
> -		[PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1},
> -		[PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
> -		[PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1},
> -		[PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1},
> -	};
>  	enum port port;
>  	int i;
>  
> -	for (port = PORT_A; port < ARRAY_SIZE(dvo_ports); port++) {
> -		for (i = 0; i < ARRAY_SIZE(dvo_ports[port]); i++) {
> -			if (dvo_ports[port][i] == -1)
> +	for (port = PORT_A; port < n_ports; port++) {
> +		for (i = 0; i < n_dvo; i++) {
> +			if (port_mapping[port][i] == -1)
>  				break;
>  
> -			if (dvo_port == dvo_ports[port][i])
> +			if (dvo_port == port_mapping[port][i])
>  				return port;
>  		}
>  	}
> @@ -1650,6 +1638,48 @@ static enum port dvo_port_to_port(u8 dvo_port)
>  	return PORT_NONE;
>  }
>  
> +static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
> +				  u8 dvo_port)
> +{
> +	/*
> +	 * Each DDI port can have more than one value on the "DVO Port" field,
> +	 * so look for all the possible values for each port.
> +	 */
> +	static const int port_mapping[][3] = {
> +		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
> +		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
> +		[PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
> +		[PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
> +		[PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, -1 },
> +		[PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 },
> +		[PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 },
> +	};
> +	/*
> +	 * Bspec lists the ports as A, B, C, D - however internally in our
> +	 * driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the
> +	 * registers in Display Engine match the right offsets. Apply the
> +	 * mapping here to translate from VBT to internal convention.
> +	 */
> +	static const int rkl_port_mapping[][3] = {
> +		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
> +		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
> +		[PORT_C] = { -1 },
> +		[PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
> +		[PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
> +	};
> +
> +	if (IS_ROCKETLAKE(dev_priv))
> +		return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
> +					  ARRAY_SIZE(rkl_port_mapping[0]),
> +					  rkl_port_mapping,
> +					  dvo_port);
> +	else
> +		return __dvo_port_to_port(ARRAY_SIZE(port_mapping),
> +					  ARRAY_SIZE(port_mapping[0]),
> +					  port_mapping,
> +					  dvo_port);
> +}

What a horror show. To me it looks like we should just use the
phy here. Or would that break something else?

> +
>  static void parse_ddi_port(struct drm_i915_private *dev_priv,
>  			   struct display_device_data *devdata,
>  			   u8 bdb_version)
> @@ -1659,7 +1689,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv,
>  	bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
>  	enum port port;
>  
> -	port = dvo_port_to_port(child->dvo_port);
> +	port = dvo_port_to_port(dev_priv, child->dvo_port);
>  	if (port == PORT_NONE)
>  		return;
>  
> @@ -2603,10 +2633,10 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
>  		aux_ch = AUX_CH_B;
>  		break;
>  	case DP_AUX_C:
> -		aux_ch = AUX_CH_C;
> +		aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C;
>  		break;
>  	case DP_AUX_D:
> -		aux_ch = AUX_CH_D;
> +		aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D;
>  		break;
>  	case DP_AUX_E:
>  		aux_ch = AUX_CH_E;
> -- 
> 2.24.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-05-07 12:04 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-04 22:52 [Intel-gfx] [PATCH v2 00/22] Introduce Rocket Lake Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 01/22] drm/i915/rkl: Add RKL platform info and PCI ids Matt Roper
2020-05-07 11:18   ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 02/22] x86/gpu: add RKL stolen memory support Matt Roper
2020-05-06 11:51   ` Srivatsa, Anusha
2020-05-19 23:57     ` Lucas De Marchi
2020-05-20  9:30       ` Borislav Petkov
2020-05-20 17:49         ` Lucas De Marchi
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 03/22] drm/i915/rkl: Re-use TGL GuC/HuC firmware Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 04/22] drm/i915/rkl: Load DMC firmware for Rocket Lake Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 05/22] drm/i915/rkl: Add PCH support Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 06/22] drm/i915/rkl: Update memory bandwidth parameters Matt Roper
2020-05-07 12:24   ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 07/22] drm/i915/rkl: Limit number of universal planes to 5 Matt Roper
2020-05-07 12:10   ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 08/22] drm/i915/rkl: Add power well support Matt Roper
2020-05-05  4:50   ` Anshuman Gupta
2020-05-05 14:39     ` Matt Roper
2020-05-05 16:09       ` Imre Deak
2020-05-06 12:13         ` Anshuman Gupta
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 09/22] drm/i915/rkl: Program BW_BUDDY0 registers instead of BW_BUDDY1/2 Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 10/22] drm/i915/rkl: RKL only uses PHY_MISC for PHY's A and B Matt Roper
2020-05-06 13:49   ` Srivatsa, Anusha
2020-05-06 16:49     ` Matt Roper
2020-05-07 11:22       ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 11/22] drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs Matt Roper
2020-05-07 11:38   ` Srivatsa, Anusha
2020-05-07 11:59   ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 13/22] drm/i915/rkl: Setup ports/phys Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 14/22] drm/i915/rkl: provide port/phy mapping for vbt Matt Roper
2020-05-07 12:04   ` Ville Syrjälä [this message]
2020-05-07 18:05     ` Matt Roper
2020-05-08  9:44       ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 15/22] drm/i915/rkl: Add DDC pin mapping Matt Roper
2020-05-06  9:19   ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 16/22] drm/i915/rkl: Don't try to access transcoder D Matt Roper
2020-05-06 20:34   ` Matt Roper
2020-05-06 21:21   ` [Intel-gfx] [PATCH v3 " Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 17/22] drm/i915/rkl: Don't try to read out DSI transcoders Matt Roper
2020-05-07 11:58   ` Ville Syrjälä
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 18/22] drm/i915/rkl: Handle comp master/slave relationships for PHYs Matt Roper
2020-05-06  9:20   ` Srivatsa, Anusha
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 19/22] drm/i915/rkl: Add DPLL4 support Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 20/22] drm/i915/rkl: Handle HTI Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 21/22] drm/i915/rkl: Disable PSR2 Matt Roper
2020-05-04 22:52 ` [Intel-gfx] [PATCH v2 22/22] drm/i915/rkl: Add initial workarounds Matt Roper
2020-05-04 23:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev4) Patchwork
2020-05-04 23:33 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-05 13:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-05-06 22:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Rocket Lake (rev5) Patchwork
2020-05-06 22:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-07  2:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200507120430.GD6112@intel.com \
    --to=ville.syrjala@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=lucas.demarchi@intel.com \
    --cc=matthew.d.roper@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).