From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: [PATCH 00/13] Enumerate midlevel and endpoint decoders
Date: Thu, 2 Sep 2021 12:50:04 -0700 [thread overview]
Message-ID: <20210902195017.2516472-1-ben.widawsky@intel.com> (raw)
Every CXL component may implement component registers as defined by the CXL 2.0
specification. In preparation for creating and enumerating regions it's
important to at least enumerate all HDM decoders which are a subset of the
component registers. To do this, a new cxl_mem driver is introduced which is
responsible for binding to a CXL.mem enabled device. In order to determine
whether or not an endpoint is CXL enabled, the relevant subhierarchy must be
enumerated.
This serves as the stepping stone toward enabling regions because regions must
be able to determine if the devices selected for the region are CXL.mem capable
and enabled.
There's two issues that need to be resolved but I'm going to propose we fix
them next time we need to touch this code...
1. cxl_pci now relinquishes its component register mappings. This may be
undesirable as cxl_pci may need to use those mappings.
2a. some amount of component register enumeration is duplicated in cxl_pci and
cxl_mem
2b. awkwardness in cxl_mem where memdevs get their component registers from
cxl_pci, and ports that enumerate their own component registers
The obvious fix for both of these is to move component register mapping to
cxl_core, and let cxl_core arbitrate the mappings for the "client" drivers.
Since the code needed to enable cxl_mem was small and subset of the existing
code (and fairly error resistent vs creating a cxl_core API) I'm hoping to kick
the can down the road.
NOTE: I do not have a way at present to test switches. For this reason and for
patch readability, the switch enumeration is left as a separate patch.
NOTE2: Some of these patches were introduced in an RFC for region creation. Upon
further inspection, it made a lot of sense to land these before region creation
so long as it's understood upfront why the new driver is needed.
I've pushed this to my gitlab here:
https://gitlab.com/bwidawsk/linux/-/tree/decoders
Ben Widawsky (13):
Documentation/cxl: Add bus internal docs
cxl/core/bus: Add kernel docs for decoder ops
cxl/core: Ignore interleave when adding decoders
cxl: Introduce endpoint decoders
cxl/pci: Disambiguate cxl_pci further from cxl_mem
cxl/mem: Introduce cxl_mem driver
cxl/memdev: Determine CXL.mem capability
cxl/mem: Add memdev as a port
cxl/pci: Retain map information in cxl_mem_probe
cxl/core: Map component registers for ports
cxl/core: Convert decoder range to resource
cxl/core/bus: Enumerate all HDM decoders
cxl/mem: Enumerate switch decoders
.../driver-api/cxl/memory-devices.rst | 6 +
drivers/cxl/Makefile | 3 +-
drivers/cxl/acpi.c | 39 +--
drivers/cxl/core/bus.c | 326 +++++++++++++++++-
drivers/cxl/core/core.h | 1 +
drivers/cxl/core/memdev.c | 19 +-
drivers/cxl/core/regs.c | 6 +-
drivers/cxl/cxl.h | 65 +++-
drivers/cxl/cxlmem.h | 6 +-
drivers/cxl/mem.c | 237 +++++++++++++
drivers/cxl/pci.c | 124 +++----
drivers/cxl/pci.h | 15 +-
12 files changed, 727 insertions(+), 120 deletions(-)
create mode 100644 drivers/cxl/mem.c
--
2.33.0
next reply other threads:[~2021-09-02 19:50 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-02 19:50 Ben Widawsky [this message]
2021-09-02 19:50 ` [PATCH 01/13] Documentation/cxl: Add bus internal docs Ben Widawsky
2021-09-03 14:05 ` Jonathan Cameron
2021-09-10 18:20 ` Dan Williams
2021-09-02 19:50 ` [PATCH 02/13] cxl/core/bus: Add kernel docs for decoder ops Ben Widawsky
2021-09-03 14:17 ` Jonathan Cameron
2021-09-10 18:51 ` Dan Williams
2021-09-11 17:25 ` Ben Widawsky
2021-09-02 19:50 ` [PATCH 03/13] cxl/core: Ignore interleave when adding decoders Ben Widawsky
2021-09-03 14:25 ` Jonathan Cameron
2021-09-10 19:00 ` Dan Williams
2021-09-11 17:30 ` Ben Widawsky
2021-09-02 19:50 ` [PATCH 04/13] cxl: Introduce endpoint decoders Ben Widawsky
2021-09-03 14:35 ` Jonathan Cameron
2021-09-13 16:19 ` Ben Widawsky
2021-09-10 19:19 ` Dan Williams
2021-09-13 16:11 ` Ben Widawsky
2021-09-13 22:07 ` Dan Williams
2021-09-13 23:19 ` Ben Widawsky
2021-09-14 21:16 ` Dan Williams
2021-09-02 19:50 ` [PATCH 05/13] cxl/pci: Disambiguate cxl_pci further from cxl_mem Ben Widawsky
2021-09-03 14:45 ` Jonathan Cameron
2021-09-10 19:27 ` Dan Williams
2021-09-02 19:50 ` [PATCH 06/13] cxl/mem: Introduce cxl_mem driver Ben Widawsky
2021-09-03 14:52 ` Jonathan Cameron
2021-09-10 21:32 ` Dan Williams
2021-09-13 16:46 ` Ben Widawsky
2021-09-13 19:37 ` Dan Williams
2021-09-02 19:50 ` [PATCH 07/13] cxl/memdev: Determine CXL.mem capability Ben Widawsky
2021-09-03 15:21 ` Jonathan Cameron
2021-09-13 19:01 ` Ben Widawsky
2021-09-10 21:59 ` Dan Williams
2021-09-13 22:10 ` Ben Widawsky
2021-09-14 22:42 ` Dan Williams
2021-09-14 22:55 ` Ben Widawsky
2021-09-02 19:50 ` [PATCH 08/13] cxl/mem: Add memdev as a port Ben Widawsky
2021-09-03 15:31 ` Jonathan Cameron
2021-09-10 23:09 ` Dan Williams
2021-09-02 19:50 ` [PATCH 09/13] cxl/pci: Retain map information in cxl_mem_probe Ben Widawsky
2021-09-10 23:12 ` Dan Williams
2021-09-10 23:45 ` Dan Williams
2021-09-02 19:50 ` [PATCH 10/13] cxl/core: Map component registers for ports Ben Widawsky
2021-09-02 22:41 ` Ben Widawsky
2021-09-02 22:42 ` Ben Widawsky
2021-09-03 16:14 ` Jonathan Cameron
2021-09-10 23:52 ` Dan Williams
2021-09-13 8:29 ` Jonathan Cameron
2021-09-10 23:44 ` Dan Williams
2021-09-02 19:50 ` [PATCH 11/13] cxl/core: Convert decoder range to resource Ben Widawsky
2021-09-03 16:16 ` Jonathan Cameron
2021-09-11 0:59 ` Dan Williams
2021-09-02 19:50 ` [PATCH 12/13] cxl/core/bus: Enumerate all HDM decoders Ben Widawsky
2021-09-03 17:43 ` Jonathan Cameron
2021-09-11 1:37 ` Dan Williams
2021-09-11 1:13 ` Dan Williams
2021-09-02 19:50 ` [PATCH 13/13] cxl/mem: Enumerate switch decoders Ben Widawsky
2021-09-03 17:56 ` Jonathan Cameron
2021-09-13 22:12 ` Ben Widawsky
2021-09-14 23:31 ` Dan Williams
2021-09-10 18:15 ` [PATCH 00/13] Enumerate midlevel and endpoint decoders Dan Williams
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210902195017.2516472-1-ben.widawsky@intel.com \
--to=ben.widawsky@intel.com \
--cc=Jonathan.Cameron@Huawei.com \
--cc=alison.schofield@intel.com \
--cc=dan.j.williams@intel.com \
--cc=ira.weiny@intel.com \
--cc=linux-cxl@vger.kernel.org \
--cc=vishal.l.verma@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).