Re: [PATCH 08/13] cxl/mem: Add memdev as a port

From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Ben Widawsky <ben.widawsky@intel.com>
Cc: <linux-cxl@vger.kernel.org>,
	Alison Schofield <alison.schofield@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	"Ira Weiny" <ira.weiny@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>
Subject: Re: [PATCH 08/13] cxl/mem: Add memdev as a port
Date: Fri, 3 Sep 2021 16:31:25 +0100	[thread overview]
Message-ID: <20210903163125.00001da3@Huawei.com> (raw)
In-Reply-To: <20210902195017.2516472-9-ben.widawsky@intel.com>

On Thu, 2 Sep 2021 12:50:12 -0700
Ben Widawsky <ben.widawsky@intel.com> wrote:

> CXL endpoints contain HDM decoders that are architecturally the same as
> a CXL switch, or a CXL hostbridge. While some restrictions are in place
> for endpoints, they will require the same enumeration logic to determine
> the number and abilities of the HDM decoders.
> 
> Utilizing the existing port APIs from cxl_core is the simplest way to
> gain access to the same set of information that switches and hostbridges
> have.
> 
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
In of itself seems sensible.  (note I'm reviewing these one at a time but
reserve the right to throw my hands up in horror at the end result ;)

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>  drivers/cxl/core/bus.c |  5 ++++-
>  drivers/cxl/mem.c      | 10 +++++++++-
>  2 files changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/cxl/core/bus.c b/drivers/cxl/core/bus.c
> index 56f57302d27b..f26095b40f5c 100644
> --- a/drivers/cxl/core/bus.c
> +++ b/drivers/cxl/core/bus.c
> @@ -377,7 +377,10 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport,
>  
>  	dev = &port->dev;
>  	if (parent_port)
> -		rc = dev_set_name(dev, "port%d", port->id);
> +		if (host->type == &cxl_memdev_type)
> +			rc = dev_set_name(dev, "devport%d", port->id);
> +		else
> +			rc = dev_set_name(dev, "port%d", port->id);
>  	else
>  		rc = dev_set_name(dev, "root%d", port->id);
>  	if (rc)
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> index b6dc34d18a86..9d5a3a29cda1 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/mem.c
> @@ -63,6 +63,7 @@ static int cxl_mem_probe(struct device *dev)
>  	struct device *pdev_parent = cxlm->dev->parent;
>  	struct pci_dev *pdev = to_pci_dev(cxlm->dev);
>  	struct device *port_dev;
> +	int rc;
>  
>  	if (!is_cxl_mem_enabled(pdev))
>  		return -ENODEV;
> @@ -72,7 +73,14 @@ static int cxl_mem_probe(struct device *dev)
>  	if (!port_dev)
>  		return -ENODEV;
>  
> -	return 0;
> +	/* TODO: Obtain component registers */
> +	rc = PTR_ERR_OR_ZERO(devm_cxl_add_port(&cxlmd->dev, &cxlmd->dev,

oh. Nasty / efficient depending on how you look at it.

> +					       CXL_RESOURCE_NONE,
> +					       to_cxl_port(port_dev)));
> +	if (rc)
> +		dev_err(dev, "Unable to add devices upstream port");
> +
> +	return rc;
>  }
>  
>  static void cxl_mem_remove(struct device *dev)