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From: Dan Williams <dan.j.williams@intel.com>
To: Ben Widawsky <ben.widawsky@intel.com>
Cc: linux-cxl@vger.kernel.org,
	Alison Schofield <alison.schofield@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Vishal Verma <vishal.l.verma@intel.com>
Subject: Re: [PATCH 04/13] cxl: Introduce endpoint decoders
Date: Tue, 14 Sep 2021 14:16:44 -0700	[thread overview]
Message-ID: <CAPcyv4hMS_O+19Qb8pEX0DpPBZQL7zP0Lyukk9j0EmSXf_igEw@mail.gmail.com> (raw)
In-Reply-To: <20210913231921.w2rujefmewgraopi@intel.com>

On Mon, Sep 13, 2021 at 4:19 PM Ben Widawsky <ben.widawsky@intel.com> wrote:
>
> On 21-09-13 15:07:44, Dan Williams wrote:
> > On Mon, Sep 13, 2021 at 9:11 AM Ben Widawsky <ben.widawsky@intel.com> wrote:
> > >
> > > On 21-09-10 12:19:24, Dan Williams wrote:
> > > > On Thu, Sep 2, 2021 at 12:50 PM Ben Widawsky <ben.widawsky@intel.com> wrote:
> > > > >
> > > > > Endpoints have decoders too. It is useful to share the same
> > > > > infrastructure from cxl_core. Endpoints do not have dports (downstream
> > > > > targets), only the underlying physical medium. As a result, some special
> > > > > casing is needed.
> > > > >
> > > > > There is no functional change introduced yet as endpoints don't actually
> > > > > enumerate decoders yet.
> > > > >
> > > > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
> > > > > ---
> > > > >  drivers/cxl/core/bus.c | 29 +++++++++++++++++++++++++----
> > > > >  1 file changed, 25 insertions(+), 4 deletions(-)
> > > > >
> > > > > diff --git a/drivers/cxl/core/bus.c b/drivers/cxl/core/bus.c
> > > > > index 8d5061b0794d..6202ce5a5ac2 100644
> > > > > --- a/drivers/cxl/core/bus.c
> > > > > +++ b/drivers/cxl/core/bus.c
> > > > > @@ -175,6 +175,12 @@ static const struct attribute_group *cxl_decoder_switch_attribute_groups[] = {
> > > > >         NULL,
> > > > >  };
> > > > >
> > > > > +static const struct attribute_group *cxl_decoder_endpoint_attribute_groups[] = {
> > > > > +       &cxl_decoder_base_attribute_group,
> > > > > +       &cxl_base_attribute_group,
> > > > > +       NULL,
> > > > > +};
> > > > > +
> > > > >  static void cxl_decoder_release(struct device *dev)
> > > > >  {
> > > > >         struct cxl_decoder *cxld = to_cxl_decoder(dev);
> > > > > @@ -184,6 +190,12 @@ static void cxl_decoder_release(struct device *dev)
> > > > >         kfree(cxld);
> > > > >  }
> > > > >
> > > > > +static const struct device_type cxl_decoder_endpoint_type = {
> > > > > +       .name = "cxl_decoder_endpoint",
> > > > > +       .release = cxl_decoder_release,
> > > > > +       .groups = cxl_decoder_endpoint_attribute_groups,
> > > > > +};
> > > > > +
> > > > >  static const struct device_type cxl_decoder_switch_type = {
> > > > >         .name = "cxl_decoder_switch",
> > > > >         .release = cxl_decoder_release,
> > > > > @@ -196,6 +208,11 @@ static const struct device_type cxl_decoder_root_type = {
> > > > >         .groups = cxl_decoder_root_attribute_groups,
> > > > >  };
> > > > >
> > > > > +static bool is_endpoint_decoder(struct device *dev)
> > > > > +{
> > > > > +       return dev->type == &cxl_decoder_endpoint_type;
> > > > > +}
> > > > > +
> > > > >  bool is_root_decoder(struct device *dev)
> > > > >  {
> > > > >         return dev->type == &cxl_decoder_root_type;
> > > > > @@ -472,7 +489,7 @@ struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port, int nr_targets)
> > > > >         struct device *dev;
> > > > >         int rc = 0;
> > > > >
> > > > > -       if (nr_targets > CXL_DECODER_MAX_INTERLEAVE || nr_targets < 1)
> > > > > +       if (nr_targets > CXL_DECODER_MAX_INTERLEAVE)
> > > > >                 return ERR_PTR(-EINVAL);
> > > > >
> > > > >         cxld = kzalloc(struct_size(cxld, target, nr_targets), GFP_KERNEL);
> > > > > @@ -491,8 +508,11 @@ struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port, int nr_targets)
> > > > >         dev->parent = &port->dev;
> > > > >         dev->bus = &cxl_bus_type;
> > > > >
> > > > > +       /* Endpoints don't have a target list */
> > > > > +       if (nr_targets == 0)
> > > > > +               dev->type = &cxl_decoder_endpoint_type;
> > > >
> > > > Do you also plan to introduce the concept of endpoint ports, and if
> > > > yes should that come before this patch? That would seem to be more
> > > > robust than, for example, allowing a switch port to carry an endpoint
> > > > decoder object as this allows.
> > >
> > > I didn't see a need as of yet to differentiate between endpoint ports and other
> > > ports. I don't entirely understand what you mean by "allowing a switch port to
> > > carry an endpoint decoder" means. Can you please elaborate?
> >
> > If endpoint ports were an explicit type then this check could make
> > sure that someone did not pass nr_targets set to 0 where the @port
> > argument is referring to a switch where the target_list must be
> > specified.
> >
> > Either that, or a comment in kernel-doc for this routine about the
> > special meaning of nr_targets == 0 and expected usage.
>
> Well, since Jonathan also brought up a concern here perhaps I should entertain
> other ideas. I suppose future versions of the spec could break things, but as it
> stands today the only CXL component that implements decoders that can have a 0
> value for this are endpoint devices (T2 or T3, or LD). I think it's fine to wait
> until we have a second reason to make an endpoint port type and update kdocs for
> now, but maybe it will also be a natural fit with a proper port driver.

"Document only" sounds good to me.

  reply	other threads:[~2021-09-14 21:18 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-02 19:50 [PATCH 00/13] Enumerate midlevel and endpoint decoders Ben Widawsky
2021-09-02 19:50 ` [PATCH 01/13] Documentation/cxl: Add bus internal docs Ben Widawsky
2021-09-03 14:05   ` Jonathan Cameron
2021-09-10 18:20     ` Dan Williams
2021-09-02 19:50 ` [PATCH 02/13] cxl/core/bus: Add kernel docs for decoder ops Ben Widawsky
2021-09-03 14:17   ` Jonathan Cameron
2021-09-10 18:51   ` Dan Williams
2021-09-11 17:25     ` Ben Widawsky
2021-09-02 19:50 ` [PATCH 03/13] cxl/core: Ignore interleave when adding decoders Ben Widawsky
2021-09-03 14:25   ` Jonathan Cameron
2021-09-10 19:00     ` Dan Williams
2021-09-11 17:30       ` Ben Widawsky
2021-09-02 19:50 ` [PATCH 04/13] cxl: Introduce endpoint decoders Ben Widawsky
2021-09-03 14:35   ` Jonathan Cameron
2021-09-13 16:19     ` Ben Widawsky
2021-09-10 19:19   ` Dan Williams
2021-09-13 16:11     ` Ben Widawsky
2021-09-13 22:07       ` Dan Williams
2021-09-13 23:19         ` Ben Widawsky
2021-09-14 21:16           ` Dan Williams [this message]
2021-09-02 19:50 ` [PATCH 05/13] cxl/pci: Disambiguate cxl_pci further from cxl_mem Ben Widawsky
2021-09-03 14:45   ` Jonathan Cameron
2021-09-10 19:27   ` Dan Williams
2021-09-02 19:50 ` [PATCH 06/13] cxl/mem: Introduce cxl_mem driver Ben Widawsky
2021-09-03 14:52   ` Jonathan Cameron
2021-09-10 21:32   ` Dan Williams
2021-09-13 16:46     ` Ben Widawsky
2021-09-13 19:37       ` Dan Williams
2021-09-02 19:50 ` [PATCH 07/13] cxl/memdev: Determine CXL.mem capability Ben Widawsky
2021-09-03 15:21   ` Jonathan Cameron
2021-09-13 19:01     ` Ben Widawsky
2021-09-10 21:59   ` Dan Williams
2021-09-13 22:10     ` Ben Widawsky
2021-09-14 22:42       ` Dan Williams
2021-09-14 22:55         ` Ben Widawsky
2021-09-02 19:50 ` [PATCH 08/13] cxl/mem: Add memdev as a port Ben Widawsky
2021-09-03 15:31   ` Jonathan Cameron
2021-09-10 23:09   ` Dan Williams
2021-09-02 19:50 ` [PATCH 09/13] cxl/pci: Retain map information in cxl_mem_probe Ben Widawsky
2021-09-10 23:12   ` Dan Williams
2021-09-10 23:45     ` Dan Williams
2021-09-02 19:50 ` [PATCH 10/13] cxl/core: Map component registers for ports Ben Widawsky
2021-09-02 22:41   ` Ben Widawsky
2021-09-02 22:42     ` Ben Widawsky
2021-09-03 16:14   ` Jonathan Cameron
2021-09-10 23:52     ` Dan Williams
2021-09-13  8:29       ` Jonathan Cameron
2021-09-10 23:44   ` Dan Williams
2021-09-02 19:50 ` [PATCH 11/13] cxl/core: Convert decoder range to resource Ben Widawsky
2021-09-03 16:16   ` Jonathan Cameron
2021-09-11  0:59   ` Dan Williams
2021-09-02 19:50 ` [PATCH 12/13] cxl/core/bus: Enumerate all HDM decoders Ben Widawsky
2021-09-03 17:43   ` Jonathan Cameron
2021-09-11  1:37     ` Dan Williams
2021-09-11  1:13   ` Dan Williams
2021-09-02 19:50 ` [PATCH 13/13] cxl/mem: Enumerate switch decoders Ben Widawsky
2021-09-03 17:56   ` Jonathan Cameron
2021-09-13 22:12     ` Ben Widawsky
2021-09-14 23:31   ` Dan Williams
2021-09-10 18:15 ` [PATCH 00/13] Enumerate midlevel and endpoint decoders Dan Williams

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