From: Ben Widawsky <ben.widawsky@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: linux-cxl@vger.kernel.org,
Alison Schofield <alison.schofield@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>
Subject: Re: [PATCH 04/13] cxl: Introduce endpoint decoders
Date: Mon, 13 Sep 2021 09:19:57 -0700 [thread overview]
Message-ID: <20210913161957.qzaoibfalyoamc5c@intel.com> (raw)
In-Reply-To: <20210903153542.00004518@Huawei.com>
On 21-09-03 15:35:42, Jonathan Cameron wrote:
> On Thu, 2 Sep 2021 12:50:08 -0700
> Ben Widawsky <ben.widawsky@intel.com> wrote:
>
> > Endpoints have decoders too. It is useful to share the same
> > infrastructure from cxl_core. Endpoints do not have dports (downstream
> > targets), only the underlying physical medium. As a result, some special
> > casing is needed.
> >
> > There is no functional change introduced yet as endpoints don't actually
> > enumerate decoders yet.
> >
> > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
>
> Comments inline...
>
> > ---
> > drivers/cxl/core/bus.c | 29 +++++++++++++++++++++++++----
> > 1 file changed, 25 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/cxl/core/bus.c b/drivers/cxl/core/bus.c
> > index 8d5061b0794d..6202ce5a5ac2 100644
> > --- a/drivers/cxl/core/bus.c
> > +++ b/drivers/cxl/core/bus.c
> > @@ -175,6 +175,12 @@ static const struct attribute_group *cxl_decoder_switch_attribute_groups[] = {
> > NULL,
> > };
> >
> > +static const struct attribute_group *cxl_decoder_endpoint_attribute_groups[] = {
> > + &cxl_decoder_base_attribute_group,
> > + &cxl_base_attribute_group,
> > + NULL,
> > +};
> > +
> > static void cxl_decoder_release(struct device *dev)
> > {
> > struct cxl_decoder *cxld = to_cxl_decoder(dev);
> > @@ -184,6 +190,12 @@ static void cxl_decoder_release(struct device *dev)
> > kfree(cxld);
> > }
> >
> > +static const struct device_type cxl_decoder_endpoint_type = {
> > + .name = "cxl_decoder_endpoint",
> > + .release = cxl_decoder_release,
> > + .groups = cxl_decoder_endpoint_attribute_groups,
> > +};
> > +
> > static const struct device_type cxl_decoder_switch_type = {
> > .name = "cxl_decoder_switch",
> > .release = cxl_decoder_release,
> > @@ -196,6 +208,11 @@ static const struct device_type cxl_decoder_root_type = {
> > .groups = cxl_decoder_root_attribute_groups,
> > };
> >
> > +static bool is_endpoint_decoder(struct device *dev)
> > +{
> > + return dev->type == &cxl_decoder_endpoint_type;
> > +}
> > +
> > bool is_root_decoder(struct device *dev)
> > {
> > return dev->type == &cxl_decoder_root_type;
> > @@ -472,7 +489,7 @@ struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port, int nr_targets)
> > struct device *dev;
> > int rc = 0;
> >
> > - if (nr_targets > CXL_DECODER_MAX_INTERLEAVE || nr_targets < 1)
>
> Why do we let nr_targets go negative? Could make the parameter unsigned perhaps or
> check for that here (even though it makes no sense).
Unsigned seems like a good idea to me as well.
>
> > + if (nr_targets > CXL_DECODER_MAX_INTERLEAVE)
> > return ERR_PTR(-EINVAL);
> >
> > cxld = kzalloc(struct_size(cxld, target, nr_targets), GFP_KERNEL);
> > @@ -491,8 +508,11 @@ struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port, int nr_targets)
> > dev->parent = &port->dev;
> > dev->bus = &cxl_bus_type;
> >
> > + /* Endpoints don't have a target list */
> > + if (nr_targets == 0)
> > + dev->type = &cxl_decoder_endpoint_type;
>
> Hmm. Whilst the check seems valid, it's a bit inelegant.
> The capability register unhelpfully simply has it defined
> as not applicable rather than 0, so I'd be nervous that might
> end up here (not checked yet).
AFAICT, 0 isn't a valid value in the register at all. Additionally, from the API
perspective I don't see much of an issue because nr_targets is the decoded
value. So the only entity that should call this with a value of 0 would have to
be something which is ignoring the field in the capability register, which would
only be an endpoint.
>
> > /* root ports do not have a cxl_port_type parent */
> > - if (port->dev.parent->type == &cxl_port_type)
> > + else if (port->dev.parent->type == &cxl_port_type)
> > dev->type = &cxl_decoder_switch_type;
> > else
> > dev->type = &cxl_decoder_root_type;
> > @@ -532,9 +552,11 @@ int cxl_decoder_add(struct device *host, struct cxl_decoder *cxld,
> > if (IS_ERR(cxld))
> > return PTR_ERR(cxld);
> >
> > + dev = &cxld->dev;
> > +
> > port = to_cxl_port(cxld->dev.parent);
> > device_lock(&port->dev);
> > - if (list_empty(&port->dports)) {
> > + if (is_endpoint_decoder(dev) && list_empty(&port->dports)) {
> > rc = -EINVAL;
> > goto out_unlock;
> > }
> > @@ -551,7 +573,6 @@ int cxl_decoder_add(struct device *host, struct cxl_decoder *cxld,
> > }
> > device_unlock(&port->dev);
> >
> > - dev = &cxld->dev;
> > rc = dev_set_name(dev, "decoder%d.%d", port->id, cxld->id);
> > if (rc)
> > return rc;
>
next prev parent reply other threads:[~2021-09-13 16:20 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-02 19:50 [PATCH 00/13] Enumerate midlevel and endpoint decoders Ben Widawsky
2021-09-02 19:50 ` [PATCH 01/13] Documentation/cxl: Add bus internal docs Ben Widawsky
2021-09-03 14:05 ` Jonathan Cameron
2021-09-10 18:20 ` Dan Williams
2021-09-02 19:50 ` [PATCH 02/13] cxl/core/bus: Add kernel docs for decoder ops Ben Widawsky
2021-09-03 14:17 ` Jonathan Cameron
2021-09-10 18:51 ` Dan Williams
2021-09-11 17:25 ` Ben Widawsky
2021-09-02 19:50 ` [PATCH 03/13] cxl/core: Ignore interleave when adding decoders Ben Widawsky
2021-09-03 14:25 ` Jonathan Cameron
2021-09-10 19:00 ` Dan Williams
2021-09-11 17:30 ` Ben Widawsky
2021-09-02 19:50 ` [PATCH 04/13] cxl: Introduce endpoint decoders Ben Widawsky
2021-09-03 14:35 ` Jonathan Cameron
2021-09-13 16:19 ` Ben Widawsky [this message]
2021-09-10 19:19 ` Dan Williams
2021-09-13 16:11 ` Ben Widawsky
2021-09-13 22:07 ` Dan Williams
2021-09-13 23:19 ` Ben Widawsky
2021-09-14 21:16 ` Dan Williams
2021-09-02 19:50 ` [PATCH 05/13] cxl/pci: Disambiguate cxl_pci further from cxl_mem Ben Widawsky
2021-09-03 14:45 ` Jonathan Cameron
2021-09-10 19:27 ` Dan Williams
2021-09-02 19:50 ` [PATCH 06/13] cxl/mem: Introduce cxl_mem driver Ben Widawsky
2021-09-03 14:52 ` Jonathan Cameron
2021-09-10 21:32 ` Dan Williams
2021-09-13 16:46 ` Ben Widawsky
2021-09-13 19:37 ` Dan Williams
2021-09-02 19:50 ` [PATCH 07/13] cxl/memdev: Determine CXL.mem capability Ben Widawsky
2021-09-03 15:21 ` Jonathan Cameron
2021-09-13 19:01 ` Ben Widawsky
2021-09-10 21:59 ` Dan Williams
2021-09-13 22:10 ` Ben Widawsky
2021-09-14 22:42 ` Dan Williams
2021-09-14 22:55 ` Ben Widawsky
2021-09-02 19:50 ` [PATCH 08/13] cxl/mem: Add memdev as a port Ben Widawsky
2021-09-03 15:31 ` Jonathan Cameron
2021-09-10 23:09 ` Dan Williams
2021-09-02 19:50 ` [PATCH 09/13] cxl/pci: Retain map information in cxl_mem_probe Ben Widawsky
2021-09-10 23:12 ` Dan Williams
2021-09-10 23:45 ` Dan Williams
2021-09-02 19:50 ` [PATCH 10/13] cxl/core: Map component registers for ports Ben Widawsky
2021-09-02 22:41 ` Ben Widawsky
2021-09-02 22:42 ` Ben Widawsky
2021-09-03 16:14 ` Jonathan Cameron
2021-09-10 23:52 ` Dan Williams
2021-09-13 8:29 ` Jonathan Cameron
2021-09-10 23:44 ` Dan Williams
2021-09-02 19:50 ` [PATCH 11/13] cxl/core: Convert decoder range to resource Ben Widawsky
2021-09-03 16:16 ` Jonathan Cameron
2021-09-11 0:59 ` Dan Williams
2021-09-02 19:50 ` [PATCH 12/13] cxl/core/bus: Enumerate all HDM decoders Ben Widawsky
2021-09-03 17:43 ` Jonathan Cameron
2021-09-11 1:37 ` Dan Williams
2021-09-11 1:13 ` Dan Williams
2021-09-02 19:50 ` [PATCH 13/13] cxl/mem: Enumerate switch decoders Ben Widawsky
2021-09-03 17:56 ` Jonathan Cameron
2021-09-13 22:12 ` Ben Widawsky
2021-09-14 23:31 ` Dan Williams
2021-09-10 18:15 ` [PATCH 00/13] Enumerate midlevel and endpoint decoders Dan Williams
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