[PATCH 00/21] Add support for sam9x7 SoC family

[PATCH 00/21] Add support for sam9x7 SoC family

[Varshini Rajendran]

This patch series adds support for the new SoC family - sam9x7.
 - The device tree, configs and drivers are added
 - Clock driver for sam9x7 is added
 - Support for basic peripherals is added

Balamanikandan Gunasundar (1):
  ARM: configs: at91: Enable csi and isc support

Hari Prasath (1):
  irqchip/atmel-aic5: Add support for sam9x7 aic

Nicolas Ferre (1):
  net: macb: add support for gmac to sam9x7

Varshini Rajendran (18):
  dt-bindings: microchip: atmel,at91rm9200-tcb: add sam9x60 compatible
  dt-bindings: usb: ehci: Add atmel at91sam9g45-ehci compatible
  dt-bindings: usb: generic-ehci: Document clock-names property
  ARM: dts: at91: sam9x7: add device tree for soc
  ARM: configs: at91: enable config flags for sam9x7 SoC
  ARM: configs: at91: add mcan support
  ARM: at91: pm: add support for sam9x7 soc family
  ARM: at91: pm: add sam9x7 soc init config
  ARM: at91: Kconfig: add config flag for SAM9X7 SoC
  ARM: at91: add support in soc driver for new sam9x7
  clk: at91: clk-sam9x60-pll: re-factor to support individual core freq
    outputs
  clk: at91: sam9x7: add support for HW PLL freq dividers
  clk: at91: sam9x7: add sam9x7 pmc driver
  dt-bindings: irqchip/atmel-aic5: Add support for sam9x7 aic
  power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7
  power: reset: at91-reset: add reset support for sam9x7 soc
  power: reset: at91-reset: add sdhwc support for sam9x7 soc
  dt-bindings: net: cdns,macb: add documentation for sam9x7 ethernet
    interface

 .../interrupt-controller/atmel,aic.txt        |    2 +-
 .../devicetree/bindings/net/cdns,macb.yaml    |    1 +
 .../soc/microchip/atmel,at91rm9200-tcb.yaml   |    1 +
 .../devicetree/bindings/usb/generic-ehci.yaml |    5 +
 arch/arm/boot/dts/sam9x7.dtsi                 | 1333 +++++++++++++++++
 arch/arm/configs/at91_dt_defconfig            |    8 +
 arch/arm/mach-at91/Kconfig                    |   21 +-
 arch/arm/mach-at91/Makefile                   |    1 +
 arch/arm/mach-at91/generic.h                  |    2 +
 arch/arm/mach-at91/pm.c                       |   35 +
 arch/arm/mach-at91/sam9x7.c                   |   34 +
 drivers/clk/at91/Makefile                     |    1 +
 drivers/clk/at91/clk-sam9x60-pll.c            |   50 +-
 drivers/clk/at91/pmc.h                        |    2 +
 drivers/clk/at91/sam9x60.c                    |    7 +
 drivers/clk/at91/sam9x7.c                     |  947 ++++++++++++
 drivers/clk/at91/sama7g5.c                    |    7 +
 drivers/irqchip/irq-atmel-aic5.c              |   10 +
 drivers/net/ethernet/cadence/macb_main.c      |    1 +
 drivers/power/reset/Kconfig                   |    4 +-
 drivers/power/reset/at91-sama5d2_shdwc.c      |    1 +
 drivers/soc/atmel/soc.c                       |   23 +
 drivers/soc/atmel/soc.h                       |    9 +
 23 files changed, 2489 insertions(+), 16 deletions(-)
 create mode 100644 arch/arm/boot/dts/sam9x7.dtsi
 create mode 100644 arch/arm/mach-at91/sam9x7.c
 create mode 100644 drivers/clk/at91/sam9x7.c

-- 
2.25.1

[PATCH 01/21] dt-bindings: microchip: atmel,at91rm9200-tcb: add sam9x60 compatible

[Varshini Rajendran]

Add sam9x60 compatible string support in the schema file

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 .../devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml  | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
index a46411149571..c70c77a5e8e5 100644
--- a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
@@ -20,6 +20,7 @@ properties:
           - atmel,at91rm9200-tcb
           - atmel,at91sam9x5-tcb
           - atmel,sama5d2-tcb
+          - microchip,sam9x60-tcb
       - const: simple-mfd
       - const: syscon
 
-- 
2.25.1

Re: [PATCH 01/21] dt-bindings: microchip: atmel,at91rm9200-tcb: add sam9x60 compatible

[Krzysztof Kozlowski]

On 03/06/2023 22:02, Varshini Rajendran wrote:
> Add sam9x60 compatible string support in the schema file
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  .../devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml  | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
> index a46411149571..c70c77a5e8e5 100644
> --- a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
> +++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
> @@ -20,6 +20,7 @@ properties:
>            - atmel,at91rm9200-tcb
>            - atmel,at91sam9x5-tcb
>            - atmel,sama5d2-tcb
> +          - microchip,sam9x60-tcb

No wildcards.

Best regards,
Krzysztof

Re: [PATCH 01/21] dt-bindings: microchip: atmel,at91rm9200-tcb: add sam9x60 compatible

[Arnd Bergmann]

On Mon, Jun 5, 2023, at 08:35, Krzysztof Kozlowski wrote:
> On 03/06/2023 22:02, Varshini Rajendran wrote:
>> Add sam9x60 compatible string support in the schema file
>> 
>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>> ---
>>  .../devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml  | 1 +
>>  1 file changed, 1 insertion(+)
>> 
>> diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
>> index a46411149571..c70c77a5e8e5 100644
>> --- a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
>> +++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
>> @@ -20,6 +20,7 @@ properties:
>>            - atmel,at91rm9200-tcb
>>            - atmel,at91sam9x5-tcb
>>            - atmel,sama5d2-tcb
>> +          - microchip,sam9x60-tcb
>
> No wildcards.

sam9x60 is the actual name of the chip, it's no wildcard. For sam9x70,
sam9x72 and sam9x75, I think using sam9x7 as the compatible string
is probably fine, as long as they are actually the same chip. Again,
the 'x' in there is not a wildcard but part of the name.

    Arnd

Re: [PATCH 01/21] dt-bindings: microchip: atmel,at91rm9200-tcb: add sam9x60 compatible

[Krzysztof Kozlowski]

On 05/06/2023 09:04, Arnd Bergmann wrote:
> On Mon, Jun 5, 2023, at 08:35, Krzysztof Kozlowski wrote:
>> On 03/06/2023 22:02, Varshini Rajendran wrote:
>>> Add sam9x60 compatible string support in the schema file
>>>
>>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>>> ---
>>>  .../devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml  | 1 +
>>>  1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
>>> index a46411149571..c70c77a5e8e5 100644
>>> --- a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
>>> +++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
>>> @@ -20,6 +20,7 @@ properties:
>>>            - atmel,at91rm9200-tcb
>>>            - atmel,at91sam9x5-tcb
>>>            - atmel,sama5d2-tcb
>>> +          - microchip,sam9x60-tcb
>>
>> No wildcards.
> 
> sam9x60 is the actual name of the chip, it's no wildcard. For sam9x70,
> sam9x72 and sam9x75, I think using sam9x7 as the compatible string
> is probably fine, as long as they are actually the same chip. Again,
> the 'x' in there is not a wildcard but part of the name.

OK, if that's the case.

Best regards,
Krzysztof

Re: [PATCH 01/21] dt-bindings: microchip: atmel,at91rm9200-tcb: add sam9x60 compatible

[Rob Herring]

On Sun, Jun 04, 2023 at 01:32:23AM +0530, Varshini Rajendran wrote:
> Add sam9x60 compatible string support in the schema file
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  .../devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml  | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 02/21] dt-bindings: usb: ehci: Add atmel at91sam9g45-ehci compatible

[Varshini Rajendran]

Document at91sam9g45-ehci compatible for usb-ehci

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
index 9445764bd8de..7e486cc6cfb8 100644
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
@@ -66,6 +66,7 @@ properties:
           - const: generic-ehci
       - items:
           - enum:
+              - atmel,at91sam9g45-ehci
               - cavium,octeon-6335-ehci
               - ibm,usb-ehci-440epx
               - ibm,usb-ehci-460ex
-- 
2.25.1

Re: [PATCH 02/21] dt-bindings: usb: ehci: Add atmel at91sam9g45-ehci compatible

[Rob Herring]

On Sun, 04 Jun 2023 01:32:24 +0530, Varshini Rajendran wrote:
> Document at91sam9g45-ehci compatible for usb-ehci
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 03/21] dt-bindings: usb: generic-ehci: Document clock-names property

[Varshini Rajendran]

Document the property clock-names in the schema.

It fixes the dtbs_warning,
'clock-names' does not match any of the regexes: 'pinctrl-[0-9]+'

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 Documentation/devicetree/bindings/usb/generic-ehci.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
index 7e486cc6cfb8..542ac26960fc 100644
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
@@ -102,6 +102,10 @@ properties:
         - if a USB DRD channel: first clock should be host and second
           one should be peripheral
 
+  clock-names:
+    minItems: 1
+    maxItems: 4
+
   power-domains:
     maxItems: 1
 
-- 
2.25.1

Re: [PATCH 03/21] dt-bindings: usb: generic-ehci: Document clock-names property

[Conor Dooley]

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Hey Varshini,

On Sun, Jun 04, 2023 at 01:32:25AM +0530, Varshini Rajendran wrote:
> Document the property clock-names in the schema.
> 
> It fixes the dtbs_warning,

s/dtbs_warning/dtbs_check warning/?

> 'clock-names' does not match any of the regexes: 'pinctrl-[0-9]+'

Does this fix a warning currently in the tree, or fix a warning
introduced by some patches in this series? (Or both?)

Cheers,
Conor.

> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  Documentation/devicetree/bindings/usb/generic-ehci.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
> index 7e486cc6cfb8..542ac26960fc 100644
> --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
> +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
> @@ -102,6 +102,10 @@ properties:
>          - if a USB DRD channel: first clock should be host and second
>            one should be peripheral
>  
> +  clock-names:
> +    minItems: 1
> +    maxItems: 4
> +
>    power-domains:
>      maxItems: 1
>  
> -- 
> 2.25.1
>

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Re: [PATCH 03/21] dt-bindings: usb: generic-ehci: Document clock-names property

[Nicolas Ferre]

On 03/06/2023 at 23:15, Conor Dooley wrote:
> Hey Varshini,
> 
> On Sun, Jun 04, 2023 at 01:32:25AM +0530, Varshini Rajendran wrote:
>> Document the property clock-names in the schema.
>>
>> It fixes the dtbs_warning,
> s/dtbs_warning/dtbs_check warning/?
> 
>> 'clock-names' does not match any of the regexes: 'pinctrl-[0-9]+'
> Does this fix a warning currently in the tree, or fix a warning
> introduced by some patches in this series? (Or both?)

Our USB DT pattern is the same on all our newer SoC, to it mustn't be 
introduced by the addition of this one.

Best regards,
   Nicolas

>> Signed-off-by: Varshini Rajendran<varshini.rajendran@microchip.com>
>> ---
>>   Documentation/devicetree/bindings/usb/generic-ehci.yaml | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
>> index 7e486cc6cfb8..542ac26960fc 100644
>> --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
>> +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
>> @@ -102,6 +102,10 @@ properties:
>>           - if a USB DRD channel: first clock should be host and second
>>             one should be peripheral
>>   
>> +  clock-names:
>> +    minItems: 1
>> +    maxItems: 4
>> +
>>     power-domains:
>>       maxItems: 1
>>   
>> -- 
>> 2.25.1

-- 
Nicolas Ferre

Re: [PATCH 03/21] dt-bindings: usb: generic-ehci: Document clock-names property

[Krzysztof Kozlowski]

On 03/06/2023 22:02, Varshini Rajendran wrote:
> Document the property clock-names in the schema.
> 
> It fixes the dtbs_warning,
> 'clock-names' does not match any of the regexes: 'pinctrl-[0-9]+'

You cut too much from the warning. Which target/board?

> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  Documentation/devicetree/bindings/usb/generic-ehci.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
> index 7e486cc6cfb8..542ac26960fc 100644
> --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
> +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
> @@ -102,6 +102,10 @@ properties:
>          - if a USB DRD channel: first clock should be host and second
>            one should be peripheral
>  
> +  clock-names:
> +    minItems: 1
> +    maxItems: 4

Not really, because we want them to be fixed, so you need to list the
items. But it seems this is not needed at all... which boards and
drivers use names?


Best regards,
Krzysztof

[PATCH 04/21] ARM: dts: at91: sam9x7: add device tree for soc

[Varshini Rajendran]

Add device tree file for SAM9X7 SoC family

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
[nicolas.ferre@microchip.com: add support for gmac to sam9x7]
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
[balamanikandan.gunasundar@microchip.com: Add device node csi2host and isc]
Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
---
 arch/arm/boot/dts/sam9x7.dtsi | 1333 +++++++++++++++++++++++++++++++++
 1 file changed, 1333 insertions(+)
 create mode 100644 arch/arm/boot/dts/sam9x7.dtsi

diff --git a/arch/arm/boot/dts/sam9x7.dtsi b/arch/arm/boot/dts/sam9x7.dtsi
new file mode 100644
index 000000000000..f98160182fe6
--- /dev/null
+++ b/arch/arm/boot/dts/sam9x7.dtsi
@@ -0,0 +1,1333 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family
+ *
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
+ */
+
+#include <dt-bindings/clock/at91.h>
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+#include <dt-bindings/pinctrl/at91.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	model = "Microchip SAM9X7 SoC";
+	compatible = "microchip,sam9x7";
+	interrupt-parent = <&aic>;
+
+	aliases {
+		serial0 = &dbgu;
+		gpio0 = &pioA;
+		gpio1 = &pioB;
+		gpio2 = &pioC;
+		gpio3 = &pioD;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,arm926ej-s";
+			device_type = "cpu";
+			reg = <0>;
+		};
+	};
+
+	clocks {
+		slow_xtal: slow_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		main_xtal: main_xtal {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+	};
+
+	sram: sram@300000 {
+		compatible = "mmio-sram";
+		reg = <0x300000 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x300000 0x10000>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		usb0: gadget@500000 {
+			compatible = "microchip,sam9x60-udc";
+			reg = <0x500000 0x100000>,
+			      <0xf803c000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
+			clock-names = "pclk", "hclk";
+			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+			assigned-clock-rates = <480000000>;
+			status = "disabled";
+		};
+
+		ohci0: usb@600000 {
+			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+			reg = <0x600000 0x100000>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
+			clock-names = "ohci_clk", "hclk", "uhpck";
+			status = "disabled";
+		};
+
+		ehci0: usb@700000 {
+			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+			reg = <0x700000 0x100000>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
+			clock-names = "usb_clk", "ehci_clk";
+			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
+			assigned-clock-rates = <480000000>;
+			status = "disabled";
+		};
+
+		sdmmc0: sdio-host@80000000 {
+			compatible = "microchip,sam9x60-sdhci";
+			reg = <0x80000000 0x300>;
+			interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
+			clock-names = "hclock", "multclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
+			assigned-clock-rates = <100000000>;
+			status = "disabled";
+		};
+
+		sdmmc1: sdio-host@90000000 {
+			compatible = "microchip,sam9x60-sdhci";
+			reg = <0x90000000 0x300>;
+			interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
+			clock-names = "hclock", "multclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
+			assigned-clock-rates = <100000000>;
+			status = "disabled";
+		};
+	};
+
+	apb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		flx4: flexcom@f0000000 {
+			compatible = "atmel,sama5d2-flexcom";
+			reg = <0xf0000000 0x200>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0xf0000000 0x800>;
+			status = "disabled";
+
+			uart4: serial@200 {
+				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(8))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(9))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+				clock-names = "usart";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			spi4: spi@400 {
+				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+				reg = <0x400 0x200>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+				clock-names = "spi_clk";
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(8))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(9))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c4: i2c@600 {
+				compatible = "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(8))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(9))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		flx5: flexcom@f0004000 {
+			compatible = "atmel,sama5d2-flexcom";
+			reg = <0xf0004000 0x200>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0xf0004000 0x800>;
+			status = "disabled";
+
+			uart5: serial@200 {
+				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(10))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(11))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+				clock-names = "usart";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			spi5: spi@400 {
+				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+				reg = <0x400 0x200>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+				clock-names = "spi_clk";
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(10))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(11))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c5: i2c@600 {
+				compatible = "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(10))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(11))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		dma0: dma-controller@f0008000 {
+			compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
+			reg = <0xf0008000 0x1000>;
+			interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+			#dma-cells = <1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
+			clock-names = "dma_clk";
+			status = "disabled";
+		};
+
+		ssc: ssc@f0010000 {
+			compatible = "atmel,at91sam9g45-ssc";
+			reg = <0xf0010000 0x4000>;
+			interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
+			dmas = <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(38))>,
+			       <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(39))>;
+			dma-names = "tx", "rx";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
+			clock-names = "pclk";
+		};
+
+		gpu: gfx2d@f0018000 {
+			compatible = "microchip,sam9x60-gfx2d";
+			reg = <0xf0018000 0x4000>;
+			interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 36>;
+			clock-names = "periph_clk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2s: i2s@f001c000 {
+			compatible = "microchip,sam9x60-i2smcc";
+			reg = <0xf001c000 0x100>;
+			interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
+			dmas = <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(36))>,
+			       <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(37))>;
+			dma-names = "tx", "rx";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
+			clock-names = "pclk", "gclk";
+			status = "disabled";
+		};
+
+		flx11: flexcom@f0020000 {
+			compatible = "atmel,sama5d2-flexcom";
+			reg = <0xf0020000 0x200>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0xf0020000 0x800>;
+			status = "disabled";
+
+			uart11: serial@200 {
+				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(22))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(23))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
+				clock-names = "usart";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c11: i2c@600 {
+				compatible = "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(22))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(23))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		flx12: flexcom@f0024000 {
+			compatible = "atmel,sama5d2-flexcom";
+			reg = <0xf0024000 0x200>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0xf0024000 0x800>;
+			status = "disabled";
+
+			uart12: serial@200 {
+				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(24))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(25))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
+				clock-names = "usart";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c12: i2c@600 {
+				compatible = "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(24))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(25))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		pit64b0: timer@f0028000 {
+			compatible = "microchip,sam9x60-pit64b";
+			reg = <0xf0028000 0x100>;
+			interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
+			clock-names = "pclk", "gclk";
+		};
+
+		sha: sha@f002c000 {
+			compatible = "atmel,at91sam9g46-sha";
+			reg = <0xf002c000 0x100>;
+			interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
+			dmas = <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(34))>;
+			dma-names = "tx";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
+			clock-names = "sha_clk";
+		};
+
+		trng: trng@f0030000 {
+			compatible = "microchip,sam9x60-trng";
+			reg = <0xf0030000 0x100>;
+			interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
+			status = "disabled";
+		};
+
+		aes: aes@f0034000 {
+			compatible = "atmel,at91sam9g46-aes";
+			reg = <0xf0034000 0x100>;
+			interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
+			dmas = <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(32))>,
+			       <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(33))>;
+			dma-names = "tx", "rx";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
+			clock-names = "aes_clk";
+		};
+
+		tdes: tdes@f0038000 {
+			compatible = "atmel,at91sam9g46-tdes";
+			reg = <0xf0038000 0x100>;
+			interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
+			dmas = <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(31))>,
+			       <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(30))>;
+			dma-names = "tx", "rx";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
+			clock-names = "tdes_clk";
+		};
+
+		classd: classd@f003c000 {
+			compatible = "atmel,sama5d2-classd";
+			reg = <0xf003c000 0x100>;
+			interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
+			dmas = <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(35))>;
+			dma-names = "tx";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
+			clock-names = "pclk", "gclk";
+			status = "disabled";
+		};
+
+		pit64b1: timer@f0040000 {
+			compatible = "microchip,sam9x60-pit64b";
+			reg = <0xf0040000 0x100>;
+			interrupts = <58 IRQ_TYPE_LEVEL_HIGH 7>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
+			clock-names = "pclk", "gclk";
+		};
+
+		can0: can@f8000000 {
+			compatible = "bosch,m_can";
+			reg = <0xf8000000 0x100>, <0x300000 0x7800>;
+			reg-names = "m_can", "message_ram";
+			interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0
+				      68 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-names = "int0", "int1";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>;
+			clock-names = "hclk", "cclk";
+			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 29>;
+			assigned-clock-rates = <480000000>, <40000000>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
+			bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
+			status = "disabled";
+		};
+
+		can1: can@f8004000 {
+			compatible = "bosch,m_can";
+			reg = <0xf8004000 0x100>, <0x300000 0xbc00>;
+			reg-names = "m_can", "message_ram";
+			interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0
+				      69 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-names = "int0", "int1";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>;
+			clock-names = "hclk", "cclk";
+			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 30>;
+			assigned-clock-rates = <480000000>, <40000000>;
+			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
+			bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
+			status = "disabled";
+		};
+
+		tcb: timer@f8008000 {
+			compatible = "microchip,sam9x60-tcb", "simple-mfd", "syscon";
+			reg = <0xf8008000 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
+			clock-names = "t0_clk", "slow_clk";
+			status = "disabled";
+		};
+
+		flx6: flexcom@f8010000 {
+			compatible = "atmel,sama5d2-flexcom";
+			reg = <0xf8010000 0x200>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0xf8010000 0x800>;
+			status = "disabled";
+
+			uart6: serial@200 {
+				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(12))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(13))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+				clock-names = "usart";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c6: i2c@600 {
+				compatible = "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(12))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(13))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		flx7: flexcom@f8014000 {
+			compatible = "atmel,sama5d2-flexcom";
+			reg = <0xf8014000 0x200>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0xf8014000 0x800>;
+			status = "disabled";
+
+			uart7: serial@200 {
+				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(14))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(15))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
+				clock-names = "usart";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c7: i2c@600 {
+				compatible = "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(14))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(15))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		flx8: flexcom@f8018000 {
+			compatible = "atmel,sama5d2-flexcom";
+			reg = <0xf8018000 0x200>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0xf8018000 0x800>;
+			status = "disabled";
+
+			uart8: serial@200 {
+				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(16))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(17))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
+				clock-names = "usart";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c8: i2c@600 {
+				compatible = "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(16))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(17))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		flx0: flexcom@f801c000 {
+			compatible = "atmel,sama5d2-flexcom";
+			reg = <0xf801c000 0x200>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0xf801c000 0x800>;
+			status = "disabled";
+
+			uart0: serial@200 {
+				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(0))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(1))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+				clock-names = "usart";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			spi0: spi@400 {
+				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+				reg = <0x400 0x200>;
+				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+				clock-names = "spi_clk";
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(0))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(1))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c0: i2c@600 {
+				compatible = "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(0))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(1))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		flx1: flexcom@f8020000 {
+			compatible = "atmel,sama5d2-flexcom";
+			reg = <0xf8020000 0x200>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0xf8020000 0x800>;
+			status = "disabled";
+
+			uart1: serial@200 {
+				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(2))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(3))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+				clock-names = "usart";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			spi1: spi@400 {
+				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+				reg = <0x400 0x200>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+				clock-names = "spi_clk";
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(2))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(3))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@600 {
+				compatible = "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(2))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(3))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		flx2: flexcom@f8024000 {
+			compatible = "atmel,sama5d2-flexcom";
+			reg = <0xf8024000 0x200>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0xf8024000 0x800>;
+			status = "disabled";
+
+			uart2: serial@200 {
+				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(4))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(5))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+				clock-names = "usart";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			spi2: spi@400 {
+				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+				reg = <0x400 0x200>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+				clock-names = "spi_clk";
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(4))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(5))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c2: i2c@600 {
+				compatible = "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(4))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(5))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		flx3: flexcom@f8028000 {
+			compatible = "atmel,sama5d2-flexcom";
+			reg = <0xf8028000 0x200>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0xf8028000 0x800>;
+			status = "disabled";
+
+			uart3: serial@200 {
+				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(6))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(7))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+				clock-names = "usart";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			spi3: spi@400 {
+				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
+				reg = <0x400 0x200>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+				clock-names = "spi_clk";
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(6))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(7))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@600 {
+				compatible = "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(6))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(7))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		gmac: ethernet@f802c000 {
+			compatible = "microchip,sam9x7-gem";
+			reg = <0xf802c000 0x1000>;
+			interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3		/* Queue 0 */
+				      60 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 1 */
+				      61 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 2 */
+				      62 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 3 */
+				      63 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 4 */
+				      64 IRQ_TYPE_LEVEL_HIGH 3>;        /* Queue 5 */
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
+			clock-names = "hclk", "pclk";
+			status = "disabled";
+		};
+
+		flx9: flexcom@f8040000 {
+			compatible = "atmel,sama5d2-flexcom";
+			reg = <0xf8040000 0x200>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0xf8040000 0x800>;
+			status = "disabled";
+
+			uart9: serial@200 {
+				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(18))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(19))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
+				clock-names = "usart";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c9: i2c@600 {
+				compatible = "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(18))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(19))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		flx10: flexcom@f8044000 {
+			compatible = "atmel,sama5d2-flexcom";
+			reg = <0xf8044000 0x200>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0xf8044000 0x800>;
+			status = "disabled";
+
+			uart10: serial@200 {
+				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
+				reg = <0x200 0x200>;
+				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(20))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(21))>;
+				dma-names = "tx", "rx";
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
+				clock-names = "usart";
+				atmel,use-dma-rx;
+				atmel,use-dma-tx;
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+
+			i2c10: i2c@600 {
+				compatible = "microchip,sam9x60-i2c";
+				reg = <0x600 0x200>;
+				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
+				dmas = <&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(20))>,
+					<&dma0
+					(AT91_XDMAC_DT_MEM_IF(0) |
+					 AT91_XDMAC_DT_PER_IF(1) |
+					 AT91_XDMAC_DT_PERID(21))>;
+				dma-names = "tx", "rx";
+				atmel,fifo-size = <16>;
+				status = "disabled";
+			};
+		};
+
+		xisc: xisc@f8048000 {
+			compatible = "microchip,sama7g5-isc";
+			reg = <0xf8048000 0x2000>;
+			interrupts = <43 IRQ_TYPE_LEVEL_HIGH 7>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
+			clock-names = "hclock";
+			#clock-cells = <0>;
+			clock-output-names = "isc-mck";
+			status = "disabled";
+
+			port {
+				xisc_in: endpoint {
+					bus-width = <14>;
+					hsync-active = <1>;
+					vsync-active = <1>;
+					remote-endpoint = <&csi2dc_out>;
+				};
+			};
+		};
+
+		sfr: sfr@f8050000 {
+			compatible = "microchip,sam9x60-sfr", "syscon";
+			reg = <0xf8050000 0x100>;
+		};
+
+		csi2host: csi2host@f8058000 {
+			compatible = "snps,dw-csi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xf8058000 0x7FF>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 53>, <&pmc PMC_TYPE_GCK 55>;
+			clock-names = "perclk", "phyclk";
+			assigned-clocks = <&pmc PMC_TYPE_GCK 55>;
+			assigned-clock-rates = <26600000>;
+			snps,output-type = <1>;
+			phys = <&csi_dphy>;
+			status = "disabled";
+
+			port@1 {
+				reg = <1>;
+				csi2host_in: endpoint {
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+				csi2host_out: endpoint {
+				};
+			};
+		};
+
+		csi_dphy: dphy@f8058040 {
+			compatible = "snps,dw-dphy-rx";
+			#phy-cells = <0>;
+			bus-width = <8>;
+			snps,dphy-frequency = <900000>;
+			snps,phy_type = <0>;
+			reg = <0xf8058040 0x20>;
+			status = "disabled";
+		};
+
+		csi2dc: csi2dc@f805c000 {
+			compatible = "microchip,sama7g5-csi2dc";
+			reg = <0xf805c000 0x500>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&xisc>;
+			clock-names = "pclk", "scck";
+			assigned-clocks = <&xisc>;
+			assigned-clock-rates = <266000000>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				port@0 {
+					reg = <0>;
+					csi2dc_in: endpoint {
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					csi2dc_out: endpoint {
+						bus-width = <14>;
+						hsync-active = <1>;
+						vsync-active = <1>;
+						remote-endpoint = <&xisc_in>;
+					};
+				};
+			};
+		};
+
+		matrix: matrix@ffffde00 {
+			compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
+			reg = <0xffffde00 0x200>;
+		};
+
+		pmecc: ecc-engine@ffffe000 {
+			compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
+			reg = <0xffffe000 0x300>,
+			      <0xffffe600 0x100>;
+		};
+
+		mpddrc: mpddrc@ffffe800 {
+			compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
+			reg = <0xffffe800 0x200>;
+			clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
+			clock-names = "ddrck", "mpddr";
+		};
+
+		smc: smc@ffffea00 {
+			compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
+			reg = <0xffffea00 0x100>;
+		};
+
+		aic: interrupt-controller@fffff100 {
+			compatible = "microchip,sam9x7-aic";
+			reg = <0xfffff100 0x100>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			atmel,external-irqs = <31>;
+		};
+
+		dbgu: serial@fffff200 {
+			compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
+			reg = <0xfffff200 0x200>;
+			interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
+			dmas = <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(28))>,
+			       <&dma0
+				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+				 AT91_XDMAC_DT_PERID(29))>;
+			dma-names = "tx", "rx";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
+			clock-names = "usart";
+			status = "disabled";
+		};
+
+		pinctrl: pinctrl@fffff400 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-mfd";
+			ranges = <0xfffff400 0xfffff400 0x800>;
+
+			/* mux-mask corresponding to sam9x7 SoC in TFBGA228L package */
+			atmel,mux-mask = <
+					 /*  A		B	   C	      D	  */
+					 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000	/* pioA */
+					 0x07ffffff 0x0805fe7f 0x01ff9f80 0x06078000	/* pioB */
+					 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000	/* pioC */
+					 0x00003fff 0x00003fe0 0x0000003f 0x00000000	/* pioD */
+					 >;
+
+			pioA: gpio@fffff400 {
+				compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+				reg = <0xfffff400 0x200>;
+				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+			};
+
+			pioB: gpio@fffff600 {
+				compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+				reg = <0xfffff600 0x200>;
+				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				#gpio-lines = <26>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
+			};
+
+			pioC: gpio@fffff800 {
+				compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+				reg = <0xfffff800 0x200>;
+				interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
+			};
+
+			pioD: gpio@fffffa00 {
+				compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+				reg = <0xfffffa00 0x200>;
+				interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
+				#gpio-cells = <2>;
+				gpio-controller;
+				#gpio-lines = <22>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
+			};
+		};
+
+		pmc: pmc@fffffc00 {
+			compatible = "microchip,sam9x7-pmc", "syscon";
+			reg = <0xfffffc00 0x200>;
+			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+			#clock-cells = <2>;
+			clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
+			clock-names = "td_slck", "md_slck", "main_xtal";
+		};
+
+		reset_controller: rstc@fffffe00 {
+			compatible = "microchip,sam9x60-rstc";
+			reg = <0xfffffe00 0x10>;
+			clocks = <&clk32k 0>;
+		};
+
+		shutdown_controller: shdwc@fffffe10 {
+			compatible = "microchip,sam9x60-shdwc";
+			reg = <0xfffffe10 0x10>;
+			clocks = <&clk32k 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			atmel,wakeup-rtc-timer;
+			atmel,wakeup-rtt-timer;
+			status = "disabled";
+		};
+
+		rtt: rtc@fffffe20 {
+			compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
+			reg = <0xfffffe20 0x20>;
+			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+			clocks = <&clk32k 0>;
+		};
+
+		clk32k: sckc@fffffe50 {
+			compatible = "microchip,sam9x60-sckc";
+			reg = <0xfffffe50 0x4>;
+			clocks = <&slow_xtal>;
+			#clock-cells = <1>;
+		};
+
+		gpbr: syscon@fffffe60 {
+			compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
+			reg = <0xfffffe60 0x10>;
+		};
+
+		rtc: rtc@fffffea8 {
+			compatible = "microchip,sam9x60-rtc";
+			reg = <0xfffffea8 0x100>;
+			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+			clocks = <&clk32k 0>;
+		};
+
+		watchdog: watchdog@ffffff80 {
+			compatible = "microchip,sam9x60-wdt";
+			reg = <0xffffff80 0x24>;
+			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+			clocks = <&clk32k 0>;
+			status = "disabled";
+		};
+	};
+};
-- 
2.25.1

Re: [PATCH 04/21] ARM: dts: at91: sam9x7: add device tree for soc

[Conor Dooley]

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Hey Varshini,

On Sun, Jun 04, 2023 at 01:32:26AM +0530, Varshini Rajendran wrote:
> Add device tree file for SAM9X7 SoC family
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> [nicolas.ferre@microchip.com: add support for gmac to sam9x7]

Please just replace these [] things with a Co-developed-by.

> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> [balamanikandan.gunasundar@microchip.com: Add device node csi2host and isc]
> Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
> ---
>  arch/arm/boot/dts/sam9x7.dtsi | 1333 +++++++++++++++++++++++++++++++++
>  1 file changed, 1333 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sam9x7.dtsi
> 
> diff --git a/arch/arm/boot/dts/sam9x7.dtsi b/arch/arm/boot/dts/sam9x7.dtsi
> new file mode 100644
> index 000000000000..f98160182fe6
> --- /dev/null
> +++ b/arch/arm/boot/dts/sam9x7.dtsi
> @@ -0,0 +1,1333 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family
> + *
> + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
> + */
> +
> +#include <dt-bindings/clock/at91.h>
> +#include <dt-bindings/dma/at91.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/mfd/atmel-flexcom.h>
> +#include <dt-bindings/pinctrl/at91.h>
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	model = "Microchip SAM9X7 SoC";
> +	compatible = "microchip,sam9x7";

Unless I am mistaken, sam9x7 is a family, not an soc. I'll have to
defer to Nicolas or someone that actually properly understands the
naming scheme here though! It's certainly odd to use sam9x7 here, when
the file is filled with references to sam9x60, which is a soc-specific
compatible.

Either way, the compatible is undocumented as far as I can tell and I
assume that this was not actually tested, since there doesn't appear
to be any dts including this file and therefore no way to build it?

> +	interrupt-parent = <&aic>;
> +
> +	aliases {
> +		serial0 = &dbgu;
> +		gpio0 = &pioA;
> +		gpio1 = &pioB;
> +		gpio2 = &pioC;
> +		gpio3 = &pioD;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			compatible = "arm,arm926ej-s";
> +			device_type = "cpu";
> +			reg = <0>;
> +		};
> +	};
> +
> +	clocks {
> +		slow_xtal: slow_xtal {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +
> +		main_xtal: main_xtal {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +	};
> +
> +	sram: sram@300000 {
> +		compatible = "mmio-sram";
> +		reg = <0x300000 0x10000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0x300000 0x10000>;
> +	};
> +
> +	ahb {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		usb0: gadget@500000 {
> +			compatible = "microchip,sam9x60-udc";

This is not a sam9x60, so it should not only have that SoC's compatible
here. Ideally, "microchip,sam9x7{0,2,5}" with the sam9x60 one as a
fallback.

> +			reg = <0x500000 0x100000>,
> +			      <0xf803c000 0x400>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			clock-names = "pclk", "hclk";
> +			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			assigned-clock-rates = <480000000>;
> +			status = "disabled";
> +		};
> +
> +		ohci0: usb@600000 {
> +			compatible = "atmel,at91rm9200-ohci", "usb-ohci";

Ditto here.

> +			reg = <0x600000 0x100000>;
> +			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
> +			clock-names = "ohci_clk", "hclk", "uhpck";
> +			status = "disabled";
> +		};
> +
> +		ehci0: usb@700000 {
> +			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";

And here.

> +			reg = <0x700000 0x100000>;
> +			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
> +			clock-names = "usb_clk", "ehci_clk";
> +			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			assigned-clock-rates = <480000000>;
> +			status = "disabled";
> +		};
> +
> +		sdmmc0: sdio-host@80000000 {
> +			compatible = "microchip,sam9x60-sdhci";

And here.

> +			reg = <0x80000000 0x300>;
> +			interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
> +			clock-names = "hclock", "multclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +		};
> +
> +		sdmmc1: sdio-host@90000000 {
> +			compatible = "microchip,sam9x60-sdhci";

There's no point me typing it every time, but ditto the whole way
through this file ;)

Cheers,
Conor.

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Re: [PATCH 04/21] ARM: dts: at91: sam9x7: add device tree for soc

[Krzysztof Kozlowski]

On 03/06/2023 22:02, Varshini Rajendran wrote:
> Add device tree file for SAM9X7 SoC family
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> [nicolas.ferre@microchip.com: add support for gmac to sam9x7]
> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> [balamanikandan.gunasundar@microchip.com: Add device node csi2host and isc]
> Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
> ---
>  arch/arm/boot/dts/sam9x7.dtsi | 1333 +++++++++++++++++++++++++++++++++
>  1 file changed, 1333 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sam9x7.dtsi
> 
> diff --git a/arch/arm/boot/dts/sam9x7.dtsi b/arch/arm/boot/dts/sam9x7.dtsi
> new file mode 100644
> index 000000000000..f98160182fe6
> --- /dev/null
> +++ b/arch/arm/boot/dts/sam9x7.dtsi
> @@ -0,0 +1,1333 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family
> + *
> + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
> + */
> +
> +#include <dt-bindings/clock/at91.h>
> +#include <dt-bindings/dma/at91.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/mfd/atmel-flexcom.h>
> +#include <dt-bindings/pinctrl/at91.h>
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	model = "Microchip SAM9X7 SoC";
> +	compatible = "microchip,sam9x7";
> +	interrupt-parent = <&aic>;
> +
> +	aliases {
> +		serial0 = &dbgu;
> +		gpio0 = &pioA;
> +		gpio1 = &pioB;
> +		gpio2 = &pioC;
> +		gpio3 = &pioD;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			compatible = "arm,arm926ej-s";
> +			device_type = "cpu";
> +			reg = <0>;
> +		};
> +	};
> +
> +	clocks {
> +		slow_xtal: slow_xtal {

No underscores in node names. Use some common prefix or suffix, e.g. clock-

> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +
> +		main_xtal: main_xtal {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +	};
> +
> +	sram: sram@300000 {
> +		compatible = "mmio-sram";
> +		reg = <0x300000 0x10000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0x300000 0x10000>;
> +	};
> +
> +	ahb {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		usb0: gadget@500000 {
> +			compatible = "microchip,sam9x60-udc";

Aren't you missing specific compatible? This applies everywhere.

> +			reg = <0x500000 0x100000>,
> +			      <0xf803c000 0x400>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			clock-names = "pclk", "hclk";
> +			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			assigned-clock-rates = <480000000>;
> +			status = "disabled";
> +		};
> +
> +		ohci0: usb@600000 {
> +			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
> +			reg = <0x600000 0x100000>;
> +			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
> +			clock-names = "ohci_clk", "hclk", "uhpck";
> +			status = "disabled";
> +		};
> +
> +		ehci0: usb@700000 {
> +			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
> +			reg = <0x700000 0x100000>;
> +			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
> +			clock-names = "usb_clk", "ehci_clk";
> +			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			assigned-clock-rates = <480000000>;
> +			status = "disabled";
> +		};
> +
> +		sdmmc0: sdio-host@80000000 {

Are you sure you have no dtbs_check warnings for this?

> +			compatible = "microchip,sam9x60-sdhci";
> +			reg = <0x80000000 0x300>;
> +			interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
> +			clock-names = "hclock", "multclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +		};
> +
> +		sdmmc1: sdio-host@90000000 {
> +			compatible = "microchip,sam9x60-sdhci";
> +			reg = <0x90000000 0x300>;
> +			interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
> +			clock-names = "hclock", "multclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +		};
> +	};
> +
> +	apb {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		flx4: flexcom@f0000000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf0000000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf0000000 0x800>;
> +			status = "disabled";
> +
> +			uart4: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(8))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(9))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi4: spi@400 {
> +				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(8))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(9))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c4: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(8))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(9))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx5: flexcom@f0004000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf0004000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf0004000 0x800>;
> +			status = "disabled";
> +
> +			uart5: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(10))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(11))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi5: spi@400 {
> +				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(10))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(11))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c5: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(10))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(11))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		dma0: dma-controller@f0008000 {
> +			compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
> +			reg = <0xf0008000 0x1000>;
> +			interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
> +			#dma-cells = <1>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
> +			clock-names = "dma_clk";
> +			status = "disabled";
> +		};
> +
> +		ssc: ssc@f0010000 {
> +			compatible = "atmel,at91sam9g45-ssc";
> +			reg = <0xf0010000 0x4000>;
> +			interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(38))>,
> +			       <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(39))>;
> +			dma-names = "tx", "rx";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
> +			clock-names = "pclk";
> +		};
> +
> +		gpu: gfx2d@f0018000 {
> +			compatible = "microchip,sam9x60-gfx2d";
> +			reg = <0xf0018000 0x4000>;
> +			interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 36>;
> +			clock-names = "periph_clk";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2s: i2s@f001c000 {
> +			compatible = "microchip,sam9x60-i2smcc";
> +			reg = <0xf001c000 0x100>;
> +			interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(36))>,
> +			       <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(37))>;
> +			dma-names = "tx", "rx";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
> +			clock-names = "pclk", "gclk";
> +			status = "disabled";
> +		};
> +
> +		flx11: flexcom@f0020000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf0020000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf0020000 0x800>;
> +			status = "disabled";
> +
> +			uart11: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(22))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(23))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c11: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(22))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(23))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx12: flexcom@f0024000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf0024000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf0024000 0x800>;
> +			status = "disabled";
> +
> +			uart12: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(24))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(25))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c12: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(24))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(25))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		pit64b0: timer@f0028000 {
> +			compatible = "microchip,sam9x60-pit64b";
> +			reg = <0xf0028000 0x100>;
> +			interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
> +			clock-names = "pclk", "gclk";
> +		};
> +
> +		sha: sha@f002c000 {
> +			compatible = "atmel,at91sam9g46-sha";
> +			reg = <0xf002c000 0x100>;
> +			interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(34))>;
> +			dma-names = "tx";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
> +			clock-names = "sha_clk";
> +		};
> +
> +		trng: trng@f0030000 {

rng@

> +			compatible = "microchip,sam9x60-trng";
> +			reg = <0xf0030000 0x100>;
> +			interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
> +			status = "disabled";
> +		};
> +
> +		aes: aes@f0034000 {

crypto@

> +			compatible = "atmel,at91sam9g46-aes";
> +			reg = <0xf0034000 0x100>;
> +			interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(32))>,
> +			       <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(33))>;
> +			dma-names = "tx", "rx";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
> +			clock-names = "aes_clk";
> +		};
> +
> +		tdes: tdes@f0038000 {

crypto@


Best regards,
Krzysztof

Re: [PATCH 04/21] ARM: dts: at91: sam9x7: add device tree for soc

[Krzysztof Kozlowski]

On 03/06/2023 22:02, Varshini Rajendran wrote:
> Add device tree file for SAM9X7 SoC family
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> [nicolas.ferre@microchip.com: add support for gmac to sam9x7]
> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> [balamanikandan.gunasundar@microchip.com: Add device node csi2host and isc]
> Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
> ---
>  arch/arm/boot/dts/sam9x7.dtsi | 1333 +++++++++++++++++++++++++++++++++
>  1 file changed, 1333 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sam9x7.dtsi

How do you even test it? Where are boards and their bindings?

Best regards,
Krzysztof

Re: [PATCH 04/21] ARM: dts: at91: sam9x7: add device tree for soc

[Dharma.B]

On 04/06/23 1:32 am, Varshini Rajendran wrote:
> Add device tree file for SAM9X7 SoC family
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> [nicolas.ferre@microchip.com: add support for gmac to sam9x7]
> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> [balamanikandan.gunasundar@microchip.com: Add device node csi2host and isc]
> Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
> ---
>   arch/arm/boot/dts/sam9x7.dtsi | 1333 +++++++++++++++++++++++++++++++++
>   1 file changed, 1333 insertions(+)
>   create mode 100644 arch/arm/boot/dts/sam9x7.dtsi
> 
> diff --git a/arch/arm/boot/dts/sam9x7.dtsi b/arch/arm/boot/dts/sam9x7.dtsi
> new file mode 100644
> index 000000000000..f98160182fe6
> --- /dev/null
> +++ b/arch/arm/boot/dts/sam9x7.dtsi
> @@ -0,0 +1,1333 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family
> + *
> + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
> + */
> +
> +#include <dt-bindings/clock/at91.h>
> +#include <dt-bindings/dma/at91.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/mfd/atmel-flexcom.h>
> +#include <dt-bindings/pinctrl/at91.h>
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	model = "Microchip SAM9X7 SoC";
> +	compatible = "microchip,sam9x7";
> +	interrupt-parent = <&aic>;
> +
> +	aliases {
> +		serial0 = &dbgu;
> +		gpio0 = &pioA;
> +		gpio1 = &pioB;
> +		gpio2 = &pioC;
> +		gpio3 = &pioD;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			compatible = "arm,arm926ej-s";
> +			device_type = "cpu";
> +			reg = <0>;
> +		};
> +	};
> +
> +	clocks {
> +		slow_xtal: slow_xtal {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +
> +		main_xtal: main_xtal {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +	};
> +
> +	sram: sram@300000 {
> +		compatible = "mmio-sram";
> +		reg = <0x300000 0x10000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0x300000 0x10000>;
> +	};
> +
> +	ahb {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		usb0: gadget@500000 {
> +			compatible = "microchip,sam9x60-udc";
> +			reg = <0x500000 0x100000>,
> +			      <0xf803c000 0x400>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			clock-names = "pclk", "hclk";
> +			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			assigned-clock-rates = <480000000>;
> +			status = "disabled";
> +		};
> +
> +		ohci0: usb@600000 {
> +			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
> +			reg = <0x600000 0x100000>;
> +			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
> +			clock-names = "ohci_clk", "hclk", "uhpck";
> +			status = "disabled";
> +		};
> +
> +		ehci0: usb@700000 {
> +			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
> +			reg = <0x700000 0x100000>;
> +			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
> +			clock-names = "usb_clk", "ehci_clk";
> +			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			assigned-clock-rates = <480000000>;
> +			status = "disabled";
> +		};
> +
> +		sdmmc0: sdio-host@80000000 {
> +			compatible = "microchip,sam9x60-sdhci";
> +			reg = <0x80000000 0x300>;
> +			interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
> +			clock-names = "hclock", "multclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +		};
> +
> +		sdmmc1: sdio-host@90000000 {
> +			compatible = "microchip,sam9x60-sdhci";
> +			reg = <0x90000000 0x300>;
> +			interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
> +			clock-names = "hclock", "multclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +		};
> +	};
> +
> +	apb {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		flx4: flexcom@f0000000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf0000000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf0000000 0x800>;
> +			status = "disabled";
> +
> +			uart4: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(8))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(9))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi4: spi@400 {
> +				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(8))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(9))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c4: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(8))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(9))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx5: flexcom@f0004000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf0004000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf0004000 0x800>;
> +			status = "disabled";
> +
> +			uart5: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(10))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(11))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi5: spi@400 {
> +				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(10))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(11))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c5: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(10))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(11))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		dma0: dma-controller@f0008000 {
> +			compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
> +			reg = <0xf0008000 0x1000>;
> +			interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
> +			#dma-cells = <1>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
> +			clock-names = "dma_clk";
> +			status = "disabled";
> +		};
> +
> +		ssc: ssc@f0010000 {
> +			compatible = "atmel,at91sam9g45-ssc";
> +			reg = <0xf0010000 0x4000>;
> +			interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(38))>,
> +			       <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(39))>;
> +			dma-names = "tx", "rx";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
> +			clock-names = "pclk";
> +		};
> +
> +		gpu: gfx2d@f0018000 {
> +			compatible = "microchip,sam9x60-gfx2d";
> +			reg = <0xf0018000 0x4000>;
> +			interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 36>;
> +			clock-names = "periph_clk";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		i2s: i2s@f001c000 {
> +			compatible = "microchip,sam9x60-i2smcc";
> +			reg = <0xf001c000 0x100>;
> +			interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(36))>,
> +			       <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(37))>;
> +			dma-names = "tx", "rx";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
> +			clock-names = "pclk", "gclk";
> +			status = "disabled";
> +		};
> +
> +		flx11: flexcom@f0020000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf0020000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf0020000 0x800>;
> +			status = "disabled";
> +
> +			uart11: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(22))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(23))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c11: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(22))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(23))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx12: flexcom@f0024000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf0024000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf0024000 0x800>;
> +			status = "disabled";
> +
> +			uart12: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(24))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(25))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c12: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(24))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(25))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		pit64b0: timer@f0028000 {
> +			compatible = "microchip,sam9x60-pit64b";
> +			reg = <0xf0028000 0x100>;
> +			interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
> +			clock-names = "pclk", "gclk";
> +		};
> +
> +		sha: sha@f002c000 {
> +			compatible = "atmel,at91sam9g46-sha";
> +			reg = <0xf002c000 0x100>;
> +			interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(34))>;
> +			dma-names = "tx";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
> +			clock-names = "sha_clk";
> +		};
> +
> +		trng: trng@f0030000 {
> +			compatible = "microchip,sam9x60-trng";
> +			reg = <0xf0030000 0x100>;
> +			interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
> +			status = "disabled";
> +		};
> +
> +		aes: aes@f0034000 {
> +			compatible = "atmel,at91sam9g46-aes";
> +			reg = <0xf0034000 0x100>;
> +			interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(32))>,
> +			       <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(33))>;
> +			dma-names = "tx", "rx";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
> +			clock-names = "aes_clk";
> +		};
> +
> +		tdes: tdes@f0038000 {
> +			compatible = "atmel,at91sam9g46-tdes";
> +			reg = <0xf0038000 0x100>;
> +			interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(31))>,
> +			       <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(30))>;
> +			dma-names = "tx", "rx";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
> +			clock-names = "tdes_clk";
> +		};
> +
> +		classd: classd@f003c000 {
> +			compatible = "atmel,sama5d2-classd";
> +			reg = <0xf003c000 0x100>;
> +			interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(35))>;
> +			dma-names = "tx";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
> +			clock-names = "pclk", "gclk";
> +			status = "disabled";
> +		};
> +
> +		pit64b1: timer@f0040000 {
> +			compatible = "microchip,sam9x60-pit64b";
> +			reg = <0xf0040000 0x100>;
> +			interrupts = <58 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
> +			clock-names = "pclk", "gclk";
> +		};
> +
> +		can0: can@f8000000 {
> +			compatible = "bosch,m_can";
> +			reg = <0xf8000000 0x100>, <0x300000 0x7800>;
> +			reg-names = "m_can", "message_ram";
> +			interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0
> +				      68 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "int0", "int1";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>;
> +			clock-names = "hclk", "cclk";
> +			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 29>;
> +			assigned-clock-rates = <480000000>, <40000000>;
> +			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
> +			status = "disabled";
> +		};
> +
> +		can1: can@f8004000 {
> +			compatible = "bosch,m_can";
> +			reg = <0xf8004000 0x100>, <0x300000 0xbc00>;
> +			reg-names = "m_can", "message_ram";
> +			interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0
> +				      69 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "int0", "int1";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>;
> +			clock-names = "hclk", "cclk";
> +			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 30>;
> +			assigned-clock-rates = <480000000>, <40000000>;
> +			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
> +			status = "disabled";
> +		};
> +
> +		tcb: timer@f8008000 {
There are two timer counter blocks available in sam9x7 series so two 
nodes "tcb0: timer@f8008000 and tcb1: timer@f800c000" with interrupts 17 
and 45" have to be defined here.
> +			compatible = "microchip,sam9x60-tcb", "simple-mfd", "syscoFix the compatible string to "atmel,sama5d2-tcb". 
"microchip,sam9x60-tcb" is no longer used.
> +			reg = <0xf8008000 0x100>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
> +			clock-names = "t0_clk", "slow_clk";
> +			status = "disabled";
> +		};
> +
> +		flx6: flexcom@f8010000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf8010000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf8010000 0x800>;
> +			status = "disabled";
> +
> +			uart6: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(12))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(13))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c6: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(12))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(13))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx7: flexcom@f8014000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf8014000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf8014000 0x800>;
> +			status = "disabled";
> +
> +			uart7: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(14))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(15))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c7: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(14))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(15))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx8: flexcom@f8018000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf8018000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf8018000 0x800>;
> +			status = "disabled";
> +
> +			uart8: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(16))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(17))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c8: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(16))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(17))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx0: flexcom@f801c000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf801c000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf801c000 0x800>;
> +			status = "disabled";
> +
> +			uart0: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(0))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(1))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi0: spi@400 {
> +				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(0))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(1))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c0: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(0))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(1))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx1: flexcom@f8020000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf8020000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf8020000 0x800>;
> +			status = "disabled";
> +
> +			uart1: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(2))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(3))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi1: spi@400 {
> +				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(2))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(3))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c1: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(2))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(3))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx2: flexcom@f8024000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf8024000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf8024000 0x800>;
> +			status = "disabled";
> +
> +			uart2: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(4))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(5))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi2: spi@400 {
> +				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(4))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(5))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c2: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(4))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(5))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx3: flexcom@f8028000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf8028000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf8028000 0x800>;
> +			status = "disabled";
> +
> +			uart3: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(6))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(7))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi3: spi@400 {
> +				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(6))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(7))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c3: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(6))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(7))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		gmac: ethernet@f802c000 {
> +			compatible = "microchip,sam9x7-gem";
> +			reg = <0xf802c000 0x1000>;
> +			interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3		/* Queue 0 */
> +				      60 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 1 */
> +				      61 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 2 */
> +				      62 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 3 */
> +				      63 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 4 */
> +				      64 IRQ_TYPE_LEVEL_HIGH 3>;        /* Queue 5 */
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
> +			clock-names = "hclk", "pclk";
> +			status = "disabled";
> +		};
> +
> +		flx9: flexcom@f8040000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf8040000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf8040000 0x800>;
> +			status = "disabled";
> +
> +			uart9: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(18))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(19))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c9: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(18))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(19))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx10: flexcom@f8044000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf8044000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf8044000 0x800>;
> +			status = "disabled";
> +
> +			uart10: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(20))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(21))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c10: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(20))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(21))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		xisc: xisc@f8048000 {
> +			compatible = "microchip,sama7g5-isc";
> +			reg = <0xf8048000 0x2000>;
> +			interrupts = <43 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
> +			clock-names = "hclock";
> +			#clock-cells = <0>;
> +			clock-output-names = "isc-mck";
> +			status = "disabled";
> +
> +			port {
> +				xisc_in: endpoint {
> +					bus-width = <14>;
> +					hsync-active = <1>;
> +					vsync-active = <1>;
> +					remote-endpoint = <&csi2dc_out>;
> +				};
> +			};
> +		};
> +
> +		sfr: sfr@f8050000 {
> +			compatible = "microchip,sam9x60-sfr", "syscon";
> +			reg = <0xf8050000 0x100>;
> +		};
> +
> +		csi2host: csi2host@f8058000 {
> +			compatible = "snps,dw-csi";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0xf8058000 0x7FF>;
> +			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 53>, <&pmc PMC_TYPE_GCK 55>;
> +			clock-names = "perclk", "phyclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 55>;
> +			assigned-clock-rates = <26600000>;
> +			snps,output-type = <1>;
> +			phys = <&csi_dphy>;
> +			status = "disabled";
> +
> +			port@1 {
> +				reg = <1>;
> +				csi2host_in: endpoint {
> +				};
> +			};
> +
> +			port@2 {
> +				reg = <2>;
> +				csi2host_out: endpoint {
> +				};
> +			};
> +		};
> +
> +		csi_dphy: dphy@f8058040 {
> +			compatible = "snps,dw-dphy-rx";
> +			#phy-cells = <0>;
> +			bus-width = <8>;
> +			snps,dphy-frequency = <900000>;
> +			snps,phy_type = <0>;
> +			reg = <0xf8058040 0x20>;
> +			status = "disabled";
> +		};
> +
> +		csi2dc: csi2dc@f805c000 {
> +			compatible = "microchip,sama7g5-csi2dc";
> +			reg = <0xf805c000 0x500>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&xisc>;
> +			clock-names = "pclk", "scck";
> +			assigned-clocks = <&xisc>;
> +			assigned-clock-rates = <266000000>;
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				port@0 {
> +					reg = <0>;
> +					csi2dc_in: endpoint {
> +					};
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +					csi2dc_out: endpoint {
> +						bus-width = <14>;
> +						hsync-active = <1>;
> +						vsync-active = <1>;
> +						remote-endpoint = <&xisc_in>;
> +					};
> +				};
> +			};
> +		};
> +
> +		matrix: matrix@ffffde00 {
> +			compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
> +			reg = <0xffffde00 0x200>;
> +		};
> +
> +		pmecc: ecc-engine@ffffe000 {
> +			compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
> +			reg = <0xffffe000 0x300>,
> +			      <0xffffe600 0x100>;
> +		};
> +
> +		mpddrc: mpddrc@ffffe800 {
> +			compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
> +			reg = <0xffffe800 0x200>;
> +			clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
> +			clock-names = "ddrck", "mpddr";
> +		};
> +
> +		smc: smc@ffffea00 {
> +			compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
> +			reg = <0xffffea00 0x100>;
> +		};
> +
> +		aic: interrupt-controller@fffff100 {
> +			compatible = "microchip,sam9x7-aic";
> +			reg = <0xfffff100 0x100>;
> +			#interrupt-cells = <3>;
> +			interrupt-controller;
> +			atmel,external-irqs = <31>;
> +		};
> +
> +		dbgu: serial@fffff200 {
> +			compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
> +			reg = <0xfffff200 0x200>;
> +			interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(28))>,
> +			       <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(29))>;
> +			dma-names = "tx", "rx";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
> +			clock-names = "usart";
> +			status = "disabled";
> +		};
> +
> +		pinctrl: pinctrl@fffff400 {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-mfd";
> +			ranges = <0xfffff400 0xfffff400 0x800>;
> +
> +			/* mux-mask corresponding to sam9x7 SoC in TFBGA228L package */
> +			atmel,mux-mask = <
> +					 /*  A		B	   C	      D	  */
> +					 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000	/* pioA */
> +					 0x07ffffff 0x0805fe7f 0x01ff9f80 0x06078000	/* pioB */
> +					 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000	/* pioC */
> +					 0x00003fff 0x00003fe0 0x0000003f 0x00000000	/* pioD */
> +					 >;
> +
> +			pioA: gpio@fffff400 {
> +				compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +				reg = <0xfffff400 0x200>;
> +				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
> +			};
> +
> +			pioB: gpio@fffff600 {
> +				compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +				reg = <0xfffff600 0x200>;
> +				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				#gpio-lines = <26>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
> +			};
> +
> +			pioC: gpio@fffff800 {
> +				compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +				reg = <0xfffff800 0x200>;
> +				interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
> +			};
> +
> +			pioD: gpio@fffffa00 {
> +				compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +				reg = <0xfffffa00 0x200>;
> +				interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				#gpio-lines = <22>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
> +			};
> +		};
> +
> +		pmc: pmc@fffffc00 {
> +			compatible = "microchip,sam9x7-pmc", "syscon";
> +			reg = <0xfffffc00 0x200>;
> +			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +			#clock-cells = <2>;
> +			clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
> +			clock-names = "td_slck", "md_slck", "main_xtal";
> +		};
> +
> +		reset_controller: rstc@fffffe00 {
> +			compatible = "microchip,sam9x60-rstc";
> +			reg = <0xfffffe00 0x10>;
> +			clocks = <&clk32k 0>;
> +		};
> +
> +		shutdown_controller: shdwc@fffffe10 {
> +			compatible = "microchip,sam9x60-shdwc";
> +			reg = <0xfffffe10 0x10>;
> +			clocks = <&clk32k 0>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			atmel,wakeup-rtc-timer;
> +			atmel,wakeup-rtt-timer;
> +			status = "disabled";
> +		};
> +
> +		rtt: rtc@fffffe20 {
> +			compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
> +			reg = <0xfffffe20 0x20>;
> +			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&clk32k 0>;
> +		};
> +
> +		clk32k: sckc@fffffe50 {
> +			compatible = "microchip,sam9x60-sckc";
> +			reg = <0xfffffe50 0x4>;
> +			clocks = <&slow_xtal>;
> +			#clock-cells = <1>;
> +		};
> +
> +		gpbr: syscon@fffffe60 {
> +			compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
> +			reg = <0xfffffe60 0x10>;
> +		};
> +
> +		rtc: rtc@fffffea8 {
> +			compatible = "microchip,sam9x60-rtc";
> +			reg = <0xfffffea8 0x100>;
> +			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&clk32k 0>;
> +		};
> +
> +		watchdog: watchdog@ffffff80 {
> +			compatible = "microchip,sam9x60-wdt";
> +			reg = <0xffffff80 0x24>;
> +			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&clk32k 0>;
> +			status = "disabled";
> +		};
> +	};
> +};

-- 
With Best Regards,
Dharma B.

Re: [PATCH 04/21] ARM: dts: at91: sam9x7: add device tree for soc

[Claudiu.Beznea]

On 03.06.2023 23:02, Varshini Rajendran wrote:
> Add device tree file for SAM9X7 SoC family
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> [nicolas.ferre@microchip.com: add support for gmac to sam9x7]
> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> [balamanikandan.gunasundar@microchip.com: Add device node csi2host and isc]
> Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
> ---
>  arch/arm/boot/dts/sam9x7.dtsi | 1333 +++++++++++++++++++++++++++++++++
>  1 file changed, 1333 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sam9x7.dtsi
> 
> diff --git a/arch/arm/boot/dts/sam9x7.dtsi b/arch/arm/boot/dts/sam9x7.dtsi
> new file mode 100644
> index 000000000000..f98160182fe6
> --- /dev/null
> +++ b/arch/arm/boot/dts/sam9x7.dtsi
> @@ -0,0 +1,1333 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family
> + *
> + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
> + */
> +
> +#include <dt-bindings/clock/at91.h>
> +#include <dt-bindings/dma/at91.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/mfd/atmel-flexcom.h>
> +#include <dt-bindings/pinctrl/at91.h>
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	model = "Microchip SAM9X7 SoC";
> +	compatible = "microchip,sam9x7";
> +	interrupt-parent = <&aic>;
> +
> +	aliases {
> +		serial0 = &dbgu;
> +		gpio0 = &pioA;
> +		gpio1 = &pioB;
> +		gpio2 = &pioC;
> +		gpio3 = &pioD;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			compatible = "arm,arm926ej-s";
> +			device_type = "cpu";
> +			reg = <0>;
> +		};
> +	};
> +
> +	clocks {
> +		slow_xtal: slow_xtal {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +
> +		main_xtal: main_xtal {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +	};
> +
> +	sram: sram@300000 {
> +		compatible = "mmio-sram";
> +		reg = <0x300000 0x10000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0x300000 0x10000>;
> +	};
> +
> +	ahb {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		usb0: gadget@500000 {
> +			compatible = "microchip,sam9x60-udc";
> +			reg = <0x500000 0x100000>,
> +			      <0xf803c000 0x400>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			clock-names = "pclk", "hclk";
> +			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			assigned-clock-rates = <480000000>;
> +			status = "disabled";
> +		};
> +
> +		ohci0: usb@600000 {
> +			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
> +			reg = <0x600000 0x100000>;
> +			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
> +			clock-names = "ohci_clk", "hclk", "uhpck";
> +			status = "disabled";
> +		};
> +
> +		ehci0: usb@700000 {
> +			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
> +			reg = <0x700000 0x100000>;
> +			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> +			clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
> +			clock-names = "usb_clk", "ehci_clk";
> +			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			assigned-clock-rates = <480000000>;
> +			status = "disabled";
> +		};
> +
> +		sdmmc0: sdio-host@80000000 {
> +			compatible = "microchip,sam9x60-sdhci";
> +			reg = <0x80000000 0x300>;
> +			interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
> +			clock-names = "hclock", "multclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +		};
> +
> +		sdmmc1: sdio-host@90000000 {
> +			compatible = "microchip,sam9x60-sdhci";
> +			reg = <0x90000000 0x300>;
> +			interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
> +			clock-names = "hclock", "multclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
> +			assigned-clock-rates = <100000000>;
> +			status = "disabled";
> +		};
> +	};
> +
> +	apb {

any reason apb isn't under ahb ?

> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		flx4: flexcom@f0000000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf0000000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf0000000 0x800>;
> +			status = "disabled";
> +
> +			uart4: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(8))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(9))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi4: spi@400 {
> +				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(8))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(9))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c4: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(8))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(9))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx5: flexcom@f0004000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf0004000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf0004000 0x800>;
> +			status = "disabled";
> +
> +			uart5: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(10))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(11))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi5: spi@400 {
> +				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(10))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(11))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c5: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(10))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(11))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		dma0: dma-controller@f0008000 {
> +			compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
> +			reg = <0xf0008000 0x1000>;
> +			interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
> +			#dma-cells = <1>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
> +			clock-names = "dma_clk";
> +			status = "disabled";
> +		};
> +
> +		ssc: ssc@f0010000 {
> +			compatible = "atmel,at91sam9g45-ssc";
> +			reg = <0xf0010000 0x4000>;
> +			interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(38))>,
> +			       <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(39))>;
> +			dma-names = "tx", "rx";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
> +			clock-names = "pclk";

should this one be enabled by default?

> +		};
> +
> +		gpu: gfx2d@f0018000 {
> +			compatible = "microchip,sam9x60-gfx2d";
> +			reg = <0xf0018000 0x4000>;
> +			interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 36>;
> +			clock-names = "periph_clk";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};

There is no mainline support for this node at the moment. It should be removed.

> +
> +		i2s: i2s@f001c000 {
> +			compatible = "microchip,sam9x60-i2smcc";
> +			reg = <0xf001c000 0x100>;
> +			interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(36))>,
> +			       <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(37))>;
> +			dma-names = "tx", "rx";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
> +			clock-names = "pclk", "gclk";
> +			status = "disabled";
> +		};
> +
> +		flx11: flexcom@f0020000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf0020000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf0020000 0x800>;
> +			status = "disabled";
> +
> +			uart11: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(22))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(23))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c11: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(22))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(23))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx12: flexcom@f0024000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf0024000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf0024000 0x800>;
> +			status = "disabled";
> +
> +			uart12: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(24))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(25))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c12: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(24))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(25))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		pit64b0: timer@f0028000 {
> +			compatible = "microchip,sam9x60-pit64b";
> +			reg = <0xf0028000 0x100>;
> +			interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
> +			clock-names = "pclk", "gclk";
> +		};
> +
> +		sha: sha@f002c000 {
> +			compatible = "atmel,at91sam9g46-sha";
> +			reg = <0xf002c000 0x100>;
> +			interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(34))>;
> +			dma-names = "tx";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
> +			clock-names = "sha_clk";
> +		};
> +
> +		trng: trng@f0030000 {
> +			compatible = "microchip,sam9x60-trng";
> +			reg = <0xf0030000 0x100>;
> +			interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
> +			status = "disabled";
> +		};
> +
> +		aes: aes@f0034000 {
> +			compatible = "atmel,at91sam9g46-aes";
> +			reg = <0xf0034000 0x100>;
> +			interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(32))>,
> +			       <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(33))>;
> +			dma-names = "tx", "rx";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
> +			clock-names = "aes_clk";
> +		};
> +
> +		tdes: tdes@f0038000 {
> +			compatible = "atmel,at91sam9g46-tdes";
> +			reg = <0xf0038000 0x100>;
> +			interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(31))>,
> +			       <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(30))>;
> +			dma-names = "tx", "rx";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
> +			clock-names = "tdes_clk";
> +		};
> +
> +		classd: classd@f003c000 {
> +			compatible = "atmel,sama5d2-classd";
> +			reg = <0xf003c000 0x100>;
> +			interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>;
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(35))>;
> +			dma-names = "tx";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>;
> +			clock-names = "pclk", "gclk";
> +			status = "disabled";
> +		};
> +
> +		pit64b1: timer@f0040000 {
> +			compatible = "microchip,sam9x60-pit64b";
> +			reg = <0xf0040000 0x100>;
> +			interrupts = <58 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
> +			clock-names = "pclk", "gclk";
> +		};
> +
> +		can0: can@f8000000 {
> +			compatible = "bosch,m_can";
> +			reg = <0xf8000000 0x100>, <0x300000 0x7800>;
> +			reg-names = "m_can", "message_ram";
> +			interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0
> +				      68 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "int0", "int1";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>;
> +			clock-names = "hclk", "cclk";
> +			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 29>;
> +			assigned-clock-rates = <480000000>, <40000000>;
> +			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
> +			status = "disabled";
> +		};
> +
> +		can1: can@f8004000 {
> +			compatible = "bosch,m_can";
> +			reg = <0xf8004000 0x100>, <0x300000 0xbc00>;
> +			reg-names = "m_can", "message_ram";
> +			interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0
> +				      69 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-names = "int0", "int1";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>;
> +			clock-names = "hclk", "cclk";
> +			assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 30>;
> +			assigned-clock-rates = <480000000>, <40000000>;
> +			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
> +			status = "disabled";
> +		};
> +
> +		tcb: timer@f8008000 {
> +			compatible = "microchip,sam9x60-tcb", "simple-mfd", "syscon";
> +			reg = <0xf8008000 0x100>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>;
> +			clock-names = "t0_clk", "slow_clk";
> +			status = "disabled";
> +		};
> +
> +		flx6: flexcom@f8010000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf8010000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf8010000 0x800>;
> +			status = "disabled";
> +
> +			uart6: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(12))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(13))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c6: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(12))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(13))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx7: flexcom@f8014000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf8014000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf8014000 0x800>;
> +			status = "disabled";
> +
> +			uart7: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(14))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(15))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c7: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(14))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(15))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx8: flexcom@f8018000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf8018000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf8018000 0x800>;
> +			status = "disabled";
> +
> +			uart8: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(16))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(17))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c8: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(16))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(17))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx0: flexcom@f801c000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf801c000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf801c000 0x800>;
> +			status = "disabled";
> +
> +			uart0: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(0))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(1))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi0: spi@400 {
> +				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(0))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(1))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c0: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(0))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(1))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx1: flexcom@f8020000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf8020000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf8020000 0x800>;
> +			status = "disabled";
> +
> +			uart1: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(2))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(3))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi1: spi@400 {
> +				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(2))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(3))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c1: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(2))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(3))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx2: flexcom@f8024000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf8024000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf8024000 0x800>;
> +			status = "disabled";
> +
> +			uart2: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(4))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(5))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi2: spi@400 {
> +				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(4))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(5))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c2: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(4))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(5))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx3: flexcom@f8028000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf8028000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf8028000 0x800>;
> +			status = "disabled";
> +
> +			uart3: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(6))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(7))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			spi3: spi@400 {
> +				compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> +				reg = <0x400 0x200>;
> +				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
> +				clock-names = "spi_clk";
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(6))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(7))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c3: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(6))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(7))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		gmac: ethernet@f802c000 {
> +			compatible = "microchip,sam9x7-gem";
> +			reg = <0xf802c000 0x1000>;
> +			interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3		/* Queue 0 */
> +				      60 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 1 */
> +				      61 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 2 */
> +				      62 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 3 */
> +				      63 IRQ_TYPE_LEVEL_HIGH 3          /* Queue 4 */
> +				      64 IRQ_TYPE_LEVEL_HIGH 3>;        /* Queue 5 */
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
> +			clock-names = "hclk", "pclk";
> +			status = "disabled";
> +		};
> +
> +		flx9: flexcom@f8040000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf8040000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf8040000 0x800>;
> +			status = "disabled";
> +
> +			uart9: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(18))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(19))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c9: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(18))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(19))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		flx10: flexcom@f8044000 {
> +			compatible = "atmel,sama5d2-flexcom";
> +			reg = <0xf8044000 0x200>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0xf8044000 0x800>;
> +			status = "disabled";
> +
> +			uart10: serial@200 {
> +				compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> +				reg = <0x200 0x200>;
> +				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(20))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(21))>;
> +				dma-names = "tx", "rx";
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
> +				clock-names = "usart";
> +				atmel,use-dma-rx;
> +				atmel,use-dma-tx;
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +
> +			i2c10: i2c@600 {
> +				compatible = "microchip,sam9x60-i2c";
> +				reg = <0x600 0x200>;
> +				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
> +				dmas = <&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(20))>,
> +					<&dma0
> +					(AT91_XDMAC_DT_MEM_IF(0) |
> +					 AT91_XDMAC_DT_PER_IF(1) |
> +					 AT91_XDMAC_DT_PERID(21))>;
> +				dma-names = "tx", "rx";
> +				atmel,fifo-size = <16>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		xisc: xisc@f8048000 {
> +			compatible = "microchip,sama7g5-isc";
> +			reg = <0xf8048000 0x2000>;
> +			interrupts = <43 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
> +			clock-names = "hclock";
> +			#clock-cells = <0>;
> +			clock-output-names = "isc-mck";
> +			status = "disabled";
> +
> +			port {
> +				xisc_in: endpoint {
> +					bus-width = <14>;
> +					hsync-active = <1>;
> +					vsync-active = <1>;
> +					remote-endpoint = <&csi2dc_out>;
> +				};
> +			};
> +		};
> +
> +		sfr: sfr@f8050000 {
> +			compatible = "microchip,sam9x60-sfr", "syscon";
> +			reg = <0xf8050000 0x100>;
> +		};
> +
> +		csi2host: csi2host@f8058000 {
> +			compatible = "snps,dw-csi";

This compatible is not available in any in tree driver.

> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0xf8058000 0x7FF>;
> +			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 53>, <&pmc PMC_TYPE_GCK 55>;
> +			clock-names = "perclk", "phyclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 55>;
> +			assigned-clock-rates = <26600000>;
> +			snps,output-type = <1>;
> +			phys = <&csi_dphy>;
> +			status = "disabled";
> +
> +			port@1 {
> +				reg = <1>;
> +				csi2host_in: endpoint {
> +				};
> +			};
> +
> +			port@2 {
> +				reg = <2>;
> +				csi2host_out: endpoint {
> +				};
> +			};
> +		};
> +
> +		csi_dphy: dphy@f8058040 {
> +			compatible = "snps,dw-dphy-rx";

same for this one.

> +			#phy-cells = <0>;
> +			bus-width = <8>;
> +			snps,dphy-frequency = <900000>;
> +			snps,phy_type = <0>;
> +			reg = <0xf8058040 0x20>;
> +			status = "disabled";
> +		};
> +
> +		csi2dc: csi2dc@f805c000 {
> +			compatible = "microchip,sama7g5-csi2dc";
> +			reg = <0xf805c000 0x500>;
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&xisc>;
> +			clock-names = "pclk", "scck";
> +			assigned-clocks = <&xisc>;
> +			assigned-clock-rates = <266000000>;
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				port@0 {
> +					reg = <0>;
> +					csi2dc_in: endpoint {
> +					};
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +					csi2dc_out: endpoint {
> +						bus-width = <14>;
> +						hsync-active = <1>;
> +						vsync-active = <1>;
> +						remote-endpoint = <&xisc_in>;
> +					};
> +				};
> +			};
> +		};
> +
> +		matrix: matrix@ffffde00 {
> +			compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon";
> +			reg = <0xffffde00 0x200>;
> +		};
> +
> +		pmecc: ecc-engine@ffffe000 {
> +			compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
> +			reg = <0xffffe000 0x300>,
> +			      <0xffffe600 0x100>;
> +		};
> +
> +		mpddrc: mpddrc@ffffe800 {
> +			compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
> +			reg = <0xffffe800 0x200>;
> +			clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
> +			clock-names = "ddrck", "mpddr";
> +		};
> +
> +		smc: smc@ffffea00 {
> +			compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
> +			reg = <0xffffea00 0x100>;
> +		};
> +
> +		aic: interrupt-controller@fffff100 {
> +			compatible = "microchip,sam9x7-aic";
> +			reg = <0xfffff100 0x100>;
> +			#interrupt-cells = <3>;
> +			interrupt-controller;
> +			atmel,external-irqs = <31>;
> +		};
> +
> +		dbgu: serial@fffff200 {
> +			compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
> +			reg = <0xfffff200 0x200>;
> +			interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>;
> +			dmas = <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(28))>,
> +			       <&dma0
> +				(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> +				 AT91_XDMAC_DT_PERID(29))>;
> +			dma-names = "tx", "rx";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
> +			clock-names = "usart";
> +			status = "disabled";
> +		};
> +
> +		pinctrl: pinctrl@fffff400 {
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			compatible = "microchip,sam9x60-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-mfd";
> +			ranges = <0xfffff400 0xfffff400 0x800>;
> +
> +			/* mux-mask corresponding to sam9x7 SoC in TFBGA228L package */
> +			atmel,mux-mask = <
> +					 /*  A		B	   C	      D	  */
> +					 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000	/* pioA */
> +					 0x07ffffff 0x0805fe7f 0x01ff9f80 0x06078000	/* pioB */
> +					 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000	/* pioC */
> +					 0x00003fff 0x00003fe0 0x0000003f 0x00000000	/* pioD */
> +					 >;
> +
> +			pioA: gpio@fffff400 {
> +				compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +				reg = <0xfffff400 0x200>;
> +				interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
> +			};
> +
> +			pioB: gpio@fffff600 {
> +				compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +				reg = <0xfffff600 0x200>;
> +				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				#gpio-lines = <26>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
> +			};
> +
> +			pioC: gpio@fffff800 {
> +				compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +				reg = <0xfffff800 0x200>;
> +				interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
> +			};
> +
> +			pioD: gpio@fffffa00 {
> +				compatible = "microchip,sam9x60-gpio", "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
> +				reg = <0xfffffa00 0x200>;
> +				interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>;
> +				#gpio-cells = <2>;
> +				gpio-controller;
> +				#gpio-lines = <22>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
> +			};
> +		};
> +
> +		pmc: pmc@fffffc00 {
> +			compatible = "microchip,sam9x7-pmc", "syscon";
> +			reg = <0xfffffc00 0x200>;
> +			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +			#clock-cells = <2>;
> +			clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
> +			clock-names = "td_slck", "md_slck", "main_xtal";
> +		};
> +
> +		reset_controller: rstc@fffffe00 {
> +			compatible = "microchip,sam9x60-rstc";
> +			reg = <0xfffffe00 0x10>;
> +			clocks = <&clk32k 0>;
> +		};
> +
> +		shutdown_controller: shdwc@fffffe10 {
> +			compatible = "microchip,sam9x60-shdwc";
> +			reg = <0xfffffe10 0x10>;
> +			clocks = <&clk32k 0>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			atmel,wakeup-rtc-timer;
> +			atmel,wakeup-rtt-timer;
> +			status = "disabled";
> +		};
> +
> +		rtt: rtc@fffffe20 {
> +			compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
> +			reg = <0xfffffe20 0x20>;
> +			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&clk32k 0>;
> +		};
> +
> +		clk32k: sckc@fffffe50 {
> +			compatible = "microchip,sam9x60-sckc";
> +			reg = <0xfffffe50 0x4>;
> +			clocks = <&slow_xtal>;
> +			#clock-cells = <1>;
> +		};
> +
> +		gpbr: syscon@fffffe60 {
> +			compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon";
> +			reg = <0xfffffe60 0x10>;
> +		};
> +
> +		rtc: rtc@fffffea8 {
> +			compatible = "microchip,sam9x60-rtc";
> +			reg = <0xfffffea8 0x100>;
> +			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&clk32k 0>;
> +		};
> +
> +		watchdog: watchdog@ffffff80 {
> +			compatible = "microchip,sam9x60-wdt";
> +			reg = <0xffffff80 0x24>;
> +			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
> +			clocks = <&clk32k 0>;
> +			status = "disabled";
> +		};
> +	};
> +};

[PATCH 05/21] ARM: configs: at91: enable config flags for sam9x7 SoC

[Varshini Rajendran]

Enable config flags for SAM9X7 SoC

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 arch/arm/configs/at91_dt_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 82bcf4dc7f54..6266a000736b 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -15,6 +15,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_SOC_AT91RM9200=y
 CONFIG_SOC_AT91SAM9=y
 CONFIG_SOC_SAM9X60=y
+CONFIG_SOC_SAM9X7=y
 # CONFIG_ATMEL_CLOCKSOURCE_PIT is not set
 CONFIG_AEABI=y
 CONFIG_UACCESS_WITH_MEMCPY=y
-- 
2.25.1

[PATCH 06/21] ARM: configs: at91: add mcan support

[Varshini Rajendran]

Enable MCAN configs to support sam9x7 soc family

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 arch/arm/configs/at91_dt_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 6266a000736b..f18bcf2dcd24 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -82,6 +82,8 @@ CONFIG_DM9000=y
 CONFIG_DAVICOM_PHY=y
 CONFIG_MICREL_PHY=y
 CONFIG_CAN_AT91=y
+CONFIG_CAN_M_CAN=y
+CONFIG_CAN_M_CAN_PLATFORM=y
 CONFIG_LIBERTAS=m
 CONFIG_LIBERTAS_SDIO=m
 CONFIG_LIBERTAS_SPI=m
-- 
2.25.1

Re: [PATCH 06/21] ARM: configs: at91: add mcan support

[Krzysztof Kozlowski]

On 03/06/2023 22:02, Varshini Rajendran wrote:
> Enable MCAN configs to support sam9x7 soc family
> 

There is no need to enable config items one by one. Squash these.

Best regards,
Krzysztof

[PATCH 07/21] ARM: configs: at91: Enable csi and isc support

[Varshini Rajendran]

From: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>

Enable CSI, ISC and IMX219 camera sensor support for image capture
pipeline.

Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 arch/arm/configs/at91_dt_defconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index f18bcf2dcd24..6d1170bb2c81 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -141,7 +141,12 @@ CONFIG_MEDIA_PLATFORM_SUPPORT=y
 CONFIG_MEDIA_USB_SUPPORT=y
 CONFIG_USB_VIDEO_CLASS=m
 CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_ATMEL_XISC=y
 CONFIG_VIDEO_ATMEL_ISI=y
+CONFIG_VIDEO_MICROCHIP_CSI2DC=y
+CONFIG_DWC_MIPI_CSI2_HOST=m
+CONFIG_DWC_MIPI_DPHY_GEN3=m
+CONFIG_VIDEO_IMX219=m
 CONFIG_VIDEO_MT9V032=m
 CONFIG_VIDEO_OV2640=m
 CONFIG_VIDEO_OV7740=m
-- 
2.25.1

[PATCH 08/21] ARM: at91: pm: add support for sam9x7 soc family

[Varshini Rajendran]

Add support and pm init config for sam9x7 soc

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 arch/arm/mach-at91/generic.h |  2 ++
 arch/arm/mach-at91/pm.c      | 35 +++++++++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+)

diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 0c3960a8b3eb..acf0b3c82a30 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -12,6 +12,7 @@
 extern void __init at91rm9200_pm_init(void);
 extern void __init at91sam9_pm_init(void);
 extern void __init sam9x60_pm_init(void);
+extern void __init sam9x7_pm_init(void);
 extern void __init sama5_pm_init(void);
 extern void __init sama5d2_pm_init(void);
 extern void __init sama7_pm_init(void);
@@ -19,6 +20,7 @@ extern void __init sama7_pm_init(void);
 static inline void __init at91rm9200_pm_init(void) { }
 static inline void __init at91sam9_pm_init(void) { }
 static inline void __init sam9x60_pm_init(void) { }
+static inline void __init sam9x7_pm_init(void) { }
 static inline void __init sama5_pm_init(void) { }
 static inline void __init sama5d2_pm_init(void) { }
 static inline void __init sama7_pm_init(void) { }
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 60dc56d8acfb..43a77ae0c38c 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -232,6 +232,17 @@ static const struct of_device_id sama7g5_ws_ids[] = {
 	{ /* sentinel */ }
 };
 
+static const struct of_device_id sam9x7_ws_ids[] = {
+	{ .compatible = "microchip,sam9x60-rtc",	.data = &ws_info[1] },
+	{ .compatible = "atmel,at91rm9200-ohci",	.data = &ws_info[2] },
+	{ .compatible = "usb-ohci",			.data = &ws_info[2] },
+	{ .compatible = "atmel,at91sam9g45-ehci",	.data = &ws_info[2] },
+	{ .compatible = "usb-ehci",			.data = &ws_info[2] },
+	{ .compatible = "microchip,sam9x60-rtt",	.data = &ws_info[4] },
+	{ .compatible = "microchip,sam9x7-gem",		.data = &ws_info[5] },
+	{ /* sentinel */ }
+};
+
 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
 {
 	const struct wakeup_source_info *wsi;
@@ -1133,6 +1144,7 @@ static const struct of_device_id gmac_ids[] __initconst = {
 	{ .compatible = "atmel,sama5d2-gem" },
 	{ .compatible = "atmel,sama5d29-gem" },
 	{ .compatible = "microchip,sama7g5-gem" },
+	{ .compatible = "microchip,sam9x7-gem" },
 	{ },
 };
 
@@ -1360,6 +1372,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
 	{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
 	{ .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
 	{ .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
+	{ .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
 	{ /* sentinel */ },
 };
 
@@ -1497,6 +1510,28 @@ void __init sam9x60_pm_init(void)
 	soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
 }
 
+void __init sam9x7_pm_init(void)
+{
+	static const int modes[] __initconst = {
+		AT91_PM_STANDBY, AT91_PM_ULP0,
+	};
+
+	int ret;
+
+	if (!IS_ENABLED(CONFIG_SOC_SAM9X7))
+		return;
+
+	at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
+	ret = at91_dt_ramc(false);
+	if (ret)
+		return;
+
+	at91_pm_init(NULL);
+
+	soc_pm.ws_ids = sam9x7_ws_ids;
+	soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
+}
+
 void __init at91sam9_pm_init(void)
 {
 	int ret;
-- 
2.25.1

Re: [PATCH 08/21] ARM: at91: pm: add support for sam9x7 soc family

[Claudiu.Beznea]

On 03.06.2023 23:02, Varshini Rajendran wrote:
> Add support and pm init config for sam9x7 soc
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>


> ---
>  arch/arm/mach-at91/generic.h |  2 ++
>  arch/arm/mach-at91/pm.c      | 35 +++++++++++++++++++++++++++++++++++
>  2 files changed, 37 insertions(+)
> 
> diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
> index 0c3960a8b3eb..acf0b3c82a30 100644
> --- a/arch/arm/mach-at91/generic.h
> +++ b/arch/arm/mach-at91/generic.h
> @@ -12,6 +12,7 @@
>  extern void __init at91rm9200_pm_init(void);
>  extern void __init at91sam9_pm_init(void);
>  extern void __init sam9x60_pm_init(void);
> +extern void __init sam9x7_pm_init(void);
>  extern void __init sama5_pm_init(void);
>  extern void __init sama5d2_pm_init(void);
>  extern void __init sama7_pm_init(void);
> @@ -19,6 +20,7 @@ extern void __init sama7_pm_init(void);
>  static inline void __init at91rm9200_pm_init(void) { }
>  static inline void __init at91sam9_pm_init(void) { }
>  static inline void __init sam9x60_pm_init(void) { }
> +static inline void __init sam9x7_pm_init(void) { }
>  static inline void __init sama5_pm_init(void) { }
>  static inline void __init sama5d2_pm_init(void) { }
>  static inline void __init sama7_pm_init(void) { }
> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> index 60dc56d8acfb..43a77ae0c38c 100644
> --- a/arch/arm/mach-at91/pm.c
> +++ b/arch/arm/mach-at91/pm.c
> @@ -232,6 +232,17 @@ static const struct of_device_id sama7g5_ws_ids[] = {
>  	{ /* sentinel */ }
>  };
>  
> +static const struct of_device_id sam9x7_ws_ids[] = {
> +	{ .compatible = "microchip,sam9x60-rtc",	.data = &ws_info[1] },
> +	{ .compatible = "atmel,at91rm9200-ohci",	.data = &ws_info[2] },
> +	{ .compatible = "usb-ohci",			.data = &ws_info[2] },
> +	{ .compatible = "atmel,at91sam9g45-ehci",	.data = &ws_info[2] },
> +	{ .compatible = "usb-ehci",			.data = &ws_info[2] },
> +	{ .compatible = "microchip,sam9x60-rtt",	.data = &ws_info[4] },
> +	{ .compatible = "microchip,sam9x7-gem",		.data = &ws_info[5] },
> +	{ /* sentinel */ }
> +};
> +
>  static int at91_pm_config_ws(unsigned int pm_mode, bool set)
>  {
>  	const struct wakeup_source_info *wsi;
> @@ -1133,6 +1144,7 @@ static const struct of_device_id gmac_ids[] __initconst = {
>  	{ .compatible = "atmel,sama5d2-gem" },
>  	{ .compatible = "atmel,sama5d29-gem" },
>  	{ .compatible = "microchip,sama7g5-gem" },
> +	{ .compatible = "microchip,sam9x7-gem" },
>  	{ },
>  };
>  
> @@ -1360,6 +1372,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
>  	{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
>  	{ .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
>  	{ .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
> +	{ .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
>  	{ /* sentinel */ },
>  };
>  
> @@ -1497,6 +1510,28 @@ void __init sam9x60_pm_init(void)
>  	soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
>  }
>  
> +void __init sam9x7_pm_init(void)
> +{
> +	static const int modes[] __initconst = {
> +		AT91_PM_STANDBY, AT91_PM_ULP0,
> +	};
> +
> +	int ret;
> +
> +	if (!IS_ENABLED(CONFIG_SOC_SAM9X7))
> +		return;
> +
> +	at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
> +	ret = at91_dt_ramc(false);
> +	if (ret)
> +		return;
> +
> +	at91_pm_init(NULL);
> +
> +	soc_pm.ws_ids = sam9x7_ws_ids;
> +	soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
> +}
> +
>  void __init at91sam9_pm_init(void)
>  {
>  	int ret;

[PATCH 09/21] ARM: at91: pm: add sam9x7 soc init config

[Varshini Rajendran]

Add SoC init config for sam9x7 family

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 arch/arm/mach-at91/Makefile |  1 +
 arch/arm/mach-at91/sam9x7.c | 34 ++++++++++++++++++++++++++++++++++
 2 files changed, 35 insertions(+)
 create mode 100644 arch/arm/mach-at91/sam9x7.c

diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 794bd12ab0a8..7d8a7bc44e65 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -7,6 +7,7 @@
 obj-$(CONFIG_SOC_AT91RM9200)	+= at91rm9200.o
 obj-$(CONFIG_SOC_AT91SAM9)	+= at91sam9.o
 obj-$(CONFIG_SOC_SAM9X60)	+= sam9x60.o
+obj-$(CONFIG_SOC_SAM9X7)	+= sam9x7.o
 obj-$(CONFIG_SOC_SAMA5)		+= sama5.o sam_secure.o
 obj-$(CONFIG_SOC_SAMA7)		+= sama7.o
 obj-$(CONFIG_SOC_SAMV7)		+= samv7.o
diff --git a/arch/arm/mach-at91/sam9x7.c b/arch/arm/mach-at91/sam9x7.c
new file mode 100644
index 000000000000..e322c5a3cdb6
--- /dev/null
+++ b/arch/arm/mach-at91/sam9x7.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Setup code for SAM9X7.
+ *
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
+ */
+
+#include <linux/of.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach/arch.h>
+#include <asm/system_misc.h>
+
+#include "generic.h"
+
+static void __init sam9x7_init(void)
+{
+	of_platform_default_populate(NULL, NULL, NULL);
+
+	sam9x7_pm_init();
+}
+
+static const char *const sam9x7_dt_board_compat[] __initconst = {
+	"microchip,sam9x7",
+	NULL
+};
+
+DT_MACHINE_START(sam9x7_dt, "Microchip SAM9X7")
+	/* Maintainer: Microchip */
+	.init_machine	= sam9x7_init,
+	.dt_compat	= sam9x7_dt_board_compat,
+MACHINE_END
-- 
2.25.1

Re: [PATCH 09/21] ARM: at91: pm: add sam9x7 soc init config

[Claudiu.Beznea]

On 03.06.2023 23:02, Varshini Rajendran wrote:
> Add SoC init config for sam9x7 family
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  arch/arm/mach-at91/Makefile |  1 +
>  arch/arm/mach-at91/sam9x7.c | 34 ++++++++++++++++++++++++++++++++++
>  2 files changed, 35 insertions(+)
>  create mode 100644 arch/arm/mach-at91/sam9x7.c
> 
> diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
> index 794bd12ab0a8..7d8a7bc44e65 100644
> --- a/arch/arm/mach-at91/Makefile
> +++ b/arch/arm/mach-at91/Makefile
> @@ -7,6 +7,7 @@
>  obj-$(CONFIG_SOC_AT91RM9200)	+= at91rm9200.o
>  obj-$(CONFIG_SOC_AT91SAM9)	+= at91sam9.o
>  obj-$(CONFIG_SOC_SAM9X60)	+= sam9x60.o
> +obj-$(CONFIG_SOC_SAM9X7)	+= sam9x7.o
>  obj-$(CONFIG_SOC_SAMA5)		+= sama5.o sam_secure.o
>  obj-$(CONFIG_SOC_SAMA7)		+= sama7.o
>  obj-$(CONFIG_SOC_SAMV7)		+= samv7.o
> diff --git a/arch/arm/mach-at91/sam9x7.c b/arch/arm/mach-at91/sam9x7.c
> new file mode 100644
> index 000000000000..e322c5a3cdb6
> --- /dev/null
> +++ b/arch/arm/mach-at91/sam9x7.c
> @@ -0,0 +1,34 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Setup code for SAM9X7.
> + *
> + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries

2023?

> + *
> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
> + */
> +
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +
> +#include <asm/mach/arch.h>
> +#include <asm/system_misc.h>
> +
> +#include "generic.h"
> +
> +static void __init sam9x7_init(void)
> +{
> +	of_platform_default_populate(NULL, NULL, NULL);
> +
> +	sam9x7_pm_init();
> +}
> +
> +static const char *const sam9x7_dt_board_compat[] __initconst = {
> +	"microchip,sam9x7",
> +	NULL
> +};
> +
> +DT_MACHINE_START(sam9x7_dt, "Microchip SAM9X7")
> +	/* Maintainer: Microchip */
> +	.init_machine	= sam9x7_init,
> +	.dt_compat	= sam9x7_dt_board_compat,
> +MACHINE_END

[PATCH 10/21] ARM: at91: Kconfig: add config flag for SAM9X7 SoC

[Varshini Rajendran]

Add config flag for sam9x7 SoC

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 arch/arm/mach-at91/Kconfig | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 3dd9e718661b..4463afd7298a 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -143,11 +143,28 @@ config SOC_SAM9X60
 	help
 	  Select this if you are using Microchip's SAM9X60 SoC
 
+config SOC_SAM9X7
+	bool "SAM9X7"
+	depends on ARCH_MULTI_V5
+	select ATMEL_AIC5_IRQ
+	select ATMEL_PM if PM
+	select ATMEL_SDRAMC
+	select CPU_ARM926T
+	select HAVE_AT91_USB_CLK
+	select HAVE_AT91_GENERATED_CLK
+	select HAVE_AT91_SAM9X60_PLL
+	select MEMORY
+	select PINCTRL_AT91
+	select SOC_SAM_V4_V5
+	select SRAM if PM
+	help
+	  Select this if you are using Microchip's SAM9X7 SoC
+
 comment "Clocksource driver selection"
 
 config ATMEL_CLOCKSOURCE_PIT
 	bool "Periodic Interval Timer (PIT) support"
-	depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
+	depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5
 	default SOC_AT91SAM9 || SOC_SAMA5
 	select ATMEL_PIT
 	help
@@ -157,7 +174,7 @@ config ATMEL_CLOCKSOURCE_PIT
 
 config ATMEL_CLOCKSOURCE_TCB
 	bool "Timer Counter Blocks (TCB) support"
-	default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
+	default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5
 	select ATMEL_TCB_CLKSRC
 	help
 	  Select this to get a high precision clocksource based on a
-- 
2.25.1

Re: [PATCH 10/21] ARM: at91: Kconfig: add config flag for SAM9X7 SoC

[Claudiu.Beznea]

On 03.06.2023 23:02, Varshini Rajendran wrote:
> Add config flag for sam9x7 SoC
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  arch/arm/mach-at91/Kconfig | 21 +++++++++++++++++++--
>  1 file changed, 19 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> index 3dd9e718661b..4463afd7298a 100644
> --- a/arch/arm/mach-at91/Kconfig
> +++ b/arch/arm/mach-at91/Kconfig
> @@ -143,11 +143,28 @@ config SOC_SAM9X60
>  	help
>  	  Select this if you are using Microchip's SAM9X60 SoC
>  
> +config SOC_SAM9X7
> +	bool "SAM9X7"
> +	depends on ARCH_MULTI_V5
> +	select ATMEL_AIC5_IRQ
> +	select ATMEL_PM if PM
> +	select ATMEL_SDRAMC
> +	select CPU_ARM926T
> +	select HAVE_AT91_USB_CLK
> +	select HAVE_AT91_GENERATED_CLK
> +	select HAVE_AT91_SAM9X60_PLL
> +	select MEMORY
> +	select PINCTRL_AT91
> +	select SOC_SAM_V4_V5
> +	select SRAM if PM
> +	help
> +	  Select this if you are using Microchip's SAM9X7 SoC
> +
>  comment "Clocksource driver selection"
>  
>  config ATMEL_CLOCKSOURCE_PIT
>  	bool "Periodic Interval Timer (PIT) support"
> -	depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
> +	depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5
>  	default SOC_AT91SAM9 || SOC_SAMA5
>  	select ATMEL_PIT
>  	help
> @@ -157,7 +174,7 @@ config ATMEL_CLOCKSOURCE_PIT
>  
>  config ATMEL_CLOCKSOURCE_TCB
>  	bool "Timer Counter Blocks (TCB) support"
> -	default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
> +	default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5

You should also take into account PIT64B available in this file after TCB.

>  	select ATMEL_TCB_CLKSRC
>  	help
>  	  Select this to get a high precision clocksource based on a

[PATCH 11/21] ARM: at91: add support in soc driver for new sam9x7

[Varshini Rajendran]

Add support for SAM9X7 SoC in the soc driver

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/soc/atmel/soc.c | 23 +++++++++++++++++++++++
 drivers/soc/atmel/soc.h |  9 +++++++++
 2 files changed, 32 insertions(+)

diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c
index cc9a3e107479..cae3452cbc60 100644
--- a/drivers/soc/atmel/soc.c
+++ b/drivers/soc/atmel/soc.c
@@ -101,6 +101,29 @@ static const struct at91_soc socs[] __initconst = {
 		 AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH,
 		 "sam9x60 8MiB SDRAM SiP", "sam9x60"),
 #endif
+#ifdef CONFIG_SOC_SAM9X7
+	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+		 "sam9x75", "sam9x7"),
+	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+		 AT91_CIDR_VERSION_MASK, SAM9X72_EXID_MATCH,
+		 "sam9x72", "sam9x7"),
+	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+		 AT91_CIDR_VERSION_MASK, SAM9X70_EXID_MATCH,
+		 "sam9x70", "sam9x7"),
+	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1G_EXID_MATCH,
+		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+		 "sam9x75 1Gb DDR3L SiP ", "sam9x7"),
+	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D5M_EXID_MATCH,
+		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+		 "sam9x75 512Mb DDR2 SiP", "sam9x7"),
+	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1M_EXID_MATCH,
+		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+		 "sam9x75 128Mb DDR2 SiP", "sam9x7"),
+	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D2G_EXID_MATCH,
+		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+		 "sam9x75 2Gb DDR3L SiP", "sam9x7"),
+#endif
 #ifdef CONFIG_SOC_SAMA5
 	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 		 AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH,
diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h
index 7a9f47ce85fb..26dd26b4f179 100644
--- a/drivers/soc/atmel/soc.h
+++ b/drivers/soc/atmel/soc.h
@@ -45,6 +45,7 @@ at91_soc_init(const struct at91_soc *socs);
 #define AT91SAM9N12_CIDR_MATCH		0x019a07a0
 #define SAM9X60_CIDR_MATCH		0x019b35a0
 #define SAMA7G5_CIDR_MATCH		0x00162100
+#define SAM9X7_CIDR_MATCH		0x09750020
 
 #define AT91SAM9M11_EXID_MATCH		0x00000001
 #define AT91SAM9M10_EXID_MATCH		0x00000002
@@ -74,6 +75,14 @@ at91_soc_init(const struct at91_soc *socs);
 #define SAMA7G54_D2G_EXID_MATCH		0x00000020
 #define SAMA7G54_D4G_EXID_MATCH		0x00000028
 
+#define SAM9X75_EXID_MATCH		0x00000000
+#define SAM9X72_EXID_MATCH		0x00000004
+#define SAM9X70_EXID_MATCH		0x00000005
+#define SAM9X75_D1G_EXID_MATCH		0x00000001
+#define SAM9X75_D5M_EXID_MATCH		0x00000002
+#define SAM9X75_D1M_EXID_MATCH		0x00000003
+#define SAM9X75_D2G_EXID_MATCH		0x00000006
+
 #define AT91SAM9XE128_CIDR_MATCH	0x329973a0
 #define AT91SAM9XE256_CIDR_MATCH	0x329a93a0
 #define AT91SAM9XE512_CIDR_MATCH	0x329aa3a0
-- 
2.25.1

Re: [PATCH 11/21] ARM: at91: add support in soc driver for new sam9x7

[Claudiu.Beznea]

On 03.06.2023 23:02, Varshini Rajendran wrote:
> Add support for SAM9X7 SoC in the soc driver
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>


> ---
>  drivers/soc/atmel/soc.c | 23 +++++++++++++++++++++++
>  drivers/soc/atmel/soc.h |  9 +++++++++
>  2 files changed, 32 insertions(+)
> 
> diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c
> index cc9a3e107479..cae3452cbc60 100644
> --- a/drivers/soc/atmel/soc.c
> +++ b/drivers/soc/atmel/soc.c
> @@ -101,6 +101,29 @@ static const struct at91_soc socs[] __initconst = {
>  		 AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH,
>  		 "sam9x60 8MiB SDRAM SiP", "sam9x60"),
>  #endif
> +#ifdef CONFIG_SOC_SAM9X7
> +	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
> +		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
> +		 "sam9x75", "sam9x7"),
> +	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
> +		 AT91_CIDR_VERSION_MASK, SAM9X72_EXID_MATCH,
> +		 "sam9x72", "sam9x7"),
> +	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
> +		 AT91_CIDR_VERSION_MASK, SAM9X70_EXID_MATCH,
> +		 "sam9x70", "sam9x7"),
> +	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1G_EXID_MATCH,
> +		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
> +		 "sam9x75 1Gb DDR3L SiP ", "sam9x7"),
> +	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D5M_EXID_MATCH,
> +		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
> +		 "sam9x75 512Mb DDR2 SiP", "sam9x7"),
> +	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1M_EXID_MATCH,
> +		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
> +		 "sam9x75 128Mb DDR2 SiP", "sam9x7"),
> +	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D2G_EXID_MATCH,
> +		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
> +		 "sam9x75 2Gb DDR3L SiP", "sam9x7"),
> +#endif
>  #ifdef CONFIG_SOC_SAMA5
>  	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
>  		 AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH,
> diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h
> index 7a9f47ce85fb..26dd26b4f179 100644
> --- a/drivers/soc/atmel/soc.h
> +++ b/drivers/soc/atmel/soc.h
> @@ -45,6 +45,7 @@ at91_soc_init(const struct at91_soc *socs);
>  #define AT91SAM9N12_CIDR_MATCH		0x019a07a0
>  #define SAM9X60_CIDR_MATCH		0x019b35a0
>  #define SAMA7G5_CIDR_MATCH		0x00162100
> +#define SAM9X7_CIDR_MATCH		0x09750020
>  
>  #define AT91SAM9M11_EXID_MATCH		0x00000001
>  #define AT91SAM9M10_EXID_MATCH		0x00000002
> @@ -74,6 +75,14 @@ at91_soc_init(const struct at91_soc *socs);
>  #define SAMA7G54_D2G_EXID_MATCH		0x00000020
>  #define SAMA7G54_D4G_EXID_MATCH		0x00000028
>  
> +#define SAM9X75_EXID_MATCH		0x00000000
> +#define SAM9X72_EXID_MATCH		0x00000004
> +#define SAM9X70_EXID_MATCH		0x00000005
> +#define SAM9X75_D1G_EXID_MATCH		0x00000001
> +#define SAM9X75_D5M_EXID_MATCH		0x00000002
> +#define SAM9X75_D1M_EXID_MATCH		0x00000003
> +#define SAM9X75_D2G_EXID_MATCH		0x00000006
> +
>  #define AT91SAM9XE128_CIDR_MATCH	0x329973a0
>  #define AT91SAM9XE256_CIDR_MATCH	0x329a93a0
>  #define AT91SAM9XE512_CIDR_MATCH	0x329aa3a0

[PATCH 12/21] clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs

[Varshini Rajendran]

-Support SoCs with different core frequency outputs for different PLL IDs
by adding a separate parameter for handling the same in the PLL driver
-Align sam9x60 and sama7g5 Soc PMC driver to PLL driver by adding core
output freq range in the PLL characteristics configurations

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/clk/at91/clk-sam9x60-pll.c | 12 ++++++------
 drivers/clk/at91/pmc.h             |  1 +
 drivers/clk/at91/sam9x60.c         |  7 +++++++
 drivers/clk/at91/sama7g5.c         |  7 +++++++
 4 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index 0882ed01d5c2..b3012641214c 100644
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -23,9 +23,6 @@
 #define UPLL_DIV		2
 #define PLL_MUL_MAX		(FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
 
-#define FCORE_MIN		(600000000)
-#define FCORE_MAX		(1200000000)
-
 #define PLL_MAX_ID		7
 
 struct sam9x60_pll_core {
@@ -194,7 +191,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,
 	unsigned long nmul = 0;
 	unsigned long nfrac = 0;
 
-	if (rate < FCORE_MIN || rate > FCORE_MAX)
+	if (rate < core->characteristics->core_output[0].min ||
+	    rate > core->characteristics->core_output[0].max)
 		return -ERANGE;
 
 	/*
@@ -214,7 +212,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,
 	}
 
 	/* Check if resulted rate is a valid.  */
-	if (tmprate < FCORE_MIN || tmprate > FCORE_MAX)
+	if (tmprate < core->characteristics->core_output[0].min ||
+	    tmprate > core->characteristics->core_output[0].max)
 		return -ERANGE;
 
 	if (update) {
@@ -666,7 +665,8 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
 			goto free;
 		}
 
-		ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN,
+		ret = sam9x60_frac_pll_compute_mul_frac(&frac->core,
+							characteristics->core_output[0].min,
 							parent_rate, true);
 		if (ret < 0) {
 			hw = ERR_PTR(ret);
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 1b3ca7dd9b57..3e36dcc464c1 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -75,6 +75,7 @@ struct clk_pll_characteristics {
 	struct clk_range input;
 	int num_output;
 	const struct clk_range *output;
+	const struct clk_range *core_output;
 	u16 *icpll;
 	u8 *out;
 	u8 upll : 1;
diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
index ac070db58195..452ad45cf251 100644
--- a/drivers/clk/at91/sam9x60.c
+++ b/drivers/clk/at91/sam9x60.c
@@ -26,10 +26,16 @@ static const struct clk_range plla_outputs[] = {
 	{ .min = 2343750, .max = 1200000000 },
 };
 
+/* Fractional PLL core output range. */
+static const struct clk_range core_outputs[] = {
+	{ .min = 600000000, .max = 1200000000 },
+};
+
 static const struct clk_pll_characteristics plla_characteristics = {
 	.input = { .min = 12000000, .max = 48000000 },
 	.num_output = ARRAY_SIZE(plla_outputs),
 	.output = plla_outputs,
+	.core_output = core_outputs,
 };
 
 static const struct clk_range upll_outputs[] = {
@@ -40,6 +46,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
 	.input = { .min = 12000000, .max = 48000000 },
 	.num_output = ARRAY_SIZE(upll_outputs),
 	.output = upll_outputs,
+	.core_output = core_outputs,
 	.upll = true,
 };
 
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index f135b662f1ff..468a3c5449b5 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -104,11 +104,17 @@ static const struct clk_range pll_outputs[] = {
 	{ .min = 2343750, .max = 1200000000 },
 };
 
+/* Fractional PLL core output range. */
+static const struct clk_range core_outputs[] = {
+	{ .min = 600000000, .max = 1200000000 },
+};
+
 /* CPU PLL characteristics. */
 static const struct clk_pll_characteristics cpu_pll_characteristics = {
 	.input = { .min = 12000000, .max = 50000000 },
 	.num_output = ARRAY_SIZE(cpu_pll_outputs),
 	.output = cpu_pll_outputs,
+	.core_output = core_outputs,
 };
 
 /* PLL characteristics. */
@@ -116,6 +122,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
 	.input = { .min = 12000000, .max = 50000000 },
 	.num_output = ARRAY_SIZE(pll_outputs),
 	.output = pll_outputs,
+	.core_output = core_outputs,
 };
 
 /*
-- 
2.25.1

Re: [PATCH 12/21] clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs

[Claudiu.Beznea]

On 03.06.2023 23:02, Varshini Rajendran wrote:
> -Support SoCs with different core frequency outputs for different PLL IDs
> by adding a separate parameter for handling the same in the PLL driver
> -Align sam9x60 and sama7g5 Soc PMC driver to PLL driver by adding core
> output freq range in the PLL characteristics configurations

Having this with "-" here makes me think you did multiple things in the
same patch. Please explain comprehensively what you've did, why and how.

> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  drivers/clk/at91/clk-sam9x60-pll.c | 12 ++++++------
>  drivers/clk/at91/pmc.h             |  1 +
>  drivers/clk/at91/sam9x60.c         |  7 +++++++
>  drivers/clk/at91/sama7g5.c         |  7 +++++++
>  4 files changed, 21 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index 0882ed01d5c2..b3012641214c 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -23,9 +23,6 @@
>  #define UPLL_DIV		2
>  #define PLL_MUL_MAX		(FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
>  
> -#define FCORE_MIN		(600000000)
> -#define FCORE_MAX		(1200000000)
> -
>  #define PLL_MAX_ID		7
>  
>  struct sam9x60_pll_core {
> @@ -194,7 +191,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,
>  	unsigned long nmul = 0;
>  	unsigned long nfrac = 0;
>  
> -	if (rate < FCORE_MIN || rate > FCORE_MAX)
> +	if (rate < core->characteristics->core_output[0].min ||
> +	    rate > core->characteristics->core_output[0].max)
>  		return -ERANGE;
>  
>  	/*
> @@ -214,7 +212,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,
>  	}
>  
>  	/* Check if resulted rate is a valid.  */
> -	if (tmprate < FCORE_MIN || tmprate > FCORE_MAX)
> +	if (tmprate < core->characteristics->core_output[0].min ||
> +	    tmprate > core->characteristics->core_output[0].max)
>  		return -ERANGE;
>  
>  	if (update) {
> @@ -666,7 +665,8 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
>  			goto free;
>  		}
>  
> -		ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN,
> +		ret = sam9x60_frac_pll_compute_mul_frac(&frac->core,
> +							characteristics->core_output[0].min,
>  							parent_rate, true);
>  		if (ret < 0) {
>  			hw = ERR_PTR(ret);
> diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
> index 1b3ca7dd9b57..3e36dcc464c1 100644
> --- a/drivers/clk/at91/pmc.h
> +++ b/drivers/clk/at91/pmc.h
> @@ -75,6 +75,7 @@ struct clk_pll_characteristics {
>  	struct clk_range input;
>  	int num_output;
>  	const struct clk_range *output;
> +	const struct clk_range *core_output;
>  	u16 *icpll;
>  	u8 *out;
>  	u8 upll : 1;
> diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
> index ac070db58195..452ad45cf251 100644
> --- a/drivers/clk/at91/sam9x60.c
> +++ b/drivers/clk/at91/sam9x60.c
> @@ -26,10 +26,16 @@ static const struct clk_range plla_outputs[] = {
>  	{ .min = 2343750, .max = 1200000000 },
>  };
>  
> +/* Fractional PLL core output range. */
> +static const struct clk_range core_outputs[] = {
> +	{ .min = 600000000, .max = 1200000000 },
> +};
> +
>  static const struct clk_pll_characteristics plla_characteristics = {
>  	.input = { .min = 12000000, .max = 48000000 },
>  	.num_output = ARRAY_SIZE(plla_outputs),
>  	.output = plla_outputs,
> +	.core_output = core_outputs,
>  };
>  
>  static const struct clk_range upll_outputs[] = {
> @@ -40,6 +46,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
>  	.input = { .min = 12000000, .max = 48000000 },
>  	.num_output = ARRAY_SIZE(upll_outputs),
>  	.output = upll_outputs,
> +	.core_output = core_outputs,
>  	.upll = true,
>  };
>  
> diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
> index f135b662f1ff..468a3c5449b5 100644
> --- a/drivers/clk/at91/sama7g5.c
> +++ b/drivers/clk/at91/sama7g5.c
> @@ -104,11 +104,17 @@ static const struct clk_range pll_outputs[] = {
>  	{ .min = 2343750, .max = 1200000000 },
>  };
>  
> +/* Fractional PLL core output range. */
> +static const struct clk_range core_outputs[] = {
> +	{ .min = 600000000, .max = 1200000000 },
> +};
> +
>  /* CPU PLL characteristics. */
>  static const struct clk_pll_characteristics cpu_pll_characteristics = {
>  	.input = { .min = 12000000, .max = 50000000 },
>  	.num_output = ARRAY_SIZE(cpu_pll_outputs),
>  	.output = cpu_pll_outputs,
> +	.core_output = core_outputs,
>  };
>  
>  /* PLL characteristics. */
> @@ -116,6 +122,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
>  	.input = { .min = 12000000, .max = 50000000 },
>  	.num_output = ARRAY_SIZE(pll_outputs),
>  	.output = pll_outputs,
> +	.core_output = core_outputs,
>  };
>  
>  /*

[PATCH 13/21] clk: at91: sam9x7: add support for HW PLL freq dividers

[Varshini Rajendran]

Add support for hardware dividers for PLL IDs in sam9x7 Soc
PLL_ID_PLLA and PLL_ID_PLLA_DIV2 has /2 hardware dividers each

fcorepllack -----> HW Div = 2 -+--> fpllack
                               |
                               +--> HW Div = 2 ---> fplladiv2ck

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/clk/at91/clk-sam9x60-pll.c | 38 ++++++++++++++++++++++++++----
 drivers/clk/at91/pmc.h             |  1 +
 2 files changed, 34 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index b3012641214c..76273ea74f8b 100644
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -73,9 +73,15 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
 {
 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 	struct sam9x60_frac *frac = to_sam9x60_frac(core);
+	unsigned long freq;
 
-	return parent_rate * (frac->mul + 1) +
+	freq = parent_rate * (frac->mul + 1) +
 		DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
+
+	if (core->layout->div2)
+		freq >>= 1;
+
+	return freq;
 }
 
 static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
@@ -432,6 +438,12 @@ static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw,
 	return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1));
 }
 
+static unsigned long sam9x60_fixed_div_pll_recalc_rate(struct clk_hw *hw,
+						       unsigned long parent_rate)
+{
+	return parent_rate >> 1;
+}
+
 static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core,
 					unsigned long *parent_rate,
 					unsigned long rate)
@@ -606,6 +618,16 @@ static const struct clk_ops sam9x60_div_pll_ops_chg = {
 	.restore_context = sam9x60_div_pll_restore_context,
 };
 
+static const struct clk_ops sam9x60_fixed_div_pll_ops = {
+	.prepare = sam9x60_div_pll_prepare,
+	.unprepare = sam9x60_div_pll_unprepare,
+	.is_prepared = sam9x60_div_pll_is_prepared,
+	.recalc_rate = sam9x60_fixed_div_pll_recalc_rate,
+	.round_rate = sam9x60_div_pll_round_rate,
+	.save_context = sam9x60_div_pll_save_context,
+	.restore_context = sam9x60_div_pll_restore_context,
+};
+
 struct clk_hw * __init
 sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
 			      const char *name, const char *parent_name,
@@ -718,10 +740,16 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
 	init.name = name;
 	init.parent_names = &parent_name;
 	init.num_parents = 1;
-	if (flags & CLK_SET_RATE_GATE)
-		init.ops = &sam9x60_div_pll_ops;
-	else
-		init.ops = &sam9x60_div_pll_ops_chg;
+
+	if (layout->div2) {
+		init.ops = &sam9x60_fixed_div_pll_ops;
+	} else {
+		if (flags & CLK_SET_RATE_GATE)
+			init.ops = &sam9x60_div_pll_ops;
+		else
+			init.ops = &sam9x60_div_pll_ops_chg;
+	}
+
 	init.flags = flags;
 
 	div->core.id = id;
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 3e36dcc464c1..1dd01f30bdee 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -64,6 +64,7 @@ struct clk_pll_layout {
 	u8 frac_shift;
 	u8 div_shift;
 	u8 endiv_shift;
+	u8 div2;
 };
 
 extern const struct clk_pll_layout at91rm9200_pll_layout;
-- 
2.25.1

Re: [PATCH 13/21] clk: at91: sam9x7: add support for HW PLL freq dividers

[Claudiu.Beznea]

On 03.06.2023 23:02, Varshini Rajendran wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Add support for hardware dividers for PLL IDs in sam9x7 Soc

dot at the end of line, probably.
s/Soc/SoC. Also, please explain it as clear as possible.

> PLL_ID_PLLA and PLL_ID_PLLA_DIV2 has /2 hardware dividers each

At the time of this patch PLL_ID_PLLA and PLL_ID_PLLA_DIV2 does't exist
thus would be more clear if you reference datasheet naming.

Other than this code looks good to me.

Thank you,
Claudiu

> 
> fcorepllack -----> HW Div = 2 -+--> fpllack
>                                |
>                                +--> HW Div = 2 ---> fplladiv2ck
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  drivers/clk/at91/clk-sam9x60-pll.c | 38 ++++++++++++++++++++++++++----
>  drivers/clk/at91/pmc.h             |  1 +
>  2 files changed, 34 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index b3012641214c..76273ea74f8b 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -73,9 +73,15 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
>  {
>         struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
>         struct sam9x60_frac *frac = to_sam9x60_frac(core);
> +       unsigned long freq;
> 
> -       return parent_rate * (frac->mul + 1) +
> +       freq = parent_rate * (frac->mul + 1) +
>                 DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
> +
> +       if (core->layout->div2)
> +               freq >>= 1;
> +
> +       return freq;
>  }
> 
>  static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
> @@ -432,6 +438,12 @@ static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw,
>         return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1));
>  }
> 
> +static unsigned long sam9x60_fixed_div_pll_recalc_rate(struct clk_hw *hw,
> +                                                      unsigned long parent_rate)
> +{
> +       return parent_rate >> 1;
> +}
> +
>  static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core,
>                                         unsigned long *parent_rate,
>                                         unsigned long rate)
> @@ -606,6 +618,16 @@ static const struct clk_ops sam9x60_div_pll_ops_chg = {
>         .restore_context = sam9x60_div_pll_restore_context,
>  };
> 
> +static const struct clk_ops sam9x60_fixed_div_pll_ops = {
> +       .prepare = sam9x60_div_pll_prepare,
> +       .unprepare = sam9x60_div_pll_unprepare,
> +       .is_prepared = sam9x60_div_pll_is_prepared,
> +       .recalc_rate = sam9x60_fixed_div_pll_recalc_rate,
> +       .round_rate = sam9x60_div_pll_round_rate,
> +       .save_context = sam9x60_div_pll_save_context,
> +       .restore_context = sam9x60_div_pll_restore_context,
> +};
> +
>  struct clk_hw * __init
>  sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
>                               const char *name, const char *parent_name,
> @@ -718,10 +740,16 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
>         init.name = name;
>         init.parent_names = &parent_name;
>         init.num_parents = 1;
> -       if (flags & CLK_SET_RATE_GATE)
> -               init.ops = &sam9x60_div_pll_ops;
> -       else
> -               init.ops = &sam9x60_div_pll_ops_chg;
> +
> +       if (layout->div2) {
> +               init.ops = &sam9x60_fixed_div_pll_ops;
> +       } else {
> +               if (flags & CLK_SET_RATE_GATE)
> +                       init.ops = &sam9x60_div_pll_ops;
> +               else
> +                       init.ops = &sam9x60_div_pll_ops_chg;
> +       }
> +
>         init.flags = flags;
> 
>         div->core.id = id;
> diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
> index 3e36dcc464c1..1dd01f30bdee 100644
> --- a/drivers/clk/at91/pmc.h
> +++ b/drivers/clk/at91/pmc.h
> @@ -64,6 +64,7 @@ struct clk_pll_layout {
>         u8 frac_shift;
>         u8 div_shift;
>         u8 endiv_shift;
> +       u8 div2;
>  };
> 
>  extern const struct clk_pll_layout at91rm9200_pll_layout;
> --
> 2.25.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 14/21] clk: at91: sam9x7: add sam9x7 pmc driver

[Varshini Rajendran]

Add a driver for the PMC clocks of sam9x7 Soc family

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/clk/at91/Makefile |   1 +
 drivers/clk/at91/sam9x7.c | 947 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 948 insertions(+)
 create mode 100644 drivers/clk/at91/sam9x7.c

diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 89061b85e7d2..8e3684ba2c74 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9rl.o at91sam9x5.o dt-compat.
 obj-$(CONFIG_SOC_AT91SAM9) += at91sam9g45.o dt-compat.o
 obj-$(CONFIG_SOC_AT91SAM9) += at91sam9n12.o at91sam9x5.o dt-compat.o
 obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o
+obj-$(CONFIG_SOC_SAM9X7) += sam9x7.o
 obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o dt-compat.o
 obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o dt-compat.o
 obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o dt-compat.o
diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
new file mode 100644
index 000000000000..8232a2af14be
--- /dev/null
+++ b/drivers/clk/at91/sam9x7.c
@@ -0,0 +1,947 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SAM9X7 PMC code.
+ *
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
+ *
+ */
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/at91.h>
+
+#include "pmc.h"
+
+#define SAM9X7_INIT_TABLE(_table, _count)		\
+	do {						\
+		u8 _i;					\
+		for (_i = 0; _i < (_count); _i++)	\
+			(_table)[_i] = _i;		\
+	} while (0)
+
+#define SAM9X7_FILL_TABLE(_to, _from, _count)		\
+	do {						\
+		u8 _i;					\
+		for (_i = 0; _i < (_count); _i++) {	\
+			(_to)[_i] = (_from)[_i];	\
+		}					\
+	} while (0)
+
+static DEFINE_SPINLOCK(pmc_pll_lock);
+static DEFINE_SPINLOCK(mck_lock);
+
+/**
+ * enum pll_ids - PLL clocks identifiers
+ * @PLL_ID_PLLA:	PLLA identifier
+ * @PLL_ID_UPLL:	UPLL identifier
+ * @PLL_ID_AUDIO:	Audio PLL identifier
+ * @PLL_ID_LVDS:	LVDS PLL identifier
+ * @PLL_ID_PLLA_DIV2:	PLLA DIV2 identifier
+ * @PLL_ID_MAX:		Max PLL Identifier
+ */
+enum pll_ids {
+	PLL_ID_PLLA,
+	PLL_ID_UPLL,
+	PLL_ID_AUDIO,
+	PLL_ID_LVDS,
+	PLL_ID_PLLA_DIV2,
+	PLL_ID_MAX,
+};
+
+/**
+ * enum pll_type - PLL type identifiers
+ * @PLL_TYPE_FRAC:	fractional PLL identifier
+ * @PLL_TYPE_DIV:	divider PLL identifier
+ */
+enum pll_type {
+	PLL_TYPE_FRAC,
+	PLL_TYPE_DIV,
+};
+
+static const struct clk_master_characteristics mck_characteristics = {
+	.output = { .min = 32000000, .max = 266666667 },
+	.divisors = { 1, 2, 4, 3 },
+	.have_div3_pres = 1,
+};
+
+static const struct clk_master_layout sam9x7_master_layout = {
+	.mask = 0x373,
+	.pres_shift = 4,
+	.offset = 0x28,
+};
+
+/* Fractional PLL core output range. */
+static const struct clk_range plla_core_outputs[] = {
+	{ .min = 375000000, .max = 1600000000 },
+};
+
+static const struct clk_range upll_core_outputs[] = {
+	{ .min = 600000000, .max = 1200000000 },
+};
+
+static const struct clk_range lvdspll_core_outputs[] = {
+	{ .min = 400000000, .max = 800000000 },
+};
+
+static const struct clk_range audiopll_core_outputs[] = {
+	{ .min = 400000000, .max = 800000000 },
+};
+
+static const struct clk_range plladiv2_core_outputs[] = {
+	{ .min = 375000000, .max = 1600000000 },
+};
+
+/* Fractional PLL output range. */
+static const struct clk_range plla_outputs[] = {
+	{ .min = 732421, .max = 800000000 },
+};
+
+static const struct clk_range upll_outputs[] = {
+	{ .min = 300000000, .max = 600000000 },
+};
+
+static const struct clk_range lvdspll_outputs[] = {
+	{ .min = 10000000, .max = 800000000 },
+};
+
+static const struct clk_range audiopll_outputs[] = {
+	{ .min = 10000000, .max = 800000000 },
+};
+
+static const struct clk_range plladiv2_outputs[] = {
+	{ .min = 366210, .max = 400000000 },
+};
+
+/* PLL characteristics. */
+static const struct clk_pll_characteristics plla_characteristics = {
+	.input = { .min = 20000000, .max = 50000000 },
+	.num_output = ARRAY_SIZE(plla_outputs),
+	.output = plla_outputs,
+	.core_output = plla_core_outputs,
+};
+
+static const struct clk_pll_characteristics upll_characteristics = {
+	.input = { .min = 20000000, .max = 50000000 },
+	.num_output = ARRAY_SIZE(upll_outputs),
+	.output = upll_outputs,
+	.core_output = upll_core_outputs,
+	.upll = true,
+};
+
+static const struct clk_pll_characteristics lvdspll_characteristics = {
+	.input = { .min = 20000000, .max = 50000000 },
+	.num_output = ARRAY_SIZE(lvdspll_outputs),
+	.output = lvdspll_outputs,
+	.core_output = lvdspll_core_outputs,
+};
+
+static const struct clk_pll_characteristics audiopll_characteristics = {
+	.input = { .min = 20000000, .max = 50000000 },
+	.num_output = ARRAY_SIZE(audiopll_outputs),
+	.output = audiopll_outputs,
+	.core_output = audiopll_core_outputs,
+};
+
+static const struct clk_pll_characteristics plladiv2_characteristics = {
+	.input = { .min = 20000000, .max = 50000000 },
+	.num_output = ARRAY_SIZE(plladiv2_outputs),
+	.output = plladiv2_outputs,
+	.core_output = plladiv2_core_outputs,
+};
+
+/* Layout for fractional PLL ID PLLA. */
+static const struct clk_pll_layout plla_frac_layout = {
+	.mul_mask = GENMASK(31, 24),
+	.frac_mask = GENMASK(21, 0),
+	.mul_shift = 24,
+	.frac_shift = 0,
+	.div2 = 1,
+};
+
+/* Layout for fractional PLLs. */
+static const struct clk_pll_layout pll_frac_layout = {
+	.mul_mask = GENMASK(31, 24),
+	.frac_mask = GENMASK(21, 0),
+	.mul_shift = 24,
+	.frac_shift = 0,
+};
+
+/* Layout for DIV PLLs. */
+static const struct clk_pll_layout pll_divpmc_layout = {
+	.div_mask = GENMASK(7, 0),
+	.endiv_mask = BIT(29),
+	.div_shift = 0,
+	.endiv_shift = 29,
+};
+
+/* Layout for DIV PLL ID PLLADIV2. */
+static const struct clk_pll_layout plladiv2_divpmc_layout = {
+	.div_mask = GENMASK(7, 0),
+	.endiv_mask = BIT(29),
+	.div_shift = 0,
+	.endiv_shift = 29,
+	.div2 = 1,
+};
+
+/* Layout for DIVIO dividers. */
+static const struct clk_pll_layout pll_divio_layout = {
+	.div_mask	= GENMASK(19, 12),
+	.endiv_mask	= BIT(30),
+	.div_shift	= 12,
+	.endiv_shift	= 30,
+};
+
+/*
+ * PLL clocks description
+ * @n:		clock name
+ * @p:		clock parent
+ * @l:		clock layout
+ * @t:		clock type
+ * @c:		pll characteristics
+ * @f:		true if clock is critical and cannot be disabled
+ * @eid:	export index in sam9x7->chws[] array
+ */
+static const struct {
+	const char *n;
+	const char *p;
+	const struct clk_pll_layout *l;
+	u8 t;
+	const struct clk_pll_characteristics *c;
+	unsigned long f;
+	u8 eid;
+} sam9x7_plls[][PLL_ID_MAX] = {
+	[PLL_ID_PLLA] = {
+		{
+			.n = "plla_fracck",
+			.p = "mainck",
+			.l = &plla_frac_layout,
+			.t = PLL_TYPE_FRAC,
+			.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
+			.c = &plla_characteristics,
+		},
+
+		{
+			.n = "plla_divpmcck",
+			.p = "plla_fracck",
+			.l = &pll_divpmc_layout,
+			.t = PLL_TYPE_DIV,
+			.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
+			.eid = PMC_PLLACK,
+			.c = &plla_characteristics,
+		},
+	},
+
+	[PLL_ID_UPLL] = {
+		{
+			.n = "upll_fracck",
+			.p = "main_osc",
+			.l = &pll_frac_layout,
+			.t = PLL_TYPE_FRAC,
+			.f = CLK_SET_RATE_GATE,
+			.c = &upll_characteristics,
+		},
+
+		{
+			.n = "upll_divpmcck",
+			.p = "upll_fracck",
+			.l = &pll_divpmc_layout,
+			.t = PLL_TYPE_DIV,
+			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+			     CLK_SET_RATE_PARENT,
+			.eid = PMC_UTMI,
+			.c = &upll_characteristics,
+		},
+	},
+
+	[PLL_ID_AUDIO] = {
+		{
+			.n = "audiopll_fracck",
+			.p = "main_osc",
+			.l = &pll_frac_layout,
+			.f = CLK_SET_RATE_GATE,
+			.c = &audiopll_characteristics,
+			.t = PLL_TYPE_FRAC,
+		},
+
+		{
+			.n = "audiopll_divpmcck",
+			.p = "audiopll_fracck",
+			.l = &pll_divpmc_layout,
+			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+			     CLK_SET_RATE_PARENT,
+			.c = &audiopll_characteristics,
+			.t = PLL_TYPE_DIV,
+		},
+
+		{
+			.n = "audiopll_diviock",
+			.p = "audiopll_fracck",
+			.l = &pll_divio_layout,
+			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+			     CLK_SET_RATE_PARENT,
+			.c = &audiopll_characteristics,
+			.t = PLL_TYPE_DIV,
+		},
+	},
+
+	[PLL_ID_LVDS] = {
+		{
+			.n = "lvdspll_fracck",
+			.p = "main_osc",
+			.l = &pll_frac_layout,
+			.f = CLK_SET_RATE_GATE,
+			.c = &lvdspll_characteristics,
+			.t = PLL_TYPE_FRAC,
+		},
+
+		{
+			.n = "lvdspll_divpmcck",
+			.p = "lvdspll_fracck",
+			.l = &pll_divpmc_layout,
+			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+			     CLK_SET_RATE_PARENT,
+			.c = &lvdspll_characteristics,
+			.t = PLL_TYPE_DIV,
+		},
+	},
+
+	[PLL_ID_PLLA_DIV2] = {
+		{
+			.n = "plla_div2pmcck",
+			.p = "plla_fracck",
+			.l = &plladiv2_divpmc_layout,
+			.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
+			.c = &plladiv2_characteristics,
+			.t = PLL_TYPE_DIV,
+		},
+	},
+};
+
+static const struct clk_programmable_layout sam9x7_programmable_layout = {
+	.pres_mask = 0xff,
+	.pres_shift = 8,
+	.css_mask = 0x1f,
+	.have_slck_mck = 0,
+	.is_pres_direct = 1,
+};
+
+static const struct clk_pcr_layout sam9x7_pcr_layout = {
+	.offset = 0x88,
+	.cmd = BIT(31),
+	.gckcss_mask = GENMASK(12, 8),
+	.pid_mask = GENMASK(6, 0),
+};
+
+static const struct {
+	char *n;
+	char *p;
+	u8 id;
+	unsigned long flags;
+} sam9x7_systemck[] = {
+	/*
+	 * ddrck feeds DDR controller and is enabled by bootloader thus we need
+	 * to keep it enabled in case there is no Linux consumer for it.
+	 */
+	{ .n = "ddrck",		.p = "masterck_div",	.id = 2,	.flags = CLK_IS_CRITICAL },
+	{ .n = "uhpck",		.p = "usbck",		.id = 6 },
+	{ .n = "pck0",		.p = "prog0",		.id = 8 },
+	{ .n = "pck1",		.p = "prog1",		.id = 9 },
+};
+
+/*
+ * Peripheral clocks description
+ * @n:		clock name
+ * @f:		true if clock is critical and cannot be disabled
+ * @id:		peripheral id
+ */
+static const struct {
+	char *n;
+	unsigned long f;
+	u8 id;
+} sam9x7_periphck[] = {
+	{ .n = "pioA_clk",	.id = 2, },
+	{ .n = "pioB_clk",	.id = 3, },
+	{ .n = "pioC_clk",	.id = 4, },
+	{ .n = "flex0_clk",	.id = 5, },
+	{ .n = "flex1_clk",	.id = 6, },
+	{ .n = "flex2_clk",	.id = 7, },
+	{ .n = "flex3_clk",	.id = 8, },
+	{ .n = "flex6_clk",	.id = 9, },
+	{ .n = "flex7_clk",	.id = 10, },
+	{ .n = "flex8_clk",	.id = 11, },
+	{ .n = "sdmmc0_clk",	.id = 12, },
+	{ .n = "flex4_clk",	.id = 13, },
+	{ .n = "flex5_clk",	.id = 14, },
+	{ .n = "flex9_clk",	.id = 15, },
+	{ .n = "flex10_clk",	.id = 16, },
+	{ .n = "tcb0_clk",	.id = 17, },
+	{ .n = "pwm_clk",	.id = 18, },
+	{ .n = "adc_clk",	.id = 19, },
+	{ .n = "dma0_clk",	.id = 20, },
+	{ .n = "uhphs_clk",	.id = 22, },
+	{ .n = "udphs_clk",	.id = 23, },
+	{ .n = "macb0_clk",	.id = 24, },
+	{ .n = "lcd_clk",	.id = 25, },
+	{ .n = "sdmmc1_clk",	.id = 26, },
+	{ .n = "ssc_clk",	.id = 28, },
+	{ .n = "can0_clk",	.id = 29, },
+	{ .n = "can1_clk",	.id = 30, },
+	{ .n = "flex11_clk",	.id = 32, },
+	{ .n = "flex12_clk",	.id = 33, },
+	{ .n = "i2s_clk",	.id = 34, },
+	{ .n = "qspi_clk",	.id = 35, },
+	{ .n = "gfx2d_clk",	.id = 36, },
+	{ .n = "pit64b0_clk",	.id = 37, },
+	{ .n = "trng_clk",	.id = 38, },
+	{ .n = "aes_clk",	.id = 39, },
+	{ .n = "tdes_clk",	.id = 40, },
+	{ .n = "sha_clk",	.id = 41, },
+	{ .n = "classd_clk",	.id = 42, },
+	{ .n = "isi_clk",	.id = 43, },
+	{ .n = "pioD_clk",	.id = 44, },
+	{ .n = "tcb1_clk",	.id = 45, },
+	{ .n = "dbgu_clk",	.id = 47, },
+	/*
+	 * mpddr_clk feeds DDR controller and is enabled by bootloader thus we
+	 * need to keep it enabled in case there is no Linux consumer for it.
+	 */
+	{ .n = "mpddr_clk",	.id = 49,	.f = CLK_IS_CRITICAL },
+	{ .n = "csi2dc_clk",	.id = 52, },
+	{ .n = "csi4l_clk",	.id = 53, },
+	{ .n = "dsi4l_clk",	.id = 54, },
+	{ .n = "lvdsc_clk",	.id = 56, },
+	{ .n = "pit64b1_clk",	.id = 58, },
+	{ .n = "puf_clk",	.id = 59, },
+	{ .n = "gmactsu_clk",	.id = 67, },
+};
+
+/*
+ * Generic clock description
+ * @n:			clock name
+ * @pp:			PLL parents
+ * @pp_mux_table:	PLL parents mux table
+ * @r:			clock output range
+ * @pp_chg_id:		id in parent array of changeable PLL parent
+ * @pp_count:		PLL parents count
+ * @id:			clock id
+ */
+static const struct {
+	const char *n;
+	const char *pp[8];
+	const char pp_mux_table[8];
+	struct clk_range r;
+	int pp_chg_id;
+	u8 pp_count;
+	u8 id;
+} sam9x7_gck[] = {
+	{
+		.n = "flex0_gclk",
+		.id = 5,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex1_gclk",
+		.id = 6,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex2_gclk",
+		.id = 7,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex3_gclk",
+		.id = 8,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex6_gclk",
+		.id = 9,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex7_gclk",
+		.id = 10,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex8_gclk",
+		.id = 11,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "sdmmc0_gclk",
+		.id = 12,
+		.r = { .max = 105000000 },
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex4_gclk",
+		.id = 13,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex5_gclk",
+		.id = 14,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex9_gclk",
+		.id = 15,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex10_gclk",
+		.id = 16,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "tcb0_gclk",
+		.id = 17,
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "adc_gclk",
+		.id = 19,
+		.pp = { "upll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 5, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "lcd_gclk",
+		.id = 25,
+		.r = { .max = 75000000 },
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "sdmmc1_gclk",
+		.id = 26,
+		.r = { .max = 105000000 },
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "mcan0_gclk",
+		.id = 29,
+		.r = { .max = 80000000 },
+		.pp = { "upll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 5, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "mcan1_gclk",
+		.id = 30,
+		.r = { .max = 80000000 },
+		.pp = { "upll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 5, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex11_gclk",
+		.id = 32,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex12_gclk",
+		.id = 33,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "i2s_gclk",
+		.id = 34,
+		.r = { .max = 100000000 },
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "qspi_gclk",
+		.id = 35,
+		.r = { .max = 20000000 },
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "pit64b0_gclk",
+		.id = 37,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "classd_gclk",
+		.id = 42,
+		.r = { .max = 100000000 },
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "tcb1_gclk",
+		.id = 45,
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "dbgu_gclk",
+		.id = 47,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "mipiphy_gclk",
+		.id = 55,
+		.r = { .max = 27000000 },
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "pit64b1_gclk",
+		.id = 58,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "gmac_gclk",
+		.id = 67,
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+};
+
+static void __init sam9x7_pmc_setup(struct device_node *np)
+{
+	struct clk_range range = CLK_RANGE(0, 0);
+	const char *td_slck_name, *md_slck_name, *mainxtal_name;
+	struct pmc_data *sam9x7_pmc;
+	const char *parent_names[9];
+	void **alloc_mem = NULL;
+	int alloc_mem_size = 0;
+	struct clk_hw *main_osc_hw;
+	struct regmap *regmap;
+	struct clk_hw *hw;
+	int i, j;
+
+	i = of_property_match_string(np, "clock-names", "td_slck");
+	if (i < 0)
+		return;
+
+	td_slck_name = of_clk_get_parent_name(np, i);
+
+	i = of_property_match_string(np, "clock-names", "md_slck");
+	if (i < 0)
+		return;
+
+	md_slck_name = of_clk_get_parent_name(np, i);
+
+	i = of_property_match_string(np, "clock-names", "main_xtal");
+	if (i < 0)
+		return;
+	mainxtal_name = of_clk_get_parent_name(np, i);
+
+	regmap = device_node_to_regmap(np);
+	if (IS_ERR(regmap))
+		return;
+
+	sam9x7_pmc = pmc_data_allocate(PMC_PLLACK + 1,
+				       nck(sam9x7_systemck),
+				       nck(sam9x7_periphck),
+				       nck(sam9x7_gck), 8);
+	if (!sam9x7_pmc)
+		return;
+
+	alloc_mem = kmalloc(sizeof(void *) *
+				(ARRAY_SIZE(sam9x7_gck)),
+				GFP_KERNEL);
+	if (!alloc_mem)
+		goto err_free;
+
+	hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
+					   50000000);
+	if (IS_ERR(hw))
+		goto err_free;
+
+	hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, 0);
+	if (IS_ERR(hw))
+		goto err_free;
+	main_osc_hw = hw;
+
+	parent_names[0] = "main_rc_osc";
+	parent_names[1] = "main_osc";
+	hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
+	if (IS_ERR(hw))
+		goto err_free;
+
+	sam9x7_pmc->chws[PMC_MAIN] = hw;
+
+	for (i = 0; i < PLL_ID_MAX; i++) {
+		for (j = 0; j < 3; j++) {
+			struct clk_hw *parent_hw;
+
+			if (!sam9x7_plls[i][j].n)
+				continue;
+
+			switch (sam9x7_plls[i][j].t) {
+			case PLL_TYPE_FRAC:
+				if (!strcmp(sam9x7_plls[i][j].p, "mainck"))
+					parent_hw = sam9x7_pmc->chws[PMC_MAIN];
+				else if (!strcmp(sam9x7_plls[i][j].p, "main_osc"))
+					parent_hw = main_osc_hw;
+				else
+					parent_hw = __clk_get_hw(of_clk_get_by_name
+								 (np, sam9x7_plls[i][j].p));
+
+				hw = sam9x60_clk_register_frac_pll(regmap,
+								   &pmc_pll_lock,
+								   sam9x7_plls[i][j].n,
+								   sam9x7_plls[i][j].p,
+								   parent_hw, i,
+								   sam9x7_plls[i][j].c,
+								   sam9x7_plls[i][j].l,
+								   sam9x7_plls[i][j].f);
+				break;
+
+			case PLL_TYPE_DIV:
+				hw = sam9x60_clk_register_div_pll(regmap,
+								  &pmc_pll_lock,
+								  sam9x7_plls[i][j].n,
+								  sam9x7_plls[i][j].p, i,
+								  sam9x7_plls[i][j].c,
+								  sam9x7_plls[i][j].l,
+								  sam9x7_plls[i][j].f, 0);
+				break;
+
+			default:
+				continue;
+			}
+
+			if (IS_ERR(hw))
+				goto err_free;
+
+			if (sam9x7_plls[i][j].eid)
+				sam9x7_pmc->chws[sam9x7_plls[i][j].eid] = hw;
+		}
+	}
+
+	parent_names[0] = md_slck_name;
+	parent_names[1] = "mainck";
+	parent_names[2] = "plla_divpmcck";
+	parent_names[3] = "upll_divpmcck";
+	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
+					   parent_names, &sam9x7_master_layout,
+					   &mck_characteristics, &mck_lock);
+	if (IS_ERR(hw))
+		goto err_free;
+
+	hw = at91_clk_register_master_div(regmap, "masterck_div",
+					  "masterck_pres", &sam9x7_master_layout,
+					  &mck_characteristics, &mck_lock,
+					  CLK_SET_RATE_GATE, 0);
+	if (IS_ERR(hw))
+		goto err_free;
+
+	sam9x7_pmc->chws[PMC_MCK] = hw;
+
+	parent_names[0] = "plla_divpmcck";
+	parent_names[1] = "upll_divpmcck";
+	parent_names[2] = "main_osc";
+	hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3);
+	if (IS_ERR(hw))
+		goto err_free;
+
+	parent_names[0] = md_slck_name;
+	parent_names[1] = td_slck_name;
+	parent_names[2] = "mainck";
+	parent_names[3] = "masterck_div";
+	parent_names[4] = "plla_divpmcck";
+	parent_names[5] = "upll_divpmcck";
+	parent_names[6] = "audiopll_divpmcck";
+	for (i = 0; i < 2; i++) {
+		char name[6];
+
+		snprintf(name, sizeof(name), "prog%d", i);
+
+		hw = at91_clk_register_programmable(regmap, name,
+						    parent_names, 7, i,
+						    &sam9x7_programmable_layout,
+						    NULL);
+		if (IS_ERR(hw))
+			goto err_free;
+
+		sam9x7_pmc->pchws[i] = hw;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(sam9x7_systemck); i++) {
+		hw = at91_clk_register_system(regmap, sam9x7_systemck[i].n,
+					      sam9x7_systemck[i].p,
+					      sam9x7_systemck[i].id,
+					      sam9x7_systemck[i].flags);
+		if (IS_ERR(hw))
+			goto err_free;
+
+		sam9x7_pmc->shws[sam9x7_systemck[i].id] = hw;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(sam9x7_periphck); i++) {
+		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
+							 &sam9x7_pcr_layout,
+							 sam9x7_periphck[i].n,
+							 "masterck_div",
+							 sam9x7_periphck[i].id,
+							 &range, INT_MIN,
+							 sam9x7_periphck[i].f);
+		if (IS_ERR(hw))
+			goto err_free;
+
+		sam9x7_pmc->phws[sam9x7_periphck[i].id] = hw;
+	}
+
+	parent_names[0] = md_slck_name;
+	parent_names[1] = td_slck_name;
+	parent_names[2] = "mainck";
+	parent_names[3] = "masterck_div";
+	for (i = 0; i < ARRAY_SIZE(sam9x7_gck); i++) {
+		u8 num_parents = 4 + sam9x7_gck[i].pp_count;
+		u32 *mux_table;
+
+		mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
+					  GFP_KERNEL);
+		if (!mux_table)
+			goto err_free;
+
+		SAM9X7_INIT_TABLE(mux_table, 4);
+		SAM9X7_FILL_TABLE(&mux_table[4], sam9x7_gck[i].pp_mux_table,
+				  sam9x7_gck[i].pp_count);
+		SAM9X7_FILL_TABLE(&parent_names[4], sam9x7_gck[i].pp,
+				  sam9x7_gck[i].pp_count);
+
+		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
+						 &sam9x7_pcr_layout,
+						 sam9x7_gck[i].n,
+						 parent_names, mux_table,
+						 num_parents,
+						 sam9x7_gck[i].id,
+						 &sam9x7_gck[i].r,
+						 sam9x7_gck[i].pp_chg_id);
+		if (IS_ERR(hw))
+			goto err_free;
+
+		sam9x7_pmc->ghws[sam9x7_gck[i].id] = hw;
+		alloc_mem[alloc_mem_size++] = mux_table;
+	}
+
+	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x7_pmc);
+
+	return;
+
+err_free:
+	if (alloc_mem) {
+		for (i = 0; i < alloc_mem_size; i++)
+			kfree(alloc_mem[i]);
+		kfree(alloc_mem);
+	}
+	kfree(sam9x7_pmc);
+}
+
+/* Some clks are used for a clocksource */
+CLK_OF_DECLARE(sam9x7_pmc, "microchip,sam9x7-pmc", sam9x7_pmc_setup);
-- 
2.25.1

Re: [PATCH 14/21] clk: at91: sam9x7: add sam9x7 pmc driver

[Simon Horman]

On Sun, Jun 04, 2023 at 01:32:36AM +0530, Varshini Rajendran wrote:
> Add a driver for the PMC clocks of sam9x7 Soc family
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

...

> +static void __init sam9x7_pmc_setup(struct device_node *np)
> +{
> +	struct clk_range range = CLK_RANGE(0, 0);
> +	const char *td_slck_name, *md_slck_name, *mainxtal_name;
> +	struct pmc_data *sam9x7_pmc;
> +	const char *parent_names[9];
> +	void **alloc_mem = NULL;
> +	int alloc_mem_size = 0;
> +	struct clk_hw *main_osc_hw;
> +	struct regmap *regmap;
> +	struct clk_hw *hw;
> +	int i, j;
> +
> +	i = of_property_match_string(np, "clock-names", "td_slck");
> +	if (i < 0)
> +		return;
> +
> +	td_slck_name = of_clk_get_parent_name(np, i);
> +
> +	i = of_property_match_string(np, "clock-names", "md_slck");
> +	if (i < 0)
> +		return;
> +
> +	md_slck_name = of_clk_get_parent_name(np, i);
> +
> +	i = of_property_match_string(np, "clock-names", "main_xtal");
> +	if (i < 0)
> +		return;
> +	mainxtal_name = of_clk_get_parent_name(np, i);
> +
> +	regmap = device_node_to_regmap(np);
> +	if (IS_ERR(regmap))
> +		return;
> +
> +	sam9x7_pmc = pmc_data_allocate(PMC_PLLACK + 1,
> +				       nck(sam9x7_systemck),
> +				       nck(sam9x7_periphck),
> +				       nck(sam9x7_gck), 8);
> +	if (!sam9x7_pmc)
> +		return;
> +
> +	alloc_mem = kmalloc(sizeof(void *) *
> +				(ARRAY_SIZE(sam9x7_gck)),
> +				GFP_KERNEL);
> +	if (!alloc_mem)
> +		goto err_free;
> +
> +	hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
> +					   50000000);
> +	if (IS_ERR(hw))
> +		goto err_free;
> +
> +	hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, 0);
> +	if (IS_ERR(hw))
> +		goto err_free;
> +	main_osc_hw = hw;
> +
> +	parent_names[0] = "main_rc_osc";
> +	parent_names[1] = "main_osc";
> +	hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
> +	if (IS_ERR(hw))
> +		goto err_free;
> +
> +	sam9x7_pmc->chws[PMC_MAIN] = hw;
> +
> +	for (i = 0; i < PLL_ID_MAX; i++) {
> +		for (j = 0; j < 3; j++) {
> +			struct clk_hw *parent_hw;
> +
> +			if (!sam9x7_plls[i][j].n)
> +				continue;
> +
> +			switch (sam9x7_plls[i][j].t) {
> +			case PLL_TYPE_FRAC:
> +				if (!strcmp(sam9x7_plls[i][j].p, "mainck"))
> +					parent_hw = sam9x7_pmc->chws[PMC_MAIN];
> +				else if (!strcmp(sam9x7_plls[i][j].p, "main_osc"))
> +					parent_hw = main_osc_hw;
> +				else
> +					parent_hw = __clk_get_hw(of_clk_get_by_name
> +								 (np, sam9x7_plls[i][j].p));
> +
> +				hw = sam9x60_clk_register_frac_pll(regmap,
> +								   &pmc_pll_lock,
> +								   sam9x7_plls[i][j].n,
> +								   sam9x7_plls[i][j].p,
> +								   parent_hw, i,
> +								   sam9x7_plls[i][j].c,
> +								   sam9x7_plls[i][j].l,
> +								   sam9x7_plls[i][j].f);
> +				break;
> +
> +			case PLL_TYPE_DIV:
> +				hw = sam9x60_clk_register_div_pll(regmap,
> +								  &pmc_pll_lock,
> +								  sam9x7_plls[i][j].n,
> +								  sam9x7_plls[i][j].p, i,
> +								  sam9x7_plls[i][j].c,
> +								  sam9x7_plls[i][j].l,
> +								  sam9x7_plls[i][j].f, 0);
> +				break;
> +
> +			default:
> +				continue;
> +			}
> +
> +			if (IS_ERR(hw))
> +				goto err_free;
> +
> +			if (sam9x7_plls[i][j].eid)
> +				sam9x7_pmc->chws[sam9x7_plls[i][j].eid] = hw;
> +		}
> +	}
> +
> +	parent_names[0] = md_slck_name;
> +	parent_names[1] = "mainck";
> +	parent_names[2] = "plla_divpmcck";
> +	parent_names[3] = "upll_divpmcck";
> +	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
> +					   parent_names, &sam9x7_master_layout,
> +					   &mck_characteristics, &mck_lock);
> +	if (IS_ERR(hw))
> +		goto err_free;
> +
> +	hw = at91_clk_register_master_div(regmap, "masterck_div",
> +					  "masterck_pres", &sam9x7_master_layout,
> +					  &mck_characteristics, &mck_lock,
> +					  CLK_SET_RATE_GATE, 0);
> +	if (IS_ERR(hw))
> +		goto err_free;
> +
> +	sam9x7_pmc->chws[PMC_MCK] = hw;
> +
> +	parent_names[0] = "plla_divpmcck";
> +	parent_names[1] = "upll_divpmcck";
> +	parent_names[2] = "main_osc";
> +	hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3);
> +	if (IS_ERR(hw))
> +		goto err_free;
> +
> +	parent_names[0] = md_slck_name;
> +	parent_names[1] = td_slck_name;
> +	parent_names[2] = "mainck";
> +	parent_names[3] = "masterck_div";
> +	parent_names[4] = "plla_divpmcck";
> +	parent_names[5] = "upll_divpmcck";
> +	parent_names[6] = "audiopll_divpmcck";
> +	for (i = 0; i < 2; i++) {
> +		char name[6];
> +
> +		snprintf(name, sizeof(name), "prog%d", i);
> +
> +		hw = at91_clk_register_programmable(regmap, name,
> +						    parent_names, 7, i,
> +						    &sam9x7_programmable_layout,
> +						    NULL);
> +		if (IS_ERR(hw))
> +			goto err_free;
> +
> +		sam9x7_pmc->pchws[i] = hw;
> +	}
> +
> +	for (i = 0; i < ARRAY_SIZE(sam9x7_systemck); i++) {
> +		hw = at91_clk_register_system(regmap, sam9x7_systemck[i].n,
> +					      sam9x7_systemck[i].p,
> +					      sam9x7_systemck[i].id,
> +					      sam9x7_systemck[i].flags);
> +		if (IS_ERR(hw))
> +			goto err_free;
> +
> +		sam9x7_pmc->shws[sam9x7_systemck[i].id] = hw;
> +	}
> +
> +	for (i = 0; i < ARRAY_SIZE(sam9x7_periphck); i++) {
> +		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
> +							 &sam9x7_pcr_layout,
> +							 sam9x7_periphck[i].n,
> +							 "masterck_div",
> +							 sam9x7_periphck[i].id,
> +							 &range, INT_MIN,
> +							 sam9x7_periphck[i].f);
> +		if (IS_ERR(hw))
> +			goto err_free;
> +
> +		sam9x7_pmc->phws[sam9x7_periphck[i].id] = hw;
> +	}
> +
> +	parent_names[0] = md_slck_name;
> +	parent_names[1] = td_slck_name;
> +	parent_names[2] = "mainck";
> +	parent_names[3] = "masterck_div";
> +	for (i = 0; i < ARRAY_SIZE(sam9x7_gck); i++) {
> +		u8 num_parents = 4 + sam9x7_gck[i].pp_count;
> +		u32 *mux_table;
> +
> +		mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
> +					  GFP_KERNEL);
> +		if (!mux_table)
> +			goto err_free;
> +
> +		SAM9X7_INIT_TABLE(mux_table, 4);
> +		SAM9X7_FILL_TABLE(&mux_table[4], sam9x7_gck[i].pp_mux_table,
> +				  sam9x7_gck[i].pp_count);
> +		SAM9X7_FILL_TABLE(&parent_names[4], sam9x7_gck[i].pp,
> +				  sam9x7_gck[i].pp_count);
> +
> +		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
> +						 &sam9x7_pcr_layout,
> +						 sam9x7_gck[i].n,
> +						 parent_names, mux_table,
> +						 num_parents,
> +						 sam9x7_gck[i].id,
> +						 &sam9x7_gck[i].r,
> +						 sam9x7_gck[i].pp_chg_id);
> +		if (IS_ERR(hw))
> +			goto err_free;
> +
> +		sam9x7_pmc->ghws[sam9x7_gck[i].id] = hw;
> +		alloc_mem[alloc_mem_size++] = mux_table;
> +	}
> +
> +	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x7_pmc);
> +

Hi Varshini,

alloc_mem appears to be leaked here.

> +	return;
> +
> +err_free:
> +	if (alloc_mem) {
> +		for (i = 0; i < alloc_mem_size; i++)
> +			kfree(alloc_mem[i]);
> +		kfree(alloc_mem);
> +	}
> +	kfree(sam9x7_pmc);
> +}
> +
> +/* Some clks are used for a clocksource */
> +CLK_OF_DECLARE(sam9x7_pmc, "microchip,sam9x7-pmc", sam9x7_pmc_setup);

I'm sure I'm missing some thing obvious, but I was unable to
find the binding for "microchip,sam9x7-pmc".

Re: [PATCH 14/21] clk: at91: sam9x7: add sam9x7 pmc driver

[Claudiu.Beznea]

On 03.06.2023 23:02, Varshini Rajendran wrote:
> Add a driver for the PMC clocks of sam9x7 Soc family

End the statement with a dot. Valid for commit messages of the other
patches in this series.

> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  drivers/clk/at91/Makefile |   1 +
>  drivers/clk/at91/sam9x7.c | 947 ++++++++++++++++++++++++++++++++++++++
>  2 files changed, 948 insertions(+)
>  create mode 100644 drivers/clk/at91/sam9x7.c
> 
> diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
> index 89061b85e7d2..8e3684ba2c74 100644
> --- a/drivers/clk/at91/Makefile
> +++ b/drivers/clk/at91/Makefile
> @@ -20,6 +20,7 @@ obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9rl.o at91sam9x5.o dt-compat.
>  obj-$(CONFIG_SOC_AT91SAM9) += at91sam9g45.o dt-compat.o
>  obj-$(CONFIG_SOC_AT91SAM9) += at91sam9n12.o at91sam9x5.o dt-compat.o
>  obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o
> +obj-$(CONFIG_SOC_SAM9X7) += sam9x7.o
>  obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o dt-compat.o
>  obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o dt-compat.o
>  obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o dt-compat.o
> diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
> new file mode 100644
> index 000000000000..8232a2af14be
> --- /dev/null
> +++ b/drivers/clk/at91/sam9x7.c
> @@ -0,0 +1,947 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SAM9X7 PMC code.
> + *
> + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries

2023?

> + *
> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
> + *
> + */
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/slab.h>
> +
> +#include <dt-bindings/clock/at91.h>
> +
> +#include "pmc.h"
> +
> +#define SAM9X7_INIT_TABLE(_table, _count)		\
> +	do {						\
> +		u8 _i;					\
> +		for (_i = 0; _i < (_count); _i++)	\
> +			(_table)[_i] = _i;		\
> +	} while (0)
> +
> +#define SAM9X7_FILL_TABLE(_to, _from, _count)		\
> +	do {						\
> +		u8 _i;					\
> +		for (_i = 0; _i < (_count); _i++) {	\
> +			(_to)[_i] = (_from)[_i];	\
> +		}					\
> +	} while (0)

Something similar is used on SAMA7G5. It could be export it in pmc.h

> +
> +static DEFINE_SPINLOCK(pmc_pll_lock);
> +static DEFINE_SPINLOCK(mck_lock);
> +
> +/**
> + * enum pll_ids - PLL clocks identifiers
> + * @PLL_ID_PLLA:	PLLA identifier
> + * @PLL_ID_UPLL:	UPLL identifier
> + * @PLL_ID_AUDIO:	Audio PLL identifier
> + * @PLL_ID_LVDS:	LVDS PLL identifier
> + * @PLL_ID_PLLA_DIV2:	PLLA DIV2 identifier
> + * @PLL_ID_MAX:		Max PLL Identifier
> + */
> +enum pll_ids {
> +	PLL_ID_PLLA,
> +	PLL_ID_UPLL,
> +	PLL_ID_AUDIO,
> +	PLL_ID_LVDS,
> +	PLL_ID_PLLA_DIV2,
> +	PLL_ID_MAX,
> +};
> +
> +/**
> + * enum pll_type - PLL type identifiers
> + * @PLL_TYPE_FRAC:	fractional PLL identifier
> + * @PLL_TYPE_DIV:	divider PLL identifier
> + */
> +enum pll_type {
> +	PLL_TYPE_FRAC,
> +	PLL_TYPE_DIV,
> +};
> +
> +static const struct clk_master_characteristics mck_characteristics = {
> +	.output = { .min = 32000000, .max = 266666667 },
> +	.divisors = { 1, 2, 4, 3 },

5 is also available in datasheet here:
https://ww1.microchip.com/downloads/aemDocuments/documents/MPU32/ProductDocuments/DataSheets/SAM9X7-Series-Data-Sheet-DS60001813.pdf

> +	.have_div3_pres = 1,
> +};
> +
> +static const struct clk_master_layout sam9x7_master_layout = {
> +	.mask = 0x373,
> +	.pres_shift = 4,
> +	.offset = 0x28,
> +};
> +
> +/* Fractional PLL core output range. */
> +static const struct clk_range plla_core_outputs[] = {
> +	{ .min = 375000000, .max = 1600000000 },
> +};
> +
> +static const struct clk_range upll_core_outputs[] = {
> +	{ .min = 600000000, .max = 1200000000 },
> +};
> +
> +static const struct clk_range lvdspll_core_outputs[] = {
> +	{ .min = 400000000, .max = 800000000 },
> +};
> +
> +static const struct clk_range audiopll_core_outputs[] = {
> +	{ .min = 400000000, .max = 800000000 },
> +};
> +
> +static const struct clk_range plladiv2_core_outputs[] = {
> +	{ .min = 375000000, .max = 1600000000 },
> +};
> +
> +/* Fractional PLL output range. */
> +static const struct clk_range plla_outputs[] = {
> +	{ .min = 732421, .max = 800000000 },
> +};
> +
> +static const struct clk_range upll_outputs[] = {
> +	{ .min = 300000000, .max = 600000000 },
> +};
> +
> +static const struct clk_range lvdspll_outputs[] = {
> +	{ .min = 10000000, .max = 800000000 },
> +};
> +
> +static const struct clk_range audiopll_outputs[] = {
> +	{ .min = 10000000, .max = 800000000 },
> +};
> +
> +static const struct clk_range plladiv2_outputs[] = {
> +	{ .min = 366210, .max = 400000000 },
> +};
> +
> +/* PLL characteristics. */
> +static const struct clk_pll_characteristics plla_characteristics = {
> +	.input = { .min = 20000000, .max = 50000000 },
> +	.num_output = ARRAY_SIZE(plla_outputs),
> +	.output = plla_outputs,
> +	.core_output = plla_core_outputs,
> +};
> +
> +static const struct clk_pll_characteristics upll_characteristics = {
> +	.input = { .min = 20000000, .max = 50000000 },
> +	.num_output = ARRAY_SIZE(upll_outputs),
> +	.output = upll_outputs,
> +	.core_output = upll_core_outputs,
> +	.upll = true,
> +};
> +
> +static const struct clk_pll_characteristics lvdspll_characteristics = {
> +	.input = { .min = 20000000, .max = 50000000 },
> +	.num_output = ARRAY_SIZE(lvdspll_outputs),
> +	.output = lvdspll_outputs,
> +	.core_output = lvdspll_core_outputs,
> +};
> +
> +static const struct clk_pll_characteristics audiopll_characteristics = {
> +	.input = { .min = 20000000, .max = 50000000 },
> +	.num_output = ARRAY_SIZE(audiopll_outputs),
> +	.output = audiopll_outputs,
> +	.core_output = audiopll_core_outputs,
> +};
> +
> +static const struct clk_pll_characteristics plladiv2_characteristics = {
> +	.input = { .min = 20000000, .max = 50000000 },
> +	.num_output = ARRAY_SIZE(plladiv2_outputs),
> +	.output = plladiv2_outputs,
> +	.core_output = plladiv2_core_outputs,
> +};
> +
> +/* Layout for fractional PLL ID PLLA. */
> +static const struct clk_pll_layout plla_frac_layout = {
> +	.mul_mask = GENMASK(31, 24),
> +	.frac_mask = GENMASK(21, 0),
> +	.mul_shift = 24,
> +	.frac_shift = 0,
> +	.div2 = 1,
> +};
> +
> +/* Layout for fractional PLLs. */
> +static const struct clk_pll_layout pll_frac_layout = {
> +	.mul_mask = GENMASK(31, 24),
> +	.frac_mask = GENMASK(21, 0),
> +	.mul_shift = 24,
> +	.frac_shift = 0,
> +};
> +
> +/* Layout for DIV PLLs. */
> +static const struct clk_pll_layout pll_divpmc_layout = {
> +	.div_mask = GENMASK(7, 0),
> +	.endiv_mask = BIT(29),
> +	.div_shift = 0,
> +	.endiv_shift = 29,
> +};
> +
> +/* Layout for DIV PLL ID PLLADIV2. */
> +static const struct clk_pll_layout plladiv2_divpmc_layout = {
> +	.div_mask = GENMASK(7, 0),
> +	.endiv_mask = BIT(29),
> +	.div_shift = 0,
> +	.endiv_shift = 29,
> +	.div2 = 1,
> +};
> +
> +/* Layout for DIVIO dividers. */
> +static const struct clk_pll_layout pll_divio_layout = {
> +	.div_mask	= GENMASK(19, 12),
> +	.endiv_mask	= BIT(30),
> +	.div_shift	= 12,
> +	.endiv_shift	= 30,
> +};
> +
> +/*
> + * PLL clocks description
> + * @n:		clock name
> + * @p:		clock parent
> + * @l:		clock layout
> + * @t:		clock type
> + * @c:		pll characteristics
> + * @f:		true if clock is critical and cannot be disabled
> + * @eid:	export index in sam9x7->chws[] array
> + */
> +static const struct {
> +	const char *n;
> +	const char *p;
> +	const struct clk_pll_layout *l;
> +	u8 t;
> +	const struct clk_pll_characteristics *c;
> +	unsigned long f;
> +	u8 eid;
> +} sam9x7_plls[][PLL_ID_MAX] = {
> +	[PLL_ID_PLLA] = {
> +		{
> +			.n = "plla_fracck",
> +			.p = "mainck",
> +			.l = &plla_frac_layout,
> +			.t = PLL_TYPE_FRAC,

Add here a comment about the necessity of having CLK_IS_CRITICAL. Same for
the other places where CLK_IS_CRITICAL is used.

> +			.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
> +			.c = &plla_characteristics,
> +		},
> +
> +		{
> +			.n = "plla_divpmcck",
> +			.p = "plla_fracck",
> +			.l = &pll_divpmc_layout,
> +			.t = PLL_TYPE_DIV,
> +			.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
> +			.eid = PMC_PLLACK,
> +			.c = &plla_characteristics,
> +		},
> +	},
> +
> +	[PLL_ID_UPLL] = {
> +		{
> +			.n = "upll_fracck",
> +			.p = "main_osc",
> +			.l = &pll_frac_layout,
> +			.t = PLL_TYPE_FRAC,
> +			.f = CLK_SET_RATE_GATE,
> +			.c = &upll_characteristics,
> +		},
> +
> +		{
> +			.n = "upll_divpmcck",
> +			.p = "upll_fracck",
> +			.l = &pll_divpmc_layout,
> +			.t = PLL_TYPE_DIV,
> +			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
> +			     CLK_SET_RATE_PARENT,
> +			.eid = PMC_UTMI,
> +			.c = &upll_characteristics,
> +		},
> +	},
> +
> +	[PLL_ID_AUDIO] = {
> +		{
> +			.n = "audiopll_fracck",
> +			.p = "main_osc",
> +			.l = &pll_frac_layout,
> +			.f = CLK_SET_RATE_GATE,
> +			.c = &audiopll_characteristics,
> +			.t = PLL_TYPE_FRAC,
> +		},
> +
> +		{
> +			.n = "audiopll_divpmcck",
> +			.p = "audiopll_fracck",
> +			.l = &pll_divpmc_layout,
> +			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
> +			     CLK_SET_RATE_PARENT,
> +			.c = &audiopll_characteristics,
> +			.t = PLL_TYPE_DIV,
> +		},
> +
> +		{
> +			.n = "audiopll_diviock",
> +			.p = "audiopll_fracck",
> +			.l = &pll_divio_layout,
> +			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
> +			     CLK_SET_RATE_PARENT,
> +			.c = &audiopll_characteristics,
> +			.t = PLL_TYPE_DIV,
> +		},
> +	},
> +
> +	[PLL_ID_LVDS] = {
> +		{
> +			.n = "lvdspll_fracck",
> +			.p = "main_osc",
> +			.l = &pll_frac_layout,
> +			.f = CLK_SET_RATE_GATE,
> +			.c = &lvdspll_characteristics,
> +			.t = PLL_TYPE_FRAC,
> +		},
> +
> +		{
> +			.n = "lvdspll_divpmcck",
> +			.p = "lvdspll_fracck",
> +			.l = &pll_divpmc_layout,
> +			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
> +			     CLK_SET_RATE_PARENT,
> +			.c = &lvdspll_characteristics,
> +			.t = PLL_TYPE_DIV,
> +		},
> +	},
> +
> +	[PLL_ID_PLLA_DIV2] = {
> +		{
> +			.n = "plla_div2pmcck",
> +			.p = "plla_fracck",
> +			.l = &plladiv2_divpmc_layout,
> +			.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
> +			.c = &plladiv2_characteristics,
> +			.t = PLL_TYPE_DIV,
> +		},
> +	},
> +};
> +
> +static const struct clk_programmable_layout sam9x7_programmable_layout = {
> +	.pres_mask = 0xff,
> +	.pres_shift = 8,
> +	.css_mask = 0x1f,
> +	.have_slck_mck = 0,
> +	.is_pres_direct = 1,
> +};
> +
> +static const struct clk_pcr_layout sam9x7_pcr_layout = {
> +	.offset = 0x88,
> +	.cmd = BIT(31),
> +	.gckcss_mask = GENMASK(12, 8),
> +	.pid_mask = GENMASK(6, 0),
> +};
> +
> +static const struct {
> +	char *n;
> +	char *p;
> +	u8 id;
> +	unsigned long flags;
> +} sam9x7_systemck[] = {
> +	/*
> +	 * ddrck feeds DDR controller and is enabled by bootloader thus we need
> +	 * to keep it enabled in case there is no Linux consumer for it.
> +	 */
> +	{ .n = "ddrck",		.p = "masterck_div",	.id = 2,	.flags = CLK_IS_CRITICAL },
> +	{ .n = "uhpck",		.p = "usbck",		.id = 6 },
> +	{ .n = "pck0",		.p = "prog0",		.id = 8 },
> +	{ .n = "pck1",		.p = "prog1",		.id = 9 },
> +};
> +
> +/*
> + * Peripheral clocks description
> + * @n:		clock name
> + * @f:		true if clock is critical and cannot be disabled
> + * @id:		peripheral id
> + */
> +static const struct {
> +	char *n;
> +	unsigned long f;
> +	u8 id;
> +} sam9x7_periphck[] = {
> +	{ .n = "pioA_clk",	.id = 2, },
> +	{ .n = "pioB_clk",	.id = 3, },
> +	{ .n = "pioC_clk",	.id = 4, },
> +	{ .n = "flex0_clk",	.id = 5, },
> +	{ .n = "flex1_clk",	.id = 6, },
> +	{ .n = "flex2_clk",	.id = 7, },
> +	{ .n = "flex3_clk",	.id = 8, },
> +	{ .n = "flex6_clk",	.id = 9, },
> +	{ .n = "flex7_clk",	.id = 10, },
> +	{ .n = "flex8_clk",	.id = 11, },
> +	{ .n = "sdmmc0_clk",	.id = 12, },
> +	{ .n = "flex4_clk",	.id = 13, },
> +	{ .n = "flex5_clk",	.id = 14, },
> +	{ .n = "flex9_clk",	.id = 15, },
> +	{ .n = "flex10_clk",	.id = 16, },
> +	{ .n = "tcb0_clk",	.id = 17, },
> +	{ .n = "pwm_clk",	.id = 18, },
> +	{ .n = "adc_clk",	.id = 19, },
> +	{ .n = "dma0_clk",	.id = 20, },
> +	{ .n = "uhphs_clk",	.id = 22, },
> +	{ .n = "udphs_clk",	.id = 23, },
> +	{ .n = "macb0_clk",	.id = 24, },
> +	{ .n = "lcd_clk",	.id = 25, },
> +	{ .n = "sdmmc1_clk",	.id = 26, },
> +	{ .n = "ssc_clk",	.id = 28, },
> +	{ .n = "can0_clk",	.id = 29, },
> +	{ .n = "can1_clk",	.id = 30, },
> +	{ .n = "flex11_clk",	.id = 32, },
> +	{ .n = "flex12_clk",	.id = 33, },
> +	{ .n = "i2s_clk",	.id = 34, },
> +	{ .n = "qspi_clk",	.id = 35, },
> +	{ .n = "gfx2d_clk",	.id = 36, },
> +	{ .n = "pit64b0_clk",	.id = 37, },
> +	{ .n = "trng_clk",	.id = 38, },
> +	{ .n = "aes_clk",	.id = 39, },
> +	{ .n = "tdes_clk",	.id = 40, },
> +	{ .n = "sha_clk",	.id = 41, },
> +	{ .n = "classd_clk",	.id = 42, },
> +	{ .n = "isi_clk",	.id = 43, },
> +	{ .n = "pioD_clk",	.id = 44, },
> +	{ .n = "tcb1_clk",	.id = 45, },
> +	{ .n = "dbgu_clk",	.id = 47, },
> +	/*
> +	 * mpddr_clk feeds DDR controller and is enabled by bootloader thus we
> +	 * need to keep it enabled in case there is no Linux consumer for it.
> +	 */
> +	{ .n = "mpddr_clk",	.id = 49,	.f = CLK_IS_CRITICAL },
> +	{ .n = "csi2dc_clk",	.id = 52, },
> +	{ .n = "csi4l_clk",	.id = 53, },
> +	{ .n = "dsi4l_clk",	.id = 54, },
> +	{ .n = "lvdsc_clk",	.id = 56, },
> +	{ .n = "pit64b1_clk",	.id = 58, },
> +	{ .n = "puf_clk",	.id = 59, },
> +	{ .n = "gmactsu_clk",	.id = 67, },
> +};
> +
> +/*
> + * Generic clock description
> + * @n:			clock name
> + * @pp:			PLL parents
> + * @pp_mux_table:	PLL parents mux table
> + * @r:			clock output range
> + * @pp_chg_id:		id in parent array of changeable PLL parent
> + * @pp_count:		PLL parents count
> + * @id:			clock id
> + */
> +static const struct {
> +	const char *n;
> +	const char *pp[8];
> +	const char pp_mux_table[8];
> +	struct clk_range r;
> +	int pp_chg_id;
> +	u8 pp_count;
> +	u8 id;
> +} sam9x7_gck[] = {
> +	{
> +		.n = "flex0_gclk",
> +		.id = 5,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex1_gclk",
> +		.id = 6,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex2_gclk",
> +		.id = 7,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex3_gclk",
> +		.id = 8,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex6_gclk",
> +		.id = 9,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex7_gclk",
> +		.id = 10,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex8_gclk",
> +		.id = 11,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "sdmmc0_gclk",
> +		.id = 12,
> +		.r = { .max = 105000000 },
> +		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 6, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex4_gclk",
> +		.id = 13,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex5_gclk",
> +		.id = 14,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex9_gclk",
> +		.id = 15,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex10_gclk",
> +		.id = 16,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "tcb0_gclk",
> +		.id = 17,
> +		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 6, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "adc_gclk",
> +		.id = 19,
> +		.pp = { "upll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 5, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "lcd_gclk",
> +		.id = 25,
> +		.r = { .max = 75000000 },
> +		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 6, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "sdmmc1_gclk",
> +		.id = 26,
> +		.r = { .max = 105000000 },
> +		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 6, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "mcan0_gclk",
> +		.id = 29,
> +		.r = { .max = 80000000 },
> +		.pp = { "upll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 5, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "mcan1_gclk",
> +		.id = 30,
> +		.r = { .max = 80000000 },
> +		.pp = { "upll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 5, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex11_gclk",
> +		.id = 32,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex12_gclk",
> +		.id = 33,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "i2s_gclk",
> +		.id = 34,
> +		.r = { .max = 100000000 },
> +		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 6, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "qspi_gclk",
> +		.id = 35,
> +		.r = { .max = 20000000 },
> +		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 6, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "pit64b0_gclk",
> +		.id = 37,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "classd_gclk",
> +		.id = 42,
> +		.r = { .max = 100000000 },
> +		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 6, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "tcb1_gclk",
> +		.id = 45,
> +		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 6, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "dbgu_gclk",
> +		.id = 47,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "mipiphy_gclk",
> +		.id = 55,
> +		.r = { .max = 27000000 },
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "pit64b1_gclk",
> +		.id = 58,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "gmac_gclk",
> +		.id = 67,
> +		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 6, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +};
> +
> +static void __init sam9x7_pmc_setup(struct device_node *np)
> +{
> +	struct clk_range range = CLK_RANGE(0, 0);
> +	const char *td_slck_name, *md_slck_name, *mainxtal_name;
> +	struct pmc_data *sam9x7_pmc;
> +	const char *parent_names[9];
> +	void **alloc_mem = NULL;
> +	int alloc_mem_size = 0;
> +	struct clk_hw *main_osc_hw;
> +	struct regmap *regmap;
> +	struct clk_hw *hw;
> +	int i, j;
> +
> +	i = of_property_match_string(np, "clock-names", "td_slck");
> +	if (i < 0)
> +		return;
> +
> +	td_slck_name = of_clk_get_parent_name(np, i);
> +
> +	i = of_property_match_string(np, "clock-names", "md_slck");
> +	if (i < 0)
> +		return;
> +
> +	md_slck_name = of_clk_get_parent_name(np, i);
> +
> +	i = of_property_match_string(np, "clock-names", "main_xtal");
> +	if (i < 0)
> +		return;
> +	mainxtal_name = of_clk_get_parent_name(np, i);
> +
> +	regmap = device_node_to_regmap(np);
> +	if (IS_ERR(regmap))
> +		return;
> +
> +	sam9x7_pmc = pmc_data_allocate(PMC_PLLACK + 1,
> +				       nck(sam9x7_systemck),
> +				       nck(sam9x7_periphck),
> +				       nck(sam9x7_gck), 8);
> +	if (!sam9x7_pmc)
> +		return;
> +
> +	alloc_mem = kmalloc(sizeof(void *) *
> +				(ARRAY_SIZE(sam9x7_gck)),
> +				GFP_KERNEL);
> +	if (!alloc_mem)
> +		goto err_free;
> +
> +	hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
> +					   50000000);
> +	if (IS_ERR(hw))
> +		goto err_free;
> +
> +	hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, 0);
> +	if (IS_ERR(hw))
> +		goto err_free;
> +	main_osc_hw = hw;
> +
> +	parent_names[0] = "main_rc_osc";
> +	parent_names[1] = "main_osc";
> +	hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
> +	if (IS_ERR(hw))
> +		goto err_free;
> +
> +	sam9x7_pmc->chws[PMC_MAIN] = hw;
> +
> +	for (i = 0; i < PLL_ID_MAX; i++) {
> +		for (j = 0; j < 3; j++) {
> +			struct clk_hw *parent_hw;
> +
> +			if (!sam9x7_plls[i][j].n)
> +				continue;
> +
> +			switch (sam9x7_plls[i][j].t) {
> +			case PLL_TYPE_FRAC:
> +				if (!strcmp(sam9x7_plls[i][j].p, "mainck"))
> +					parent_hw = sam9x7_pmc->chws[PMC_MAIN];
> +				else if (!strcmp(sam9x7_plls[i][j].p, "main_osc"))
> +					parent_hw = main_osc_hw;
> +				else
> +					parent_hw = __clk_get_hw(of_clk_get_by_name
> +								 (np, sam9x7_plls[i][j].p));
> +
> +				hw = sam9x60_clk_register_frac_pll(regmap,
> +								   &pmc_pll_lock,
> +								   sam9x7_plls[i][j].n,
> +								   sam9x7_plls[i][j].p,
> +								   parent_hw, i,
> +								   sam9x7_plls[i][j].c,
> +								   sam9x7_plls[i][j].l,
> +								   sam9x7_plls[i][j].f);
> +				break;
> +
> +			case PLL_TYPE_DIV:
> +				hw = sam9x60_clk_register_div_pll(regmap,
> +								  &pmc_pll_lock,
> +								  sam9x7_plls[i][j].n,
> +								  sam9x7_plls[i][j].p, i,
> +								  sam9x7_plls[i][j].c,
> +								  sam9x7_plls[i][j].l,
> +								  sam9x7_plls[i][j].f, 0);
> +				break;
> +
> +			default:
> +				continue;
> +			}
> +
> +			if (IS_ERR(hw))
> +				goto err_free;
> +
> +			if (sam9x7_plls[i][j].eid)
> +				sam9x7_pmc->chws[sam9x7_plls[i][j].eid] = hw;
> +		}
> +	}
> +
> +	parent_names[0] = md_slck_name;
> +	parent_names[1] = "mainck";
> +	parent_names[2] = "plla_divpmcck";
> +	parent_names[3] = "upll_divpmcck";
> +	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
> +					   parent_names, &sam9x7_master_layout,
> +					   &mck_characteristics, &mck_lock);
> +	if (IS_ERR(hw))
> +		goto err_free;
> +
> +	hw = at91_clk_register_master_div(regmap, "masterck_div",
> +					  "masterck_pres", &sam9x7_master_layout,
> +					  &mck_characteristics, &mck_lock,
> +					  CLK_SET_RATE_GATE, 0);
> +	if (IS_ERR(hw))
> +		goto err_free;
> +
> +	sam9x7_pmc->chws[PMC_MCK] = hw;
> +
> +	parent_names[0] = "plla_divpmcck";
> +	parent_names[1] = "upll_divpmcck";
> +	parent_names[2] = "main_osc";
> +	hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3);
> +	if (IS_ERR(hw))
> +		goto err_free;
> +
> +	parent_names[0] = md_slck_name;
> +	parent_names[1] = td_slck_name;
> +	parent_names[2] = "mainck";
> +	parent_names[3] = "masterck_div";
> +	parent_names[4] = "plla_divpmcck";
> +	parent_names[5] = "upll_divpmcck";
> +	parent_names[6] = "audiopll_divpmcck";
> +	for (i = 0; i < 2; i++) {
> +		char name[6];
> +
> +		snprintf(name, sizeof(name), "prog%d", i);
> +
> +		hw = at91_clk_register_programmable(regmap, name,
> +						    parent_names, 7, i,
> +						    &sam9x7_programmable_layout,
> +						    NULL);
> +		if (IS_ERR(hw))
> +			goto err_free;
> +
> +		sam9x7_pmc->pchws[i] = hw;
> +	}
> +
> +	for (i = 0; i < ARRAY_SIZE(sam9x7_systemck); i++) {
> +		hw = at91_clk_register_system(regmap, sam9x7_systemck[i].n,
> +					      sam9x7_systemck[i].p,
> +					      sam9x7_systemck[i].id,
> +					      sam9x7_systemck[i].flags);
> +		if (IS_ERR(hw))
> +			goto err_free;
> +
> +		sam9x7_pmc->shws[sam9x7_systemck[i].id] = hw;
> +	}
> +
> +	for (i = 0; i < ARRAY_SIZE(sam9x7_periphck); i++) {
> +		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
> +							 &sam9x7_pcr_layout,
> +							 sam9x7_periphck[i].n,
> +							 "masterck_div",
> +							 sam9x7_periphck[i].id,
> +							 &range, INT_MIN,
> +							 sam9x7_periphck[i].f);
> +		if (IS_ERR(hw))
> +			goto err_free;
> +
> +		sam9x7_pmc->phws[sam9x7_periphck[i].id] = hw;
> +	}
> +
> +	parent_names[0] = md_slck_name;
> +	parent_names[1] = td_slck_name;
> +	parent_names[2] = "mainck";
> +	parent_names[3] = "masterck_div";
> +	for (i = 0; i < ARRAY_SIZE(sam9x7_gck); i++) {
> +		u8 num_parents = 4 + sam9x7_gck[i].pp_count;
> +		u32 *mux_table;
> +
> +		mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
> +					  GFP_KERNEL);
> +		if (!mux_table)
> +			goto err_free;
> +
> +		SAM9X7_INIT_TABLE(mux_table, 4);
> +		SAM9X7_FILL_TABLE(&mux_table[4], sam9x7_gck[i].pp_mux_table,
> +				  sam9x7_gck[i].pp_count);
> +		SAM9X7_FILL_TABLE(&parent_names[4], sam9x7_gck[i].pp,
> +				  sam9x7_gck[i].pp_count);
> +
> +		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
> +						 &sam9x7_pcr_layout,
> +						 sam9x7_gck[i].n,
> +						 parent_names, mux_table,
> +						 num_parents,
> +						 sam9x7_gck[i].id,
> +						 &sam9x7_gck[i].r,
> +						 sam9x7_gck[i].pp_chg_id);
> +		if (IS_ERR(hw))
> +			goto err_free;
> +
> +		sam9x7_pmc->ghws[sam9x7_gck[i].id] = hw;
> +		alloc_mem[alloc_mem_size++] = mux_table;
> +	}
> +
> +	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x7_pmc);
> +
> +	return;
> +
> +err_free:
> +	if (alloc_mem) {
> +		for (i = 0; i < alloc_mem_size; i++)
> +			kfree(alloc_mem[i]);
> +		kfree(alloc_mem);
> +	}
> +	kfree(sam9x7_pmc);
> +}
> +
> +/* Some clks are used for a clocksource */
> +CLK_OF_DECLARE(sam9x7_pmc, "microchip,sam9x7-pmc", sam9x7_pmc_setup);

[PATCH 15/21] dt-bindings: irqchip/atmel-aic5: Add support for sam9x7 aic

[Varshini Rajendran]

Document the support added for the Advanced interrupt controller(AIC)
chip in the sam9x7 soc family

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 .../devicetree/bindings/interrupt-controller/atmel,aic.txt      | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
index 7079d44bf3ba..2c267a66a3ea 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
@@ -4,7 +4,7 @@ Required properties:
 - compatible: Should be:
     - "atmel,<chip>-aic" where  <chip> can be "at91rm9200", "sama5d2",
       "sama5d3" or "sama5d4"
-    - "microchip,<chip>-aic" where <chip> can be "sam9x60"
+    - "microchip,<chip>-aic" where <chip> can be "sam9x60", "sam9x7"
 
 - interrupt-controller: Identifies the node as an interrupt controller.
 - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
-- 
2.25.1

Re: [PATCH 15/21] dt-bindings: irqchip/atmel-aic5: Add support for sam9x7 aic

[Conor Dooley]

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Hey Varshini,

On Sun, Jun 04, 2023 at 01:32:37AM +0530, Varshini Rajendran wrote:
> Document the support added for the Advanced interrupt controller(AIC)
> chip in the sam9x7 soc family

Please do not add new family based compatibles, but rather use per-soc
compatibles instead.

Cheers,
Conor.

> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  .../devicetree/bindings/interrupt-controller/atmel,aic.txt      | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
> index 7079d44bf3ba..2c267a66a3ea 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
> @@ -4,7 +4,7 @@ Required properties:
>  - compatible: Should be:
>      - "atmel,<chip>-aic" where  <chip> can be "at91rm9200", "sama5d2",
>        "sama5d3" or "sama5d4"
> -    - "microchip,<chip>-aic" where <chip> can be "sam9x60"
> +    - "microchip,<chip>-aic" where <chip> can be "sam9x60", "sam9x7"
>  
>  - interrupt-controller: Identifies the node as an interrupt controller.
>  - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
> -- 
> 2.25.1
>

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Re: [PATCH 15/21] dt-bindings: irqchip/atmel-aic5: Add support for sam9x7 aic

[Conor Dooley]

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On Sat, Jun 03, 2023 at 10:19:50PM +0100, Conor Dooley wrote:
> Hey Varshini,
> 
> On Sun, Jun 04, 2023 at 01:32:37AM +0530, Varshini Rajendran wrote:
> > Document the support added for the Advanced interrupt controller(AIC)
> > chip in the sam9x7 soc family
> 
> Please do not add new family based compatibles, but rather use per-soc
> compatibles instead.

These things leave me penally confused. Afaiu, sam9x60 is a particular
SoC. sam9x7 is actually a family, containing sam9x70, sam9x72 and
sam9x75. It would appear to me that each should have its own compatible,
no?

> 
> Cheers,
> Conor.
> 
> > 
> > Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> > ---
> >  .../devicetree/bindings/interrupt-controller/atmel,aic.txt      | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
> > index 7079d44bf3ba..2c267a66a3ea 100644
> > --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
> > @@ -4,7 +4,7 @@ Required properties:
> >  - compatible: Should be:
> >      - "atmel,<chip>-aic" where  <chip> can be "at91rm9200", "sama5d2",
> >        "sama5d3" or "sama5d4"
> > -    - "microchip,<chip>-aic" where <chip> can be "sam9x60"
> > +    - "microchip,<chip>-aic" where <chip> can be "sam9x60", "sam9x7"
> >  
> >  - interrupt-controller: Identifies the node as an interrupt controller.
> >  - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
> > -- 
> > 2.25.1
> >



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Re: [PATCH 15/21] dt-bindings: irqchip/atmel-aic5: Add support for sam9x7 aic

[Arnd Bergmann]

On Sat, Jun 3, 2023, at 23:23, Conor Dooley wrote:
> On Sat, Jun 03, 2023 at 10:19:50PM +0100, Conor Dooley wrote:
>> Hey Varshini,
>> 
>> On Sun, Jun 04, 2023 at 01:32:37AM +0530, Varshini Rajendran wrote:
>> > Document the support added for the Advanced interrupt controller(AIC)
>> > chip in the sam9x7 soc family
>> 
>> Please do not add new family based compatibles, but rather use per-soc
>> compatibles instead.
>
> These things leave me penally confused. Afaiu, sam9x60 is a particular
> SoC. sam9x7 is actually a family, containing sam9x70, sam9x72 and
> sam9x75. It would appear to me that each should have its own compatible,
> no?

I think the usual way this works is that the sam9x7 refers to the
SoC design as in what is actually part of the chip, whereas the 70,
72 and 75 models are variants that have a certain subset of the
features enabled.

If that is the case here, then referring to the on-chip parts by
the sam9x7 name makes sense, and this is similar to what we do
on TI AM-series chips.

There is a remaining risk that a there would be a future
sam9x71/73/74/76/... product based on a new chip that uses
incompatible devices, but at that point we can still use the
more specific model number to identify those without being
ambiguous. The same thing can of course happen when a SoC
vendor reuses a specific name of a prior product with an update
chip that has software visible changes.

I'd just leave this up to Varshini and the other at91 maintainers
here, provided they understand the exact risks.

It's different for the parts that are listed as just sam9x60
compatible in the DT, I think those clearly need to have sam9x7
in the compatible list, but could have the sam9x60 identifier
as a fallback if the hardware is compatible.

     Arnd

Re: [PATCH 15/21] dt-bindings: irqchip/atmel-aic5: Add support for sam9x7 aic

[Conor Dooley]

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On Sun, Jun 04, 2023 at 11:49:48AM +0200, Arnd Bergmann wrote:
> On Sat, Jun 3, 2023, at 23:23, Conor Dooley wrote:
> > On Sat, Jun 03, 2023 at 10:19:50PM +0100, Conor Dooley wrote:
> >> Hey Varshini,
> >> 
> >> On Sun, Jun 04, 2023 at 01:32:37AM +0530, Varshini Rajendran wrote:
> >> > Document the support added for the Advanced interrupt controller(AIC)
> >> > chip in the sam9x7 soc family
> >> 
> >> Please do not add new family based compatibles, but rather use per-soc
> >> compatibles instead.
> >
> > These things leave me penally confused. Afaiu, sam9x60 is a particular

s/penally/perennially/

> > SoC. sam9x7 is actually a family, containing sam9x70, sam9x72 and
> > sam9x75. It would appear to me that each should have its own compatible,
> > no?
> 
> I think the usual way this works is that the sam9x7 refers to the
> SoC design as in what is actually part of the chip, whereas the 70,
> 72 and 75 models are variants that have a certain subset of the
> features enabled.
> 
> If that is the case here, then referring to the on-chip parts by
> the sam9x7 name makes sense, and this is similar to what we do
> on TI AM-series chips.

If it is the case that what differentiates them is having bits chopped
off, and there's no implementation differences that seems fair.

> There is a remaining risk that a there would be a future
> sam9x71/73/74/76/... product based on a new chip that uses
> incompatible devices, but at that point we can still use the
> more specific model number to identify those without being
> ambiguous. The same thing can of course happen when a SoC
> vendor reuses a specific name of a prior product with an update
> chip that has software visible changes.
> 
> I'd just leave this up to Varshini and the other at91 maintainers
> here, provided they understand the exact risks.

Ye, seems fair to me. Nicolas/Claudiu etc, is there a convention to use
the "0" model as the compatible (like the 9x60 did) or have "random"
things been done so far?

> It's different for the parts that are listed as just sam9x60
> compatible in the DT, I think those clearly need to have sam9x7
> in the compatible list, but could have the sam9x60 identifier
> as a fallback if the hardware is compatible.

Aye.

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Re: [PATCH 15/21] dt-bindings: irqchip/atmel-aic5: Add support for sam9x7 aic

[Nicolas Ferre]

Arnd, Conor,

On 04/06/2023 at 23:08, Conor Dooley wrote:
> On Sun, Jun 04, 2023 at 11:49:48AM +0200, Arnd Bergmann wrote:
>> On Sat, Jun 3, 2023, at 23:23, Conor Dooley wrote:
>>> On Sat, Jun 03, 2023 at 10:19:50PM +0100, Conor Dooley wrote:
>>>> Hey Varshini,
>>>>
>>>> On Sun, Jun 04, 2023 at 01:32:37AM +0530, Varshini Rajendran wrote:
>>>>> Document the support added for the Advanced interrupt controller(AIC)
>>>>> chip in the sam9x7 soc family
>>>> Please do not add new family based compatibles, but rather use per-soc
>>>> compatibles instead.
>>> These things leave me penally confused. Afaiu, sam9x60 is a particular
> s/penally/perennially/
> 
>>> SoC. sam9x7 is actually a family, containing sam9x70, sam9x72 and
>>> sam9x75. It would appear to me that each should have its own compatible,
>>> no?
>> I think the usual way this works is that the sam9x7 refers to the
>> SoC design as in what is actually part of the chip, whereas the 70,
>> 72 and 75 models are variants that have a certain subset of the
>> features enabled.

Yes, That's the case.
>> If that is the case here, then referring to the on-chip parts by
>> the sam9x7 name makes sense, and this is similar to what we do
>> on TI AM-series chips.

This is what we did for most of our SoCs families, indeed.

> If it is the case that what differentiates them is having bits chopped
> off, and there's no implementation differences that seems fair.

Ok, thanks.

>> There is a remaining risk that a there would be a future
>> sam9x71/73/74/76/... product based on a new chip that uses
>> incompatible devices, but at that point we can still use the
>> more specific model number to identify those without being
>> ambiguous. 

This is exactly what we did for sama5d29 which is not the same silicon 
vs. the other members of the sama5d2 family. We used the more specify 
sama5d29 sub-string for describing the changing parts (CAN-FD and Ethernet).

>> The same thing can of course happen when a SoC
>> vendor reuses a specific name of a prior product with an update
>> chip that has software visible changes.
>>
>> I'd just leave this up to Varshini and the other at91 maintainers
>> here, provided they understand the exact risks.

Yep, I understand the risk and will try to review the compatibility 
strings that would need more precise description (maybe PMC or AIC).

> Ye, seems fair to me. Nicolas/Claudiu etc, is there a convention to use
> the "0" model as the compatible (like the 9x60 did) or have "random"
> things been done so far?

sam9x60 was a single SoC, not a member of a "family", so there was no 
meaning of the "0" here. Moreover, the "0" ones are usually not the 
subset, if it even exists.
So far, we used the silicon string to define the compatibility string, 
adding a more precise string for hardware of family members that needed 
it (as mentioned above for sama5d29).

>> It's different for the parts that are listed as just sam9x60
>> compatible in the DT, I think those clearly need to have sam9x7
>> in the compatible list, but could have the sam9x60 identifier
>> as a fallback if the hardware is compatible.
> Aye.

Yep, agreed.

Thanks for your help. Best regards,
   Nicolas

-- 
Nicolas Ferre

Re: [PATCH 15/21] dt-bindings: irqchip/atmel-aic5: Add support for sam9x7 aic

[Rob Herring]

On Mon, Jun 05, 2023 at 02:37:16PM +0200, Nicolas Ferre wrote:
> Arnd, Conor,
> 
> On 04/06/2023 at 23:08, Conor Dooley wrote:
> > On Sun, Jun 04, 2023 at 11:49:48AM +0200, Arnd Bergmann wrote:
> > > On Sat, Jun 3, 2023, at 23:23, Conor Dooley wrote:
> > > > On Sat, Jun 03, 2023 at 10:19:50PM +0100, Conor Dooley wrote:
> > > > > Hey Varshini,
> > > > > 
> > > > > On Sun, Jun 04, 2023 at 01:32:37AM +0530, Varshini Rajendran wrote:
> > > > > > Document the support added for the Advanced interrupt controller(AIC)
> > > > > > chip in the sam9x7 soc family
> > > > > Please do not add new family based compatibles, but rather use per-soc
> > > > > compatibles instead.
> > > > These things leave me penally confused. Afaiu, sam9x60 is a particular
> > s/penally/perennially/
> > 
> > > > SoC. sam9x7 is actually a family, containing sam9x70, sam9x72 and
> > > > sam9x75. It would appear to me that each should have its own compatible,
> > > > no?
> > > I think the usual way this works is that the sam9x7 refers to the
> > > SoC design as in what is actually part of the chip, whereas the 70,
> > > 72 and 75 models are variants that have a certain subset of the
> > > features enabled.
> 
> Yes, That's the case.
> > > If that is the case here, then referring to the on-chip parts by
> > > the sam9x7 name makes sense, and this is similar to what we do
> > > on TI AM-series chips.
> 
> This is what we did for most of our SoCs families, indeed.
> 
> > If it is the case that what differentiates them is having bits chopped
> > off, and there's no implementation differences that seems fair.
> 
> Ok, thanks.
> 
> > > There is a remaining risk that a there would be a future
> > > sam9x71/73/74/76/... product based on a new chip that uses
> > > incompatible devices, but at that point we can still use the
> > > more specific model number to identify those without being
> > > ambiguous.
> 
> This is exactly what we did for sama5d29 which is not the same silicon vs.
> the other members of the sama5d2 family. We used the more specify sama5d29
> sub-string for describing the changing parts (CAN-FD and Ethernet).
> 
> > > The same thing can of course happen when a SoC
> > > vendor reuses a specific name of a prior product with an update
> > > chip that has software visible changes.
> > > 
> > > I'd just leave this up to Varshini and the other at91 maintainers
> > > here, provided they understand the exact risks.
> 
> Yep, I understand the risk and will try to review the compatibility strings
> that would need more precise description (maybe PMC or AIC).
> 
> > Ye, seems fair to me. Nicolas/Claudiu etc, is there a convention to use
> > the "0" model as the compatible (like the 9x60 did) or have "random"
> > things been done so far?
> 
> sam9x60 was a single SoC, not a member of a "family", so there was no
> meaning of the "0" here. Moreover, the "0" ones are usually not the subset,
> if it even exists.
> So far, we used the silicon string to define the compatibility string,
> adding a more precise string for hardware of family members that needed it
> (as mentioned above for sama5d29).
> 
> > > It's different for the parts that are listed as just sam9x60
> > > compatible in the DT, I think those clearly need to have sam9x7
> > > in the compatible list, but could have the sam9x60 identifier
> > > as a fallback if the hardware is compatible.
> > Aye.
> 
> Yep, agreed.

Can we convert this binding to schema so all this is perfectly clear 
what's valid or not.

Rob

[PATCH 16/21] irqchip/atmel-aic5: Add support for sam9x7 aic

[Varshini Rajendran]

From: Hari Prasath <Hari.PrasathGE@microchip.com>

Add support for the Advanced interrupt controller(AIC) chip in the sam9x7.

Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/irqchip/irq-atmel-aic5.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c
index 145535bd7560..bab11900f3ef 100644
--- a/drivers/irqchip/irq-atmel-aic5.c
+++ b/drivers/irqchip/irq-atmel-aic5.c
@@ -320,6 +320,7 @@ static const struct of_device_id aic5_irq_fixups[] __initconst = {
 	{ .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup },
 	{ .compatible = "atmel,sama5d4", .data = sama5d3_aic_irq_fixup },
 	{ .compatible = "microchip,sam9x60", .data = sam9x60_aic_irq_fixup },
+	{ .compatible = "microchip,sam9x7", .data = sam9x60_aic_irq_fixup },
 	{ /* sentinel */ },
 };
 
@@ -406,3 +407,12 @@ static int __init sam9x60_aic5_of_init(struct device_node *node,
 	return aic5_of_init(node, parent, NR_SAM9X60_IRQS);
 }
 IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_init);
+
+#define NR_SAM9X7_IRQS		70
+
+static int __init sam9x7_aic5_of_init(struct device_node *node,
+				      struct device_node *parent)
+{
+	return aic5_of_init(node, parent, NR_SAM9X7_IRQS);
+}
+IRQCHIP_DECLARE(sam9x7_aic5, "microchip,sam9x7-aic", sam9x7_aic5_of_init);
-- 
2.25.1

[PATCH 17/21] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7

[Varshini Rajendran]

Use sam9x7 pmc's compatible to lookup for in the SHDWC driver

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/power/reset/at91-sama5d2_shdwc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c
index d8ecffe72f16..d0f29b99f25e 100644
--- a/drivers/power/reset/at91-sama5d2_shdwc.c
+++ b/drivers/power/reset/at91-sama5d2_shdwc.c
@@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] = {
 	{ .compatible = "atmel,sama5d2-pmc" },
 	{ .compatible = "microchip,sam9x60-pmc" },
 	{ .compatible = "microchip,sama7g5-pmc" },
+	{ .compatible = "microchip,sam9x7-pmc" },
 	{ /* Sentinel. */ }
 };
 
-- 
2.25.1

Re: [PATCH 17/21] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7

[Krzysztof Kozlowski]

On 03/06/2023 22:02, Varshini Rajendran wrote:
> Use sam9x7 pmc's compatible to lookup for in the SHDWC driver
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  drivers/power/reset/at91-sama5d2_shdwc.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c
> index d8ecffe72f16..d0f29b99f25e 100644
> --- a/drivers/power/reset/at91-sama5d2_shdwc.c
> +++ b/drivers/power/reset/at91-sama5d2_shdwc.c
> @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] = {
>  	{ .compatible = "atmel,sama5d2-pmc" },
>  	{ .compatible = "microchip,sam9x60-pmc" },
>  	{ .compatible = "microchip,sama7g5-pmc" },
> +	{ .compatible = "microchip,sam9x7-pmc" },

Why do you need new entry if these are compatible?

Best regards,
Krzysztof

Re: [PATCH 17/21] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7

[Nicolas Ferre]

On 05/06/2023 at 08:43, Krzysztof Kozlowski wrote:
> On 03/06/2023 22:02, Varshini Rajendran wrote:
>> Use sam9x7 pmc's compatible to lookup for in the SHDWC driver
>>
>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>> ---
>>   drivers/power/reset/at91-sama5d2_shdwc.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c
>> index d8ecffe72f16..d0f29b99f25e 100644
>> --- a/drivers/power/reset/at91-sama5d2_shdwc.c
>> +++ b/drivers/power/reset/at91-sama5d2_shdwc.c
>> @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] = {
>>        { .compatible = "atmel,sama5d2-pmc" },
>>        { .compatible = "microchip,sam9x60-pmc" },
>>        { .compatible = "microchip,sama7g5-pmc" },
>> +     { .compatible = "microchip,sam9x7-pmc" },
> 
> Why do you need new entry if these are compatible?

Yes, PMC is very specific to a SoC silicon. As we must look for it in 
the shutdown controller, I think we need a new entry here.

Best regards,
   Nicolas

-- 
Nicolas Ferre

Re: [PATCH 17/21] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7

[Conor Dooley]

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Hey,

On Mon, Jun 05, 2023 at 03:04:34PM +0200, Nicolas Ferre wrote:
> On 05/06/2023 at 08:43, Krzysztof Kozlowski wrote:
> > On 03/06/2023 22:02, Varshini Rajendran wrote:
> > > Use sam9x7 pmc's compatible to lookup for in the SHDWC driver
> > > 
> > > Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> > > ---
> > >   drivers/power/reset/at91-sama5d2_shdwc.c | 1 +
> > >   1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c
> > > index d8ecffe72f16..d0f29b99f25e 100644
> > > --- a/drivers/power/reset/at91-sama5d2_shdwc.c
> > > +++ b/drivers/power/reset/at91-sama5d2_shdwc.c
> > > @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] = {
> > >        { .compatible = "atmel,sama5d2-pmc" },
> > >        { .compatible = "microchip,sam9x60-pmc" },
> > >        { .compatible = "microchip,sama7g5-pmc" },
> > > +     { .compatible = "microchip,sam9x7-pmc" },
> > 
> > Why do you need new entry if these are compatible?
> 
> Yes, PMC is very specific to a SoC silicon. As we must look for it in the
> shutdown controller, I think we need a new entry here.

Copy-pasting this for a wee bit of context as I have two questions.

| static const struct of_device_id at91_shdwc_of_match[] = {
| 	{
| 		.compatible = "atmel,sama5d2-shdwc",
| 		.data = &sama5d2_reg_config,
| 	},
| 	{
| 		.compatible = "microchip,sam9x60-shdwc",
| 		.data = &sam9x60_reg_config,
| 	},
| 	{
| 		.compatible = "microchip,sama7g5-shdwc",
| 		.data = &sama7g5_reg_config,
| 	}, {
| 		/*sentinel*/
| 	}
| };
| MODULE_DEVICE_TABLE(of, at91_shdwc_of_match);
| 
| static const struct of_device_id at91_pmc_ids[] = {
| 	{ .compatible = "atmel,sama5d2-pmc" },
| 	{ .compatible = "microchip,sam9x60-pmc" },
| 	{ .compatible = "microchip,sama7g5-pmc" },
| 	{ .compatible = "microchip,sam9x7-pmc" },
| 	{ /* Sentinel. */ }
| };

If there's no changes made to the code, other than adding an entry to
the list of pmc compatibles, then either this has the same as an
existing SoC, or there is a bug in the patch, since the behaviour of
the driver will not have changed.

Secondly, this patch only updates the at91_pmc_ids and the dts patch
contains:
| shutdown_controller: shdwc@fffffe10 {
| 	compatible = "microchip,sam9x60-shdwc";
| 	reg = <0xfffffe10 0x10>;
| 	clocks = <&clk32k 0>;
| 	#address-cells = <1>;
| 	#size-cells = <0>;
| 	atmel,wakeup-rtc-timer;
| 	atmel,wakeup-rtt-timer;
| 	status = "disabled";
| };

...which would mean that the there's nothing different between the
programming models for the sam9x60 and sam9x7. If that's the case, the
dt-binding & dts should list the sam9x60 as a fallback for the sam9x7 &
there is no change required to the driver. If it's not the case, then
there's a bug in this patch and the dts one :)

In general, if things are the same as previous products, there's no need
to change the drivers at all & just add fallback compatibles to the
bindings and dts. IFF some difference pops up in the future, then the
sam9x7 compatible will already exist in the dts, and can then be added
to the driver.

Cheers,
Conor.


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Re: [PATCH 17/21] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7

[Varshini.Rajendran]

On 05/06/23 6:56 pm, Conor Dooley wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> Hey,
> 
> On Mon, Jun 05, 2023 at 03:04:34PM +0200, Nicolas Ferre wrote:
>> On 05/06/2023 at 08:43, Krzysztof Kozlowski wrote:
>>> On 03/06/2023 22:02, Varshini Rajendran wrote:
>>>> Use sam9x7 pmc's compatible to lookup for in the SHDWC driver
>>>>
>>>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>>>> ---
>>>>   drivers/power/reset/at91-sama5d2_shdwc.c | 1 +
>>>>   1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c
>>>> index d8ecffe72f16..d0f29b99f25e 100644
>>>> --- a/drivers/power/reset/at91-sama5d2_shdwc.c
>>>> +++ b/drivers/power/reset/at91-sama5d2_shdwc.c
>>>> @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] = {
>>>>        { .compatible = "atmel,sama5d2-pmc" },
>>>>        { .compatible = "microchip,sam9x60-pmc" },
>>>>        { .compatible = "microchip,sama7g5-pmc" },
>>>> +     { .compatible = "microchip,sam9x7-pmc" },
>>>
>>> Why do you need new entry if these are compatible?
>>
>> Yes, PMC is very specific to a SoC silicon. As we must look for it in the
>> shutdown controller, I think we need a new entry here.
> 
> Copy-pasting this for a wee bit of context as I have two questions.
> 
> | static const struct of_device_id at91_shdwc_of_match[] = {
> | 	{
> | 		.compatible = "atmel,sama5d2-shdwc",
> | 		.data = &sama5d2_reg_config,
> | 	},
> | 	{
> | 		.compatible = "microchip,sam9x60-shdwc",
> | 		.data = &sam9x60_reg_config,
> | 	},
> | 	{
> | 		.compatible = "microchip,sama7g5-shdwc",
> | 		.data = &sama7g5_reg_config,
> | 	}, {
> | 		/*sentinel*/
> | 	}
> | };
> | MODULE_DEVICE_TABLE(of, at91_shdwc_of_match);
> | 
> | static const struct of_device_id at91_pmc_ids[] = {
> | 	{ .compatible = "atmel,sama5d2-pmc" },
> | 	{ .compatible = "microchip,sam9x60-pmc" },
> | 	{ .compatible = "microchip,sama7g5-pmc" },
> | 	{ .compatible = "microchip,sam9x7-pmc" },
> | 	{ /* Sentinel. */ }
> | };
> 
> If there's no changes made to the code, other than adding an entry to
> the list of pmc compatibles, then either this has the same as an
> existing SoC, or there is a bug in the patch, since the behaviour of
> the driver will not have changed.
> 
> Secondly, this patch only updates the at91_pmc_ids and the dts patch
> contains:
> | shutdown_controller: shdwc@fffffe10 {
> | 	compatible = "microchip,sam9x60-shdwc";
> | 	reg = <0xfffffe10 0x10>;
> | 	clocks = <&clk32k 0>;
> | 	#address-cells = <1>;
> | 	#size-cells = <0>;
> | 	atmel,wakeup-rtc-timer;
> | 	atmel,wakeup-rtt-timer;
> | 	status = "disabled";
> | };
> 
> ...which would mean that the there's nothing different between the
> programming models for the sam9x60 and sam9x7. If that's the case, the
> dt-binding & dts should list the sam9x60 as a fallback for the sam9x7 &
> there is no change required to the driver. If it's not the case, then
> there's a bug in this patch and the dts one 😄
> 
> In general, if things are the same as previous products, there's no need
> to change the drivers at all & just add fallback compatibles to the
> bindings and dts. IFF some difference pops up in the future, then the
> sam9x7 compatible will already exist in the dts, and can then be added
> to the driver.

Yes. I totally agree with you. In this patch I have not added a 
compatible for the shutdown controller for sam9x7. I have added the 
compatible of the pmc used in sam9x7 in the list of compatibles to use 
the right pmc driver in order to control the clk disable functions for 
the right pmc. The shutdown programming is no different, so no new 
compatible for sam9x7 (like microchip,sam9x7-shdwc). But the PMC is 
totally different than the other older SoCs, hence I have added the new 
compatible microchip,sam9x7-pmc in the list as it is defined in the 
drivers/clk/at91/sam9x7.c driver. Hope this is clear.

> 
> Cheers,
> Conor.
> 

-- 
Thanks and Regards,
Varshini Rajendran.

Re: [PATCH 17/21] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7

[Krzysztof Kozlowski]

On 05/06/2023 15:04, Nicolas Ferre wrote:
> On 05/06/2023 at 08:43, Krzysztof Kozlowski wrote:
>> On 03/06/2023 22:02, Varshini Rajendran wrote:
>>> Use sam9x7 pmc's compatible to lookup for in the SHDWC driver
>>>
>>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>>> ---
>>>   drivers/power/reset/at91-sama5d2_shdwc.c | 1 +
>>>   1 file changed, 1 insertion(+)
>>>
>>> diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c
>>> index d8ecffe72f16..d0f29b99f25e 100644
>>> --- a/drivers/power/reset/at91-sama5d2_shdwc.c
>>> +++ b/drivers/power/reset/at91-sama5d2_shdwc.c
>>> @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] = {
>>>        { .compatible = "atmel,sama5d2-pmc" },
>>>        { .compatible = "microchip,sam9x60-pmc" },
>>>        { .compatible = "microchip,sama7g5-pmc" },
>>> +     { .compatible = "microchip,sam9x7-pmc" },
>>
>> Why do you need new entry if these are compatible?
> 
> Yes, PMC is very specific to a SoC silicon. As we must look for it in 
> the shutdown controller, I think we need a new entry here.

??? How does it answer to my question at all? What is exactly specific
which warrants new entry?


Best regards,
Krzysztof

[PATCH 18/21] power: reset: at91-reset: add reset support for sam9x7 soc

[Varshini Rajendran]

Add power reset support for SAM9X7 SoC

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/power/reset/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index 8c87eeda0fec..6c4ad81a0059 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -26,7 +26,7 @@ config POWER_RESET_AT91_POWEROFF
 config POWER_RESET_AT91_RESET
 	tristate "Atmel AT91 reset driver"
 	depends on ARCH_AT91
-	default SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
+	default SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5
 	help
 	  This driver supports restart for Atmel AT91SAM9 and SAMA5
 	  SoCs
-- 
2.25.1

[PATCH 19/21] power: reset: at91-reset: add sdhwc support for sam9x7 soc

[Varshini Rajendran]

Add shutdown controller support for SAM9X7 SoC

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/power/reset/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index 6c4ad81a0059..59459f5abbed 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -34,7 +34,7 @@ config POWER_RESET_AT91_RESET
 config POWER_RESET_AT91_SAMA5D2_SHDWC
 	tristate "Atmel AT91 SAMA5D2-Compatible shutdown controller driver"
 	depends on ARCH_AT91
-	default SOC_SAM9X60 || SOC_SAMA5
+	default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5
 	help
 	  This driver supports the alternate shutdown controller for some Atmel
 	  SAMA5 SoCs. It is present for example on SAMA5D2 SoC.
-- 
2.25.1

[PATCH 20/21] dt-bindings: net: cdns,macb: add documentation for sam9x7 ethernet interface

[Varshini Rajendran]

Add documentation for sam9x7 ethernet interface

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 Documentation/devicetree/bindings/net/cdns,macb.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml
index bef5e0f895be..e4f9e9b353e5 100644
--- a/Documentation/devicetree/bindings/net/cdns,macb.yaml
+++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml
@@ -54,6 +54,7 @@ properties:
           - cdns,np4-macb             # NP4 SoC devices
           - microchip,sama7g5-emac    # Microchip SAMA7G5 ethernet interface
           - microchip,sama7g5-gem     # Microchip SAMA7G5 gigabit ethernet interface
+          - microchip,sam9x7-gem      # Microchip SAM9X7 gigabit ethernet interface
           - sifive,fu540-c000-gem     # SiFive FU540-C000 SoC
           - cdns,emac                 # Generic
           - cdns,gem                  # Generic
-- 
2.25.1

Re: [PATCH 20/21] dt-bindings: net: cdns,macb: add documentation for sam9x7 ethernet interface

[Krzysztof Kozlowski]

On 03/06/2023 22:02, Varshini Rajendran wrote:
> Add documentation for sam9x7 ethernet interface
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  Documentation/devicetree/bindings/net/cdns,macb.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml
> index bef5e0f895be..e4f9e9b353e5 100644
> --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml
> +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml
> @@ -54,6 +54,7 @@ properties:
>            - cdns,np4-macb             # NP4 SoC devices
>            - microchip,sama7g5-emac    # Microchip SAMA7G5 ethernet interface
>            - microchip,sama7g5-gem     # Microchip SAMA7G5 gigabit ethernet interface
> +          - microchip,sam9x7-gem      # Microchip SAM9X7 gigabit ethernet interface

No wildcards in compatibles.

Best regards,
Krzysztof

Re: [PATCH 20/21] dt-bindings: net: cdns,macb: add documentation for sam9x7 ethernet interface

[Rob Herring]

On Sun, 04 Jun 2023 01:32:42 +0530, Varshini Rajendran wrote:
> Add documentation for sam9x7 ethernet interface
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  Documentation/devicetree/bindings/net/cdns,macb.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 21/21] net: macb: add support for gmac to sam9x7

[Varshini Rajendran]

From: Nicolas Ferre <nicolas.ferre@microchip.com>

Add support for GMAC in sam9x7 SoC family

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
---
 drivers/net/ethernet/cadence/macb_main.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index 29a1199dad14..609c8e9305ba 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -4913,6 +4913,7 @@ static const struct of_device_id macb_dt_ids[] = {
 	{ .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
 	{ .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
 	{ .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
+	{ .compatible = "microchip,sam9x7-gem", .data = &sama7g5_gem_config },
 	{ .compatible = "xlnx,zynqmp-gem", .data = &zynqmp_config},
 	{ .compatible = "xlnx,zynq-gem", .data = &zynq_config },
 	{ .compatible = "xlnx,versal-gem", .data = &versal_config},
-- 
2.25.1

Re: [PATCH 21/21] net: macb: add support for gmac to sam9x7

[Krzysztof Kozlowski]

On 03/06/2023 22:02, Varshini Rajendran wrote:
> From: Nicolas Ferre <nicolas.ferre@microchip.com>
> 
> Add support for GMAC in sam9x7 SoC family
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> ---
>  drivers/net/ethernet/cadence/macb_main.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
> index 29a1199dad14..609c8e9305ba 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -4913,6 +4913,7 @@ static const struct of_device_id macb_dt_ids[] = {
>  	{ .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
>  	{ .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
>  	{ .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
> +	{ .compatible = "microchip,sam9x7-gem", .data = &sama7g5_gem_config },

These are compatible, aren't they? Why do you need new entry?

Best regards,
Krzysztof

Re: [PATCH 21/21] net: macb: add support for gmac to sam9x7

[Nicolas Ferre]

On 05/06/2023 at 08:42, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 03/06/2023 22:02, Varshini Rajendran wrote:
>> From: Nicolas Ferre <nicolas.ferre@microchip.com>
>>
>> Add support for GMAC in sam9x7 SoC family
>>
>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
>> ---
>>   drivers/net/ethernet/cadence/macb_main.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
>> index 29a1199dad14..609c8e9305ba 100644
>> --- a/drivers/net/ethernet/cadence/macb_main.c
>> +++ b/drivers/net/ethernet/cadence/macb_main.c
>> @@ -4913,6 +4913,7 @@ static const struct of_device_id macb_dt_ids[] = {
>>        { .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
>>        { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
>>        { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
>> +     { .compatible = "microchip,sam9x7-gem", .data = &sama7g5_gem_config },
> 
> These are compatible, aren't they? Why do you need new entry?

The hardware itself is different, even if the new features are not 
supported yet in the macb driver.
The macb driver will certainly evolve in order to add these features so 
we decided to match a new compatible string all the way to the driver.

Best regards,
   Nicolas


-- 
Nicolas Ferre

Re: [PATCH 21/21] net: macb: add support for gmac to sam9x7

[Arnd Bergmann]

On Mon, Jun 5, 2023, at 14:07, Nicolas Ferre wrote:
> On 05/06/2023 at 08:42, Krzysztof Kozlowski wrote:
>>>
>>> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
>>> index 29a1199dad14..609c8e9305ba 100644
>>> --- a/drivers/net/ethernet/cadence/macb_main.c
>>> +++ b/drivers/net/ethernet/cadence/macb_main.c
>>> @@ -4913,6 +4913,7 @@ static const struct of_device_id macb_dt_ids[] = {
>>>        { .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
>>>        { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
>>>        { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
>>> +     { .compatible = "microchip,sam9x7-gem", .data = &sama7g5_gem_config },
>> 
>> These are compatible, aren't they? Why do you need new entry?
>
> The hardware itself is different, even if the new features are not 
> supported yet in the macb driver.
> The macb driver will certainly evolve in order to add these features so 
> we decided to match a new compatible string all the way to the driver.

It sounds like you can still drop this patch though, and only add a
specific entry here after the .data field is actually different
when those features get added.

The important bit for now is to have the specific string in the binding
and in the dtb, along with the fallback for I assume "microchip,sama7g5-gem".

     Arnd

Re: [PATCH 21/21] net: macb: add support for gmac to sam9x7

[Krzysztof Kozlowski]

On 05/06/2023 14:07, Nicolas Ferre wrote:
> On 05/06/2023 at 08:42, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 03/06/2023 22:02, Varshini Rajendran wrote:
>>> From: Nicolas Ferre <nicolas.ferre@microchip.com>
>>>
>>> Add support for GMAC in sam9x7 SoC family
>>>
>>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>>> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
>>> ---
>>>   drivers/net/ethernet/cadence/macb_main.c | 1 +
>>>   1 file changed, 1 insertion(+)
>>>
>>> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
>>> index 29a1199dad14..609c8e9305ba 100644
>>> --- a/drivers/net/ethernet/cadence/macb_main.c
>>> +++ b/drivers/net/ethernet/cadence/macb_main.c
>>> @@ -4913,6 +4913,7 @@ static const struct of_device_id macb_dt_ids[] = {
>>>        { .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
>>>        { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
>>>        { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
>>> +     { .compatible = "microchip,sam9x7-gem", .data = &sama7g5_gem_config },
>>
>> These are compatible, aren't they? Why do you need new entry?
> 
> The hardware itself is different, even if the new features are not 
> supported yet in the macb driver.
> The macb driver will certainly evolve in order to add these features so 
> we decided to match a new compatible string all the way to the driver.

You claim to be fully compatible with sama7g5-gem, so adding new
features does not warrant not-reusing old match entry now.

Best regards,
Krzysztof