From: Andrew Jones <ajones@ventanamicro.com>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: devicetree@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>,
Jonathan Corbet <corbet@lwn.net>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
conor@kernel.org, Rob Herring <robh+dt@kernel.org>,
palmer@dabbelt.com, Palmer Dabbelt <palmer@rivosinc.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org,
Heiko Stuebner <heiko.stuebner@vrull.eu>,
Evan Green <evan@rivosinc.com>
Subject: Re: [PATCH v3 01/11] RISC-V: Provide a more helpful error message on invalid ISA strings
Date: Mon, 3 Jul 2023 12:36:44 +0200 [thread overview]
Message-ID: <20230703-8b9d59a770926dbfa5771966@orel> (raw)
In-Reply-To: <20230703-girdle-underling-880f633c4c73@wendy>
On Mon, Jul 03, 2023 at 11:27:53AM +0100, Conor Dooley wrote:
> From: Palmer Dabbelt <palmer@rivosinc.com>
>
> Right now we provide a somewhat unhelpful error message on systems with
> invalid error messages, something along the lines of
>
> CPU with hartid=0 is not available
> ------------[ cut here ]------------
> kernel BUG at arch/riscv/kernel/smpboot.c:174!
> Kernel BUG [#1]
> Modules linked in:
> CPU: 0 PID: 0 Comm: swapper Not tainted 6.4.0-rc1-00096-ge0097d2c62d5-dirty #1
> Hardware name: Microchip PolarFire-SoC Icicle Kit (DT)
> epc : of_parse_and_init_cpus+0x16c/0x16e
> ra : of_parse_and_init_cpus+0x9a/0x16e
> epc : ffffffff80c04e0a ra : ffffffff80c04d38 sp : ffffffff81603e20
> gp : ffffffff8182d658 tp : ffffffff81613f80 t0 : 000000000000006e
> t1 : 0000000000000064 t2 : 0000000000000000 s0 : ffffffff81603e80
> s1 : 0000000000000000 a0 : 0000000000000000 a1 : 0000000000000000
> a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000
> a5 : 0000000000001fff a6 : 0000000000001fff a7 : ffffffff816148b0
> s2 : 0000000000000001 s3 : ffffffff81492a4c s4 : ffffffff81a4b090
> s5 : ffffffff81506030 s6 : 0000000000000040 s7 : 0000000000000000
> s8 : 00000000bfb6f046 s9 : 0000000000000001 s10: 0000000000000000
> s11: 00000000bf389700 t3 : 0000000000000000 t4 : 0000000000000000
> t5 : ffffffff824dd188 t6 : ffffffff824dd187
> status: 0000000200000100 badaddr: 0000000000000000 cause: 0000000000000003
> [<ffffffff80c04e0a>] of_parse_and_init_cpus+0x16c/0x16e
> [<ffffffff80c04c96>] setup_smp+0x1e/0x26
> [<ffffffff80c03ffe>] setup_arch+0x6e/0xb2
> [<ffffffff80c00384>] start_kernel+0x72/0x400
> Code: 80e7 4a00 a603 0009 b795 1097 ffe5 80e7 92c0 9002 (9002) 715d
> ---[ end trace 0000000000000000 ]---
> Kernel panic - not syncing: Fatal exception in interrupt
>
> Add a warning for the cases where the ISA string isn't valid. It's still
> above the BUG_ON cut, but hopefully it's at least a bit easier for users.
>
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> arch/riscv/kernel/cpu.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index a2fc952318e9..3af2d214ce21 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -66,11 +66,15 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har
> return -ENODEV;
> }
>
> - if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7))
> + if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7)) {
> + pr_warn("CPU with hartid=%lu does not support rv32ima", *hart);
> return -ENODEV;
> + }
>
> - if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7))
> + if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7)) {
> + pr_warn("CPU with hartid=%lu does not support rv64ima", *hart);
> return -ENODEV;
> + }
>
> return 0;
> }
> --
> 2.40.1
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
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next prev parent reply other threads:[~2023-07-03 10:36 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-03 10:27 [PATCH v3 00/11] RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base Conor Dooley
2023-07-03 10:27 ` [PATCH v3 01/11] RISC-V: Provide a more helpful error message on invalid ISA strings Conor Dooley
2023-07-03 10:36 ` Andrew Jones [this message]
2023-07-05 15:51 ` Evan Green
2023-07-03 10:27 ` [PATCH v3 02/11] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Conor Dooley
2023-07-03 16:17 ` Conor Dooley
2023-07-03 10:27 ` [PATCH v3 03/11] RISC-V: drop a needless check in print_isa_ext() Conor Dooley
2023-07-03 10:27 ` [PATCH v3 04/11] RISC-V: shunt isa_ext_arr to cpufeature.c Conor Dooley
2023-07-03 16:17 ` Conor Dooley
2023-07-03 10:27 ` [PATCH v3 05/11] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() Conor Dooley
2023-07-03 10:27 ` [PATCH v3 06/11] RISC-V: add missing single letter extension definitions Conor Dooley
2023-07-03 16:18 ` Conor Dooley
2023-07-03 10:27 ` [PATCH v3 07/11] RISC-V: add single letter extensions to riscv_isa_ext Conor Dooley
2023-07-03 10:28 ` [PATCH v3 08/11] RISC-V: split riscv_fill_hwcap() in 3 Conor Dooley
2023-07-03 10:28 ` [PATCH v3 09/11] RISC-V: enable extension detection from new properties Conor Dooley
2023-07-03 10:28 ` [PATCH v3 10/11] RISC-V: try new extension properties in of_early_processor_hartid() Conor Dooley
2023-07-03 10:28 ` [PATCH v3 11/11] RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa" Conor Dooley
2023-07-03 10:44 ` Andrew Jones
2023-07-04 7:12 ` Conor Dooley
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