From: Conor Dooley <conor.dooley@microchip.com>
To: <palmer@dabbelt.com>
Cc: devicetree@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>,
Jonathan Corbet <corbet@lwn.net>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
conor@kernel.org, conor.dooley@microchip.com,
Rob Herring <robh+dt@kernel.org>, Evan Green <evan@rivosinc.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org,
Heiko Stuebner <heiko.stuebner@vrull.eu>,
Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH v3 02/11] RISC-V: don't parse dt/acpi isa string to get rv32/rv64
Date: Mon, 3 Jul 2023 11:27:54 +0100 [thread overview]
Message-ID: <20230703-foothill-enforced-86baba776d5e@wendy> (raw)
In-Reply-To: <20230703-repayment-vocalist-e4f3eeac2b2a@wendy>
From: Heiko Stuebner <heiko.stuebner@vrull.eu>
When filling hwcap the kernel already expects the isa string to start with
rv32 if CONFIG_32BIT and rv64 if CONFIG_64BIT.
So when recreating the runtime isa-string we can also just go the other way
to get the correct starting point for it.
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Co-developed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes in v3:
- Fix tabbing of print_mmu()
Changes in v2:
- Delete the whole else & pull print_mmu() above it, since that's common
code now
---
arch/riscv/kernel/cpu.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 3af2d214ce21..f808b67f5a27 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -257,13 +257,16 @@ static void print_isa_ext(struct seq_file *f)
*/
static const char base_riscv_exts[13] = "imafdqcbkjpvh";
-static void print_isa(struct seq_file *f, const char *isa)
+static void print_isa(struct seq_file *f)
{
int i;
seq_puts(f, "isa\t\t: ");
- /* Print the rv[64/32] part */
- seq_write(f, isa, 4);
+ if (IS_ENABLED(CONFIG_32BIT))
+ seq_write(f, "rv32", 4);
+ else
+ seq_write(f, "rv64", 4);
+
for (i = 0; i < sizeof(base_riscv_exts); i++) {
if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a'))
/* Print only enabled the base ISA extensions */
@@ -320,27 +323,21 @@ static int c_show(struct seq_file *m, void *v)
unsigned long cpu_id = (unsigned long)v - 1;
struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
struct device_node *node;
- const char *compat, *isa;
+ const char *compat;
seq_printf(m, "processor\t: %lu\n", cpu_id);
seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
+ print_isa(m);
+ print_mmu(m);
if (acpi_disabled) {
node = of_get_cpu_node(cpu_id, NULL);
- if (!of_property_read_string(node, "riscv,isa", &isa))
- print_isa(m, isa);
- print_mmu(m);
if (!of_property_read_string(node, "compatible", &compat) &&
strcmp(compat, "riscv"))
seq_printf(m, "uarch\t\t: %s\n", compat);
of_node_put(node);
- } else {
- if (!acpi_get_riscv_isa(NULL, cpu_id, &isa))
- print_isa(m, isa);
-
- print_mmu(m);
}
seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid);
--
2.40.1
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next prev parent reply other threads:[~2023-07-03 10:29 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-03 10:27 [PATCH v3 00/11] RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base Conor Dooley
2023-07-03 10:27 ` [PATCH v3 01/11] RISC-V: Provide a more helpful error message on invalid ISA strings Conor Dooley
2023-07-03 10:36 ` Andrew Jones
2023-07-05 15:51 ` Evan Green
2023-07-03 10:27 ` Conor Dooley [this message]
2023-07-03 16:17 ` [PATCH v3 02/11] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Conor Dooley
2023-07-03 10:27 ` [PATCH v3 03/11] RISC-V: drop a needless check in print_isa_ext() Conor Dooley
2023-07-03 10:27 ` [PATCH v3 04/11] RISC-V: shunt isa_ext_arr to cpufeature.c Conor Dooley
2023-07-03 16:17 ` Conor Dooley
2023-07-03 10:27 ` [PATCH v3 05/11] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() Conor Dooley
2023-07-03 10:27 ` [PATCH v3 06/11] RISC-V: add missing single letter extension definitions Conor Dooley
2023-07-03 16:18 ` Conor Dooley
2023-07-03 10:27 ` [PATCH v3 07/11] RISC-V: add single letter extensions to riscv_isa_ext Conor Dooley
2023-07-03 10:28 ` [PATCH v3 08/11] RISC-V: split riscv_fill_hwcap() in 3 Conor Dooley
2023-07-03 10:28 ` [PATCH v3 09/11] RISC-V: enable extension detection from new properties Conor Dooley
2023-07-03 10:28 ` [PATCH v3 10/11] RISC-V: try new extension properties in of_early_processor_hartid() Conor Dooley
2023-07-03 10:28 ` [PATCH v3 11/11] RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa" Conor Dooley
2023-07-03 10:44 ` Andrew Jones
2023-07-04 7:12 ` Conor Dooley
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