From: Conor Dooley <conor.dooley@microchip.com>
To: <palmer@dabbelt.com>
Cc: devicetree@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>,
Jonathan Corbet <corbet@lwn.net>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
conor@kernel.org, conor.dooley@microchip.com,
Rob Herring <robh+dt@kernel.org>, Evan Green <evan@rivosinc.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org,
Heiko Stuebner <heiko.stuebner@vrull.eu>,
Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH v3 05/11] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap()
Date: Mon, 3 Jul 2023 11:27:57 +0100 [thread overview]
Message-ID: <20230703-esteemed-broadside-6309c1fbc65a@wendy> (raw)
In-Reply-To: <20230703-repayment-vocalist-e4f3eeac2b2a@wendy>
In riscv_fill_hwcap() riscv_isa_ext array can be looped over, rather
than duplicating the list of extensions with individual
SET_ISA_EXT_MAP() usage. While at it, drop the statement-of-the-obvious
comments from the struct, rename uprop to something more suitable for
its new use & constify the members.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes in v2:
- Delete the now unused definition
---
arch/riscv/include/asm/hwcap.h | 7 ++-----
arch/riscv/kernel/cpu.c | 5 +++--
arch/riscv/kernel/cpufeature.c | 26 +++++++-------------------
3 files changed, 12 insertions(+), 26 deletions(-)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 7a57e6109aef..2460ac2fc7ed 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -55,7 +55,6 @@
#define RISCV_ISA_EXT_ZIHPM 42
#define RISCV_ISA_EXT_MAX 64
-#define RISCV_ISA_EXT_NAME_LEN_MAX 32
#ifdef CONFIG_RISCV_M_MODE
#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA
@@ -70,10 +69,8 @@
unsigned long riscv_get_elf_hwcap(void);
struct riscv_isa_ext_data {
- /* Name of the extension displayed to userspace via /proc/cpuinfo */
- char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
- /* The logical ISA extension ID */
- unsigned int isa_ext_id;
+ const unsigned int id;
+ const char *name;
};
extern const struct riscv_isa_ext_data riscv_isa_ext[];
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index bf93293d51f3..aa17eeb0ec9a 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -168,9 +168,10 @@ static void print_isa_ext(struct seq_file *f)
{
for (int i = 0; i < riscv_isa_ext_count; i++) {
const struct riscv_isa_ext_data *edata = &riscv_isa_ext[i];
- if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id))
+ if (!__riscv_isa_extension_available(NULL, edata->id))
continue;
- seq_printf(f, "_%s", edata->uprop);
+
+ seq_printf(f, "_%s", edata->name);
}
}
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index fb476153fffc..6d8cd45af723 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -99,11 +99,10 @@ static bool riscv_isa_extension_check(int id)
return true;
}
-#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \
- { \
- .uprop = #UPROP, \
- .isa_ext_id = EXTID, \
- }
+#define __RISCV_ISA_EXT_DATA(_name, _id) { \
+ .name = #_name, \
+ .id = _id, \
+}
/*
* The canonical order of ISA extension names in the ISA string is defined in
@@ -366,20 +365,9 @@ void __init riscv_fill_hwcap(void)
set_bit(nr, isainfo->isa);
}
} else {
- /* sorted alphabetically */
- SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
- SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
- SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
- SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
- SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
- SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
- SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
- SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA);
- SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
- SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS);
- SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
- SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);
- SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
+ for (int i = 0; i < riscv_isa_ext_count; i++)
+ SET_ISA_EXT_MAP(riscv_isa_ext[i].name,
+ riscv_isa_ext[i].id);
}
#undef SET_ISA_EXT_MAP
}
--
2.40.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-07-03 10:29 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-03 10:27 [PATCH v3 00/11] RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base Conor Dooley
2023-07-03 10:27 ` [PATCH v3 01/11] RISC-V: Provide a more helpful error message on invalid ISA strings Conor Dooley
2023-07-03 10:36 ` Andrew Jones
2023-07-05 15:51 ` Evan Green
2023-07-03 10:27 ` [PATCH v3 02/11] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Conor Dooley
2023-07-03 16:17 ` Conor Dooley
2023-07-03 10:27 ` [PATCH v3 03/11] RISC-V: drop a needless check in print_isa_ext() Conor Dooley
2023-07-03 10:27 ` [PATCH v3 04/11] RISC-V: shunt isa_ext_arr to cpufeature.c Conor Dooley
2023-07-03 16:17 ` Conor Dooley
2023-07-03 10:27 ` Conor Dooley [this message]
2023-07-03 10:27 ` [PATCH v3 06/11] RISC-V: add missing single letter extension definitions Conor Dooley
2023-07-03 16:18 ` Conor Dooley
2023-07-03 10:27 ` [PATCH v3 07/11] RISC-V: add single letter extensions to riscv_isa_ext Conor Dooley
2023-07-03 10:28 ` [PATCH v3 08/11] RISC-V: split riscv_fill_hwcap() in 3 Conor Dooley
2023-07-03 10:28 ` [PATCH v3 09/11] RISC-V: enable extension detection from new properties Conor Dooley
2023-07-03 10:28 ` [PATCH v3 10/11] RISC-V: try new extension properties in of_early_processor_hartid() Conor Dooley
2023-07-03 10:28 ` [PATCH v3 11/11] RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa" Conor Dooley
2023-07-03 10:44 ` Andrew Jones
2023-07-04 7:12 ` Conor Dooley
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230703-esteemed-broadside-6309c1fbc65a@wendy \
--to=conor.dooley@microchip.com \
--cc=ajones@ventanamicro.com \
--cc=aou@eecs.berkeley.edu \
--cc=conor@kernel.org \
--cc=corbet@lwn.net \
--cc=devicetree@vger.kernel.org \
--cc=evan@rivosinc.com \
--cc=heiko.stuebner@vrull.eu \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).