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From: Conor Dooley <conor.dooley@microchip.com>
To: <palmer@dabbelt.com>
Cc: devicetree@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>,
	Jonathan Corbet <corbet@lwn.net>,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	conor@kernel.org, conor.dooley@microchip.com,
	Rob Herring <robh+dt@kernel.org>, Evan Green <evan@rivosinc.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	linux-riscv@lists.infradead.org,
	Heiko Stuebner <heiko.stuebner@vrull.eu>,
	Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH v3 06/11] RISC-V: add missing single letter extension definitions
Date: Mon, 3 Jul 2023 11:27:58 +0100	[thread overview]
Message-ID: <20230703-unlocking-straining-5c814e99642b@wendy> (raw)
In-Reply-To: <20230703-repayment-vocalist-e4f3eeac2b2a@wendy>

To facilitate adding single letter extensions to riscv_isa_ext, add
definitions for the extensions present in base_riscv_exts that do not
already have them.

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/include/asm/hwcap.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 2460ac2fc7ed..a20e4ade1b53 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -14,12 +14,17 @@
 #include <uapi/asm/hwcap.h>
 
 #define RISCV_ISA_EXT_a		('a' - 'a')
+#define RISCV_ISA_EXT_b		('b' - 'a')
 #define RISCV_ISA_EXT_c		('c' - 'a')
 #define RISCV_ISA_EXT_d		('d' - 'a')
 #define RISCV_ISA_EXT_f		('f' - 'a')
 #define RISCV_ISA_EXT_h		('h' - 'a')
 #define RISCV_ISA_EXT_i		('i' - 'a')
+#define RISCV_ISA_EXT_j		('j' - 'a')
+#define RISCV_ISA_EXT_k		('k' - 'a')
 #define RISCV_ISA_EXT_m		('m' - 'a')
+#define RISCV_ISA_EXT_p		('p' - 'a')
+#define RISCV_ISA_EXT_q		('q' - 'a')
 #define RISCV_ISA_EXT_s		('s' - 'a')
 #define RISCV_ISA_EXT_u		('u' - 'a')
 #define RISCV_ISA_EXT_v		('v' - 'a')
-- 
2.40.1


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  parent reply	other threads:[~2023-07-03 10:29 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-03 10:27 [PATCH v3 00/11] RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base Conor Dooley
2023-07-03 10:27 ` [PATCH v3 01/11] RISC-V: Provide a more helpful error message on invalid ISA strings Conor Dooley
2023-07-03 10:36   ` Andrew Jones
2023-07-05 15:51   ` Evan Green
2023-07-03 10:27 ` [PATCH v3 02/11] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Conor Dooley
2023-07-03 16:17   ` Conor Dooley
2023-07-03 10:27 ` [PATCH v3 03/11] RISC-V: drop a needless check in print_isa_ext() Conor Dooley
2023-07-03 10:27 ` [PATCH v3 04/11] RISC-V: shunt isa_ext_arr to cpufeature.c Conor Dooley
2023-07-03 16:17   ` Conor Dooley
2023-07-03 10:27 ` [PATCH v3 05/11] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() Conor Dooley
2023-07-03 10:27 ` Conor Dooley [this message]
2023-07-03 16:18   ` [PATCH v3 06/11] RISC-V: add missing single letter extension definitions Conor Dooley
2023-07-03 10:27 ` [PATCH v3 07/11] RISC-V: add single letter extensions to riscv_isa_ext Conor Dooley
2023-07-03 10:28 ` [PATCH v3 08/11] RISC-V: split riscv_fill_hwcap() in 3 Conor Dooley
2023-07-03 10:28 ` [PATCH v3 09/11] RISC-V: enable extension detection from new properties Conor Dooley
2023-07-03 10:28 ` [PATCH v3 10/11] RISC-V: try new extension properties in of_early_processor_hartid() Conor Dooley
2023-07-03 10:28 ` [PATCH v3 11/11] RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa" Conor Dooley
2023-07-03 10:44   ` Andrew Jones
2023-07-04  7:12   ` Conor Dooley

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