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From: Taylor Simpson <tsimpson@quicinc.com>
To: qemu-devel@nongnu.org
Cc: riku.voipio@iki.fi, richard.henderson@linaro.org,
	laurent@vivier.eu, Taylor Simpson <tsimpson@quicinc.com>,
	philmd@redhat.com, aleksandar.m.mail@gmail.com
Subject: [RFC PATCH v2 34/67] Hexagon TCG generation helpers - step 1
Date: Fri, 28 Feb 2020 10:43:30 -0600	[thread overview]
Message-ID: <1582908244-304-35-git-send-email-tsimpson@quicinc.com> (raw)
In-Reply-To: <1582908244-304-1-git-send-email-tsimpson@quicinc.com>

Helpers for reading and writing registers
Helpers for getting and setting parts of values (e.g., set bit)

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
 target/hexagon/genptr_helpers.h | 337 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 337 insertions(+)
 create mode 100644 target/hexagon/genptr_helpers.h

diff --git a/target/hexagon/genptr_helpers.h b/target/hexagon/genptr_helpers.h
new file mode 100644
index 0000000..d8d5d95
--- /dev/null
+++ b/target/hexagon/genptr_helpers.h
@@ -0,0 +1,337 @@
+/*
+ *  Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HEXAGON_GENPTR_HELPERS_H
+#define HEXAGON_GENPTR_HELPERS_H
+
+#include "tcg/tcg.h"
+
+static inline TCGv gen_read_reg(TCGv result, int num)
+{
+    tcg_gen_mov_tl(result, hex_gpr[num]);
+    return result;
+}
+
+static inline TCGv gen_read_preg(TCGv pred, uint8_t num)
+{
+    tcg_gen_mov_tl(pred, hex_pred[num]);
+    return pred;
+}
+
+static inline TCGv gen_newreg_st(TCGv result, TCGv_env cpu_env, TCGv rnum)
+{
+    gen_helper_new_value(result, cpu_env, rnum);
+    return result;
+}
+
+static inline bool is_preloaded(DisasContext *ctx, int num)
+{
+    int i;
+    for (i = 0; i < ctx->ctx_reg_log_idx; i++) {
+        if (ctx->ctx_reg_log[i] == num) {
+            return true;
+        }
+    }
+    return false;
+}
+
+static inline void gen_log_reg_write(int rnum, TCGv val, int slot,
+                                     int is_predicated)
+{
+    if (is_predicated) {
+        TCGv one = tcg_const_tl(1);
+        TCGv zero = tcg_const_tl(0);
+        TCGv slot_mask = tcg_temp_new();
+
+        tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
+        tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
+                           val, hex_new_value[rnum]);
+#if HEX_DEBUG
+        /* Do this so HELPER(debug_commit_end) will know */
+        tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum], slot_mask, zero,
+                           one, hex_reg_written[rnum]);
+#endif
+
+        tcg_temp_free(one);
+        tcg_temp_free(zero);
+        tcg_temp_free(slot_mask);
+    } else {
+        tcg_gen_mov_tl(hex_new_value[rnum], val);
+#if HEX_DEBUG
+        /* Do this so HELPER(debug_commit_end) will know */
+        tcg_gen_movi_tl(hex_reg_written[rnum], 1);
+#endif
+    }
+}
+
+static inline void gen_log_reg_write_pair(int rnum, TCGv_i64 val, int slot,
+                                          int is_predicated)
+{
+    TCGv val32 = tcg_temp_new();
+
+    if (is_predicated) {
+        TCGv one = tcg_const_tl(1);
+        TCGv zero = tcg_const_tl(0);
+        TCGv slot_mask = tcg_temp_new();
+
+        tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
+        /* Low word */
+        tcg_gen_extrl_i64_i32(val32, val);
+        tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
+                           val32, hex_new_value[rnum]);
+        /* High word */
+        tcg_gen_extrh_i64_i32(val32, val);
+        tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum + 1],
+                           slot_mask, zero,
+                           val32, hex_new_value[rnum + 1]);
+
+        tcg_temp_free(one);
+        tcg_temp_free(zero);
+        tcg_temp_free(slot_mask);
+    } else {
+        /* Low word */
+        tcg_gen_extrl_i64_i32(val32, val);
+        tcg_gen_mov_tl(hex_new_value[rnum], val32);
+        /* High word */
+        tcg_gen_extrh_i64_i32(val32, val);
+        tcg_gen_mov_tl(hex_new_value[rnum + 1], val32);
+    }
+
+    tcg_temp_free(val32);
+}
+
+static inline void gen_log_pred_write(int pnum, TCGv val)
+{
+    TCGv zero = tcg_const_tl(0);
+    TCGv base_val = tcg_temp_new();
+    TCGv and_val = tcg_temp_new();
+    TCGv pred_written = tcg_temp_new();
+
+    /* Multiple writes to the same preg are and'ed together */
+    tcg_gen_andi_tl(base_val, val, 0xff);
+    tcg_gen_and_tl(and_val, base_val, hex_new_pred_value[pnum]);
+    tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pnum);
+    tcg_gen_movcond_tl(TCG_COND_NE, hex_new_pred_value[pnum],
+                       pred_written, zero,
+                       and_val, base_val);
+    tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum);
+
+    tcg_temp_free(zero);
+    tcg_temp_free(base_val);
+    tcg_temp_free(and_val);
+    tcg_temp_free(pred_written);
+}
+
+static inline void gen_read_p3_0(TCGv control_reg)
+{
+    TCGv pval = tcg_temp_new();
+    int i;
+    tcg_gen_movi_tl(control_reg, 0);
+    for (i = NUM_PREGS - 1; i >= 0; i--) {
+        tcg_gen_shli_tl(control_reg, control_reg, 8);
+        tcg_gen_andi_tl(pval, hex_pred[i], 0xff);
+        tcg_gen_or_tl(control_reg, control_reg, pval);
+    }
+    tcg_temp_free(pval);
+}
+
+static inline void gen_write_p3_0(TCGv tmp)
+{
+    TCGv control_reg = tcg_temp_new();
+    TCGv pred_val = tcg_temp_new();
+    int i;
+
+    tcg_gen_mov_tl(control_reg, tmp);
+    for (i = 0; i < NUM_PREGS; i++) {
+        tcg_gen_andi_tl(pred_val, control_reg, 0xff);
+        tcg_gen_mov_tl(hex_pred[i], pred_val);
+        tcg_gen_shri_tl(control_reg, control_reg, 8);
+    }
+    tcg_temp_free(control_reg);
+    tcg_temp_free(pred_val);
+}
+
+static inline TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign)
+{
+    TCGv shift = tcg_const_tl(8 * N);
+    TCGv mask = tcg_const_tl(0xff);
+
+    tcg_gen_shr_tl(result, src, shift);
+    tcg_gen_and_tl(result, result, mask);
+    if (sign) {
+        tcg_gen_ext8s_tl(result, result);
+    } else {
+        tcg_gen_ext8u_tl(result, result);
+    }
+    tcg_temp_free(mask);
+    tcg_temp_free(shift);
+
+    return result;
+}
+
+static inline TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign)
+{
+    TCGv_i64 result_i64 = tcg_temp_new_i64();
+    TCGv_i64 shift = tcg_const_i64(8 * N);
+    TCGv_i64 mask = tcg_const_i64(0xff);
+    tcg_gen_shr_i64(result_i64, src, shift);
+    tcg_gen_and_i64(result_i64, result_i64, mask);
+    tcg_gen_extrl_i64_i32(result, result_i64);
+    if (sign) {
+        tcg_gen_ext8s_tl(result, result);
+    } else {
+        tcg_gen_ext8u_tl(result, result);
+    }
+    tcg_temp_free_i64(result_i64);
+    tcg_temp_free_i64(shift);
+    tcg_temp_free_i64(mask);
+
+    return result;
+
+}
+static inline TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign)
+{
+    TCGv shift = tcg_const_tl(16 * N);
+    TCGv mask = tcg_const_tl(0xffff);
+
+    tcg_gen_shr_tl(result, src, shift);
+    tcg_gen_and_tl(result, result, mask);
+    if (sign) {
+        tcg_gen_ext16s_tl(result, result);
+    } else {
+        tcg_gen_ext16u_tl(result, result);
+    }
+    tcg_temp_free(mask);
+    tcg_temp_free(shift);
+
+    return result;
+}
+
+static inline void gen_set_half(int N, TCGv result, TCGv src)
+{
+    TCGv mask1 = tcg_const_tl(~(0xffff << (N * 16)));
+    TCGv mask2 = tcg_const_tl(0xffff);
+    TCGv shift = tcg_const_tl(N * 16);
+    TCGv tmp = tcg_temp_new();
+
+    tcg_gen_and_tl(result, result, mask1);
+    tcg_gen_and_tl(tmp, src, mask2);
+    tcg_gen_shli_tl(tmp, tmp, N * 16);
+    tcg_gen_or_tl(result, result, tmp);
+
+    tcg_temp_free(mask1);
+    tcg_temp_free(mask2);
+    tcg_temp_free(shift);
+    tcg_temp_free(tmp);
+}
+
+static inline void gen_set_half_i64(int N, TCGv_i64 result, TCGv src)
+{
+    TCGv_i64 mask1 = tcg_const_i64(~(0xffffLL << (N * 16)));
+    TCGv_i64 mask2 = tcg_const_i64(0xffffLL);
+    TCGv_i64 shift = tcg_const_i64(N * 16);
+    TCGv_i64 tmp = tcg_temp_new_i64();
+
+    tcg_gen_and_i64(result, result, mask1);
+    tcg_gen_concat_i32_i64(tmp, src, src);
+    tcg_gen_and_i64(tmp, tmp, mask2);
+    tcg_gen_shli_i64(tmp, tmp, N * 16);
+    tcg_gen_or_i64(result, result, tmp);
+
+    tcg_temp_free_i64(mask1);
+    tcg_temp_free_i64(mask2);
+    tcg_temp_free_i64(shift);
+    tcg_temp_free_i64(tmp);
+}
+
+static inline void gen_set_byte(int N, TCGv result, TCGv src)
+{
+    TCGv mask1 = tcg_const_tl(~(0xff << (N * 8)));
+    TCGv mask2 = tcg_const_tl(0xff);
+    TCGv shift = tcg_const_tl(N * 8);
+    TCGv tmp = tcg_temp_new();
+
+    tcg_gen_and_tl(result, result, mask1);
+    tcg_gen_and_tl(tmp, src, mask2);
+    tcg_gen_shli_tl(tmp, tmp, N * 8);
+    tcg_gen_or_tl(result, result, tmp);
+
+    tcg_temp_free(mask1);
+    tcg_temp_free(mask2);
+    tcg_temp_free(shift);
+    tcg_temp_free(tmp);
+}
+
+static inline void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
+{
+    TCGv_i64 mask1 = tcg_const_i64(~(0xffLL << (N * 8)));
+    TCGv_i64 mask2 = tcg_const_i64(0xffLL);
+    TCGv_i64 shift = tcg_const_i64(N * 8);
+    TCGv_i64 tmp = tcg_temp_new_i64();
+
+    tcg_gen_and_i64(result, result, mask1);
+    tcg_gen_concat_i32_i64(tmp, src, src);
+    tcg_gen_and_i64(tmp, tmp, mask2);
+    tcg_gen_shli_i64(tmp, tmp, N * 8);
+    tcg_gen_or_i64(result, result, tmp);
+
+    tcg_temp_free_i64(mask1);
+    tcg_temp_free_i64(mask2);
+    tcg_temp_free_i64(shift);
+    tcg_temp_free_i64(tmp);
+}
+
+static inline TCGv gen_get_word(TCGv result, int N, TCGv_i64 src, bool sign)
+{
+    if (N == 0) {
+        tcg_gen_extrl_i64_i32(result, src);
+    } else if (N == 1) {
+        tcg_gen_extrh_i64_i32(result, src);
+    } else {
+      g_assert_not_reached();
+    }
+    return result;
+}
+
+static inline TCGv_i64 gen_get_word_i64(TCGv_i64 result, int N, TCGv_i64 src,
+                                        bool sign)
+{
+    TCGv word = tcg_temp_new();
+    gen_get_word(word, N, src, sign);
+    if (sign) {
+        tcg_gen_ext_i32_i64(result, word);
+    } else {
+        tcg_gen_extu_i32_i64(result, word);
+    }
+    tcg_temp_free(word);
+    return result;
+}
+
+static inline TCGv gen_set_bit(int i, TCGv result, TCGv src)
+{
+    TCGv mask = tcg_const_tl(~(1 << i));
+    TCGv bit = tcg_temp_new();
+    tcg_gen_shli_tl(bit, src, i);
+    tcg_gen_and_tl(result, result, mask);
+    tcg_gen_or_tl(result, result, bit);
+    tcg_temp_free(mask);
+    tcg_temp_free(bit);
+
+    return result;
+}
+
+#endif
-- 
2.7.4


  parent reply	other threads:[~2020-02-28 17:13 UTC|newest]

Thread overview: 72+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-28 16:42 [RFC PATCH v2 00/67] Hexagon patch series Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 01/67] Hexagon Maintainers Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 02/67] Hexagon README Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 03/67] Hexagon ELF Machine Definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 04/67] Hexagon CPU Scalar Core Definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 05/67] Hexagon register names Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 06/67] Hexagon Disassembler Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 07/67] Hexagon CPU Scalar Core Helpers Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 08/67] Hexagon GDB Stub Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 09/67] Hexagon architecture types Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 10/67] Hexagon instruction and packet types Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 11/67] Hexagon register fields Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 12/67] Hexagon instruction attributes Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 13/67] Hexagon register map Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 14/67] Hexagon instruction/packet decode Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 15/67] Hexagon instruction printing Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 16/67] Hexagon arch import - instruction semantics definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 17/67] Hexagon arch import - macro definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 18/67] Hexagon arch import - instruction encoding Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 19/67] Hexagon instruction class definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 20/67] Hexagon instruction utility functions Taylor Simpson
2020-04-09 18:53   ` Brian Cain
2020-04-09 20:22     ` Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 21/67] Hexagon generator phase 1 - C preprocessor for semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 22/67] Hexagon generator phase 2 - qemu_def_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 23/67] Hexagon generator phase 2 - qemu_wrap_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 24/67] Hexagon generator phase 2 - opcodes_def_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 25/67] Hexagon generator phase 2 - op_attribs_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 26/67] Hexagon generator phase 2 - op_regs_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 27/67] Hexagon generator phase 2 - printinsn-generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 28/67] Hexagon generator phase 3 - C preprocessor for decode tree Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 29/67] Hexagon generater phase 4 - Decode tree Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 30/67] Hexagon opcode data structures Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 31/67] Hexagon macros to interface with the generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 32/67] Hexagon macros referenced in instruction semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 33/67] Hexagon instruction classes Taylor Simpson
2020-02-28 16:43 ` Taylor Simpson [this message]
2020-02-28 16:43 ` [RFC PATCH v2 35/67] Hexagon TCG generation helpers - step 2 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 36/67] Hexagon TCG generation helpers - step 3 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 37/67] Hexagon TCG generation helpers - step 4 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 38/67] Hexagon TCG generation helpers - step 5 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 39/67] Hexagon TCG generation - step 01 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 40/67] Hexagon TCG generation - step 02 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 41/67] Hexagon TCG generation - step 03 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 42/67] Hexagon TCG generation - step 04 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 43/67] Hexagon TCG generation - step 05 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 44/67] Hexagon TCG generation - step 06 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 45/67] Hexagon TCG generation - step 07 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 46/67] Hexagon TCG generation - step 08 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 47/67] Hexagon TCG generation - step 09 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 48/67] Hexagon TCG generation - step 10 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 49/67] Hexagon TCG generation - step 11 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 50/67] Hexagon TCG generation - step 12 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 51/67] Hexagon translation Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 52/67] Hexagon Linux user emulation Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 53/67] Hexagon build infrastructure Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 54/67] Hexagon - Add Hexagon Vector eXtensions (HVX) to core definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 55/67] Hexagon HVX support in gdbstub Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 56/67] Hexagon HVX import instruction encodings Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 57/67] Hexagon HVX import semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 58/67] Hexagon HVX import macro definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 59/67] Hexagon HVX semantics generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 60/67] Hexagon HVX instruction decoding Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 61/67] Hexagon HVX instruction utility functions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 62/67] Hexagon HVX macros to interface with the generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 63/67] Hexagon HVX macros referenced in instruction semantics Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 64/67] Hexagon HVX helper to commit vector stores (masked and scatter/gather) Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 65/67] Hexagon HVX TCG generation Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 66/67] Hexagon HVX translation Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 67/67] Hexagon HVX build infrastructure Taylor Simpson
2020-03-25 21:13 ` [RFC PATCH v2 00/67] Hexagon patch series Taylor Simpson
2020-04-30 20:53   ` Taylor Simpson

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