From: Taylor Simpson <tsimpson@quicinc.com>
To: qemu-devel@nongnu.org
Cc: riku.voipio@iki.fi, richard.henderson@linaro.org,
laurent@vivier.eu, Taylor Simpson <tsimpson@quicinc.com>,
philmd@redhat.com, aleksandar.m.mail@gmail.com
Subject: [RFC PATCH v2 07/67] Hexagon CPU Scalar Core Helpers
Date: Fri, 28 Feb 2020 10:43:03 -0600 [thread overview]
Message-ID: <1582908244-304-8-git-send-email-tsimpson@quicinc.com> (raw)
In-Reply-To: <1582908244-304-1-git-send-email-tsimpson@quicinc.com>
The majority of helpers are generated. Define the helper functions needed
then include the generated file
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/helper.h | 37 ++++
target/hexagon/op_helper.c | 434 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 471 insertions(+)
create mode 100644 target/hexagon/helper.h
create mode 100644 target/hexagon/op_helper.c
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
new file mode 100644
index 0000000..8558da8
--- /dev/null
+++ b/target/hexagon/helper.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "helper_overrides.h"
+
+DEF_HELPER_2(raise_exception, noreturn, env, i32)
+DEF_HELPER_1(debug_start_packet, void, env)
+DEF_HELPER_2(new_value, s32, env, int)
+DEF_HELPER_3(debug_check_store_width, void, env, int, int)
+DEF_HELPER_3(debug_commit_end, void, env, int, int)
+DEF_HELPER_3(sfrecipa_val, s32, env, s32, s32)
+DEF_HELPER_3(sfrecipa_pred, s32, env, s32, s32)
+DEF_HELPER_2(sfinvsqrta_val, s32, env, s32)
+DEF_HELPER_2(sfinvsqrta_pred, s32, env, s32)
+DEF_HELPER_4(vacsh_val, s64, env, s64, s64, s64)
+DEF_HELPER_4(vacsh_pred, s32, env, s64, s64, s64)
+
+#define DEF_QEMU(TAG, SHORTCODE, HELPER, GENFN, HELPFN) HELPER
+#include "qemu_def_generated.h"
+#undef DEF_QEMU
+
+DEF_HELPER_2(debug_value, void, env, s32)
+DEF_HELPER_2(debug_value_i64, void, env, s64)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
new file mode 100644
index 0000000..d944d03
--- /dev/null
+++ b/target/hexagon/op_helper.c
@@ -0,0 +1,434 @@
+/*
+ * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <math.h>
+#include "qemu/osdep.h"
+#include "qemu.h"
+#include "exec/helper-proto.h"
+#include "tcg/tcg-op.h"
+#include "cpu.h"
+#include "internal.h"
+#include "macros.h"
+#include "arch.h"
+#include "fma_emu.h"
+#include "conv_emu.h"
+
+#if COUNT_HEX_HELPERS
+#include "opcodes.h"
+
+typedef struct {
+ int count;
+ const char *tag;
+} helper_count_t;
+
+helper_count_t helper_counts[] = {
+#define OPCODE(TAG) { 0, #TAG },
+#include "opcodes_def_generated.h"
+#undef OPCODE
+ { 0, NULL }
+};
+
+#define COUNT_HELPER(TAG) \
+ do { \
+ helper_counts[(TAG)].count++; \
+ } while (0)
+
+void print_helper_counts(void)
+{
+ helper_count_t *p;
+
+ printf("HELPER COUNTS\n");
+ for (p = helper_counts; p->tag; p++) {
+ if (p->count) {
+ printf("\t%d\t\t%s\n", p->count, p->tag);
+ }
+ }
+}
+#else
+#define COUNT_HELPER(TAG) /* Nothing */
+#endif
+
+/* Exceptions processing helpers */
+static void QEMU_NORETURN do_raise_exception_err(CPUHexagonState *env,
+ uint32_t exception,
+ uintptr_t pc)
+{
+ CPUState *cs = CPU(hexagon_env_get_cpu(env));
+ qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception);
+ cs->exception_index = exception;
+ cpu_loop_exit_restore(cs, pc);
+}
+
+void HELPER(raise_exception)(CPUHexagonState *env, uint32_t exception)
+{
+ do_raise_exception_err(env, exception, 0);
+}
+
+static inline void log_reg_write(CPUHexagonState *env, int rnum,
+ target_ulong val, uint32_t slot)
+{
+ HEX_DEBUG_LOG("log_reg_write[%d] = " TARGET_FMT_ld " (0x" TARGET_FMT_lx ")",
+ rnum, val, val);
+ if (env->slot_cancelled & (1 << slot)) {
+ HEX_DEBUG_LOG(" CANCELLED");
+ }
+ if (val == env->gpr[rnum]) {
+ HEX_DEBUG_LOG(" NO CHANGE");
+ }
+ HEX_DEBUG_LOG("\n");
+ if (!(env->slot_cancelled & (1 << slot))) {
+ env->new_value[rnum] = val;
+#if HEX_DEBUG
+ /* Do this so HELPER(debug_commit_end) will know */
+ env->reg_written[rnum] = 1;
+#endif
+ }
+}
+
+static __attribute__((unused))
+inline void log_reg_write_pair(CPUHexagonState *env, int rnum,
+ int64_t val, uint32_t slot)
+{
+ HEX_DEBUG_LOG("log_reg_write_pair[%d:%d] = %ld\n", rnum + 1, rnum, val);
+ log_reg_write(env, rnum, val & 0xFFFFFFFF, slot);
+ log_reg_write(env, rnum + 1, (val >> 32) & 0xFFFFFFFF, slot);
+}
+
+static inline void log_pred_write(CPUHexagonState *env, int pnum,
+ target_ulong val)
+{
+ HEX_DEBUG_LOG("log_pred_write[%d] = " TARGET_FMT_ld
+ " (0x" TARGET_FMT_lx ")\n",
+ pnum, val, val);
+
+ /* Multiple writes to the same preg are and'ed together */
+ if (env->pred_written & (1 << pnum)) {
+ env->new_pred_value[pnum] &= val & 0xff;
+ } else {
+ env->new_pred_value[pnum] = val & 0xff;
+ env->pred_written |= 1 << pnum;
+ }
+}
+
+static inline void log_store32(CPUHexagonState *env, target_ulong addr,
+ target_ulong val, int width, int slot)
+{
+ HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx ", " TARGET_FMT_ld
+ " [0x" TARGET_FMT_lx "])\n",
+ width, addr, val, val);
+ env->mem_log_stores[slot].va = addr;
+ env->mem_log_stores[slot].width = width;
+ env->mem_log_stores[slot].data32 = val;
+}
+
+static inline void log_store64(CPUHexagonState *env, target_ulong addr,
+ int64_t val, int width, int slot)
+{
+ HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx ", %ld [0x%lx])\n",
+ width, addr, val, val);
+ env->mem_log_stores[slot].va = addr;
+ env->mem_log_stores[slot].width = width;
+ env->mem_log_stores[slot].data64 = val;
+}
+
+static inline void write_new_pc(CPUHexagonState *env, target_ulong addr)
+{
+ HEX_DEBUG_LOG("write_new_pc(0x" TARGET_FMT_lx ")\n", addr);
+
+ /*
+ * If more than one branch it taken in a packet, only the first one
+ * is actually done.
+ */
+ if (env->branch_taken) {
+ HEX_DEBUG_LOG("INFO: multiple branches taken in same packet, "
+ "ignoring the second one\n");
+ } else {
+ fCHECK_PCALIGN(addr);
+ env->branch_taken = 1;
+ env->next_PC = addr;
+ }
+}
+
+/* Handy place to set a breakpoint */
+void HELPER(debug_start_packet)(CPUHexagonState *env)
+{
+ HEX_DEBUG_LOG("Start packet: pc = 0x" TARGET_FMT_lx "\n",
+ env->gpr[HEX_REG_PC]);
+
+ int i;
+ for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) {
+ env->reg_written[i] = 0;
+ }
+}
+
+/*
+ * This helper is needed when the rnum has already been turned into a TCGv,
+ * so we can't just do tcg_gen_mov_tl(result, hex_new_value[rnum]);
+ */
+int32_t HELPER(new_value)(CPUHexagonState *env, int rnum)
+{
+ return env->new_value[rnum];
+}
+
+static inline int32_t new_pred_value(CPUHexagonState *env, int pnum)
+{
+ return env->new_pred_value[pnum];
+}
+
+/* Checks for bookkeeping errors between disassembly context and runtime */
+void HELPER(debug_check_store_width)(CPUHexagonState *env, int slot, int check)
+{
+ if (env->mem_log_stores[slot].width != check) {
+ HEX_DEBUG_LOG("ERROR: %d != %d\n",
+ env->mem_log_stores[slot].width, check);
+ g_assert_not_reached();
+ }
+}
+
+static void print_store(CPUHexagonState *env, int slot)
+{
+ if (!(env->slot_cancelled & (1 << slot))) {
+ size1u_t width = env->mem_log_stores[slot].width;
+ if (width == 1) {
+ size4u_t data = env->mem_log_stores[slot].data32 & 0xff;
+ HEX_DEBUG_LOG("\tmemb[0x" TARGET_FMT_lx "] = %d (0x%02x)\n",
+ env->mem_log_stores[slot].va, data, data);
+ } else if (width == 2) {
+ size4u_t data = env->mem_log_stores[slot].data32 & 0xffff;
+ HEX_DEBUG_LOG("\tmemh[0x" TARGET_FMT_lx "] = %d (0x%04x)\n",
+ env->mem_log_stores[slot].va, data, data);
+ } else if (width == 4) {
+ size4u_t data = env->mem_log_stores[slot].data32;
+ HEX_DEBUG_LOG("\tmemw[0x" TARGET_FMT_lx "] = %d (0x%08x)\n",
+ env->mem_log_stores[slot].va, data, data);
+ } else if (width == 8) {
+ HEX_DEBUG_LOG("\tmemd[0x" TARGET_FMT_lx "] = %lu (0x%016lx)\n",
+ env->mem_log_stores[slot].va,
+ env->mem_log_stores[slot].data64,
+ env->mem_log_stores[slot].data64);
+ } else {
+ HEX_DEBUG_LOG("\tBad store width %d\n", width);
+ g_assert_not_reached();
+ }
+ }
+}
+
+/* This function is a handy place to set a breakpoint */
+void HELPER(debug_commit_end)(CPUHexagonState *env, int has_st0, int has_st1)
+{
+ bool reg_printed = false;
+ bool pred_printed = false;
+ int i;
+
+ HEX_DEBUG_LOG("Packet committed: pc = 0x" TARGET_FMT_lx "\n",
+ env->this_PC);
+ HEX_DEBUG_LOG("slot_cancelled = %d\n", env->slot_cancelled);
+
+ for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) {
+ if (env->reg_written[i]) {
+ if (!reg_printed) {
+ HEX_DEBUG_LOG("Regs written\n");
+ reg_printed = true;
+ }
+ HEX_DEBUG_LOG("\tr%d = " TARGET_FMT_ld " (0x" TARGET_FMT_lx " )\n",
+ i, env->new_value[i], env->new_value[i]);
+ }
+ }
+
+ for (i = 0; i < NUM_PREGS; i++) {
+ if (env->pred_written & (1 << i)) {
+ if (!pred_printed) {
+ HEX_DEBUG_LOG("Predicates written\n");
+ pred_printed = true;
+ }
+ HEX_DEBUG_LOG("\tp%d = 0x" TARGET_FMT_lx "\n",
+ i, env->new_pred_value[i]);
+ }
+ }
+
+ if (has_st0 || has_st1) {
+ HEX_DEBUG_LOG("Stores\n");
+ if (has_st0) {
+ print_store(env, 0);
+ }
+ if (has_st1) {
+ print_store(env, 1);
+ }
+ }
+
+ HEX_DEBUG_LOG("Next PC = 0x%x\n", env->next_PC);
+ HEX_DEBUG_LOG("Exec counters: pkt = " TARGET_FMT_lx
+ ", insn = " TARGET_FMT_lx
+ ", hvx = " TARGET_FMT_lx "\n",
+ env->gpr[HEX_REG_QEMU_PKT_CNT],
+ env->gpr[HEX_REG_QEMU_INSN_CNT],
+ env->gpr[HEX_REG_QEMU_HVX_CNT]);
+
+}
+
+/*
+ * sfrecipa, sfinvsqrta, vacsh have two results
+ * r0,p0=sfrecipa(r1,r2)
+ * r0,p0=sfinvsqrta(r1)
+ * r1:0,p0=vacsh(r3:2,r5:4)
+ * Since helpers can only return a single value, we have two helpers
+ * for each of these. They each contain basically the same code (copy/pasted
+ * from the arch library), but one returns the register and the other
+ * returns the predicate.
+ */
+int32_t HELPER(sfrecipa_val)(CPUHexagonState *env, int32_t RsV, int32_t RtV)
+{
+ /* int32_t PeV; Not needed to compute value */
+ int32_t RdV;
+ fHIDE(int idx;)
+ fHIDE(int adjust;)
+ fHIDE(int mant;)
+ fHIDE(int exp;)
+ if (fSF_RECIP_COMMON(RsV, RtV, RdV, adjust)) {
+ /* PeV = adjust; Not needed to compute value */
+ idx = (RtV >> 16) & 0x7f;
+ mant = (fSF_RECIP_LOOKUP(idx) << 15) | 1;
+ exp = fSF_BIAS() - (fSF_GETEXP(RtV) - fSF_BIAS()) - 1;
+ RdV = fMAKESF(fGETBIT(31, RtV), exp, mant);
+ }
+ return RdV;
+}
+
+int32_t HELPER(sfrecipa_pred)(CPUHexagonState *env, int32_t RsV, int32_t RtV)
+{
+ int32_t PeV = 0;
+ int32_t RdV;
+ fHIDE(int idx;)
+ fHIDE(int adjust;)
+ fHIDE(int mant;)
+ fHIDE(int exp;)
+ if (fSF_RECIP_COMMON(RsV, RtV, RdV, adjust)) {
+ PeV = adjust;
+ idx = (RtV >> 16) & 0x7f;
+ mant = (fSF_RECIP_LOOKUP(idx) << 15) | 1;
+ exp = fSF_BIAS() - (fSF_GETEXP(RtV) - fSF_BIAS()) - 1;
+ RdV = fMAKESF(fGETBIT(31, RtV), exp, mant);
+ }
+ return PeV;
+}
+
+int32_t HELPER(sfinvsqrta_val)(CPUHexagonState *env, int32_t RsV)
+{
+ /* int32_t PeV; Not needed for val version */
+ int32_t RdV;
+ fHIDE(int idx;)
+ fHIDE(int adjust;)
+ fHIDE(int mant;)
+ fHIDE(int exp;)
+ if (fSF_INVSQRT_COMMON(RsV, RdV, adjust)) {
+ /* PeV = adjust; Not needed for val version */
+ idx = (RsV >> 17) & 0x7f;
+ mant = (fSF_INVSQRT_LOOKUP(idx) << 15);
+ exp = fSF_BIAS() - ((fSF_GETEXP(RsV) - fSF_BIAS()) >> 1) - 1;
+ RdV = fMAKESF(fGETBIT(31, RsV), exp, mant);
+ }
+ return RdV;
+}
+
+int32_t HELPER(sfinvsqrta_pred)(CPUHexagonState *env, int32_t RsV)
+{
+ int32_t PeV = 0;
+ int32_t RdV;
+ fHIDE(int idx;)
+ fHIDE(int adjust;)
+ fHIDE(int mant;)
+ fHIDE(int exp;)
+ if (fSF_INVSQRT_COMMON(RsV, RdV, adjust)) {
+ PeV = adjust;
+ idx = (RsV >> 17) & 0x7f;
+ mant = (fSF_INVSQRT_LOOKUP(idx) << 15);
+ exp = fSF_BIAS() - ((fSF_GETEXP(RsV) - fSF_BIAS()) >> 1) - 1;
+ RdV = fMAKESF(fGETBIT(31, RsV), exp, mant);
+ }
+ return PeV;
+}
+
+int64_t HELPER(vacsh_val)(CPUHexagonState *env,
+ int64_t RxxV, int64_t RssV, int64_t RttV)
+{
+ int32_t PeV = 0;
+ fHIDE(int i;)
+ fHIDE(int xv;)
+ fHIDE(int sv;)
+ fHIDE(int tv;)
+ for (i = 0; i < 4; i++) {
+ xv = (int)fGETHALF(i, RxxV);
+ sv = (int)fGETHALF(i, RssV);
+ tv = (int)fGETHALF(i, RttV);
+ xv = xv + tv;
+ sv = sv - tv;
+ fSETBIT(i * 2, PeV, (xv > sv));
+ fSETBIT(i * 2 + 1, PeV, (xv > sv));
+ fSETHALF(i, RxxV, fSATH(fMAX(xv, sv)));
+ }
+ return RxxV;
+}
+
+int32_t HELPER(vacsh_pred)(CPUHexagonState *env,
+ int64_t RxxV, int64_t RssV, int64_t RttV)
+{
+ int32_t PeV = 0;
+ fHIDE(int i;)
+ fHIDE(int xv;)
+ fHIDE(int sv;)
+ fHIDE(int tv;)
+ for (i = 0; i < 4; i++) {
+ xv = (int)fGETHALF(i, RxxV);
+ sv = (int)fGETHALF(i, RssV);
+ tv = (int)fGETHALF(i, RttV);
+ xv = xv + tv;
+ sv = sv - tv;
+ fSETBIT(i * 2, PeV, (xv > sv));
+ fSETBIT(i * 2 + 1, PeV, (xv > sv));
+ fSETHALF(i, RxxV, fSATH(fMAX(xv, sv)));
+ }
+ return PeV;
+}
+
+/* Helpful for printing intermediate values within instructions */
+void HELPER(debug_value)(CPUHexagonState *env, int32_t value)
+{
+ HEX_DEBUG_LOG("value = 0x%x\n", value);
+}
+
+void HELPER(debug_value_i64)(CPUHexagonState *env, int64_t value)
+{
+ HEX_DEBUG_LOG("value = 0x%lx\n", value);
+}
+
+static void cancel_slot(CPUHexagonState *env, uint32_t slot)
+{
+ HEX_DEBUG_LOG("Slot %d cancelled\n", slot);
+ env->slot_cancelled |= (1 << slot);
+}
+
+/* These macros can be referenced in the generated helper functions */
+#define warn(...) /* Nothing */
+#define fatal(...) g_assert_not_reached();
+
+#define BOGUS_HELPER(tag) \
+ printf("ERROR: bogus helper: " #tag "\n")
+
+#define DEF_QEMU(TAG, SHORTCODE, HELPER, GENFN, HELPFN) HELPFN
+#include "qemu_def_generated.h"
+#undef DEF_QEMU
+
--
2.7.4
next prev parent reply other threads:[~2020-02-28 17:01 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-28 16:42 [RFC PATCH v2 00/67] Hexagon patch series Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 01/67] Hexagon Maintainers Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 02/67] Hexagon README Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 03/67] Hexagon ELF Machine Definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 04/67] Hexagon CPU Scalar Core Definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 05/67] Hexagon register names Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 06/67] Hexagon Disassembler Taylor Simpson
2020-02-28 16:43 ` Taylor Simpson [this message]
2020-02-28 16:43 ` [RFC PATCH v2 08/67] Hexagon GDB Stub Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 09/67] Hexagon architecture types Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 10/67] Hexagon instruction and packet types Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 11/67] Hexagon register fields Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 12/67] Hexagon instruction attributes Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 13/67] Hexagon register map Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 14/67] Hexagon instruction/packet decode Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 15/67] Hexagon instruction printing Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 16/67] Hexagon arch import - instruction semantics definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 17/67] Hexagon arch import - macro definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 18/67] Hexagon arch import - instruction encoding Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 19/67] Hexagon instruction class definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 20/67] Hexagon instruction utility functions Taylor Simpson
2020-04-09 18:53 ` Brian Cain
2020-04-09 20:22 ` Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 21/67] Hexagon generator phase 1 - C preprocessor for semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 22/67] Hexagon generator phase 2 - qemu_def_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 23/67] Hexagon generator phase 2 - qemu_wrap_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 24/67] Hexagon generator phase 2 - opcodes_def_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 25/67] Hexagon generator phase 2 - op_attribs_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 26/67] Hexagon generator phase 2 - op_regs_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 27/67] Hexagon generator phase 2 - printinsn-generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 28/67] Hexagon generator phase 3 - C preprocessor for decode tree Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 29/67] Hexagon generater phase 4 - Decode tree Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 30/67] Hexagon opcode data structures Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 31/67] Hexagon macros to interface with the generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 32/67] Hexagon macros referenced in instruction semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 33/67] Hexagon instruction classes Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 34/67] Hexagon TCG generation helpers - step 1 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 35/67] Hexagon TCG generation helpers - step 2 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 36/67] Hexagon TCG generation helpers - step 3 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 37/67] Hexagon TCG generation helpers - step 4 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 38/67] Hexagon TCG generation helpers - step 5 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 39/67] Hexagon TCG generation - step 01 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 40/67] Hexagon TCG generation - step 02 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 41/67] Hexagon TCG generation - step 03 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 42/67] Hexagon TCG generation - step 04 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 43/67] Hexagon TCG generation - step 05 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 44/67] Hexagon TCG generation - step 06 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 45/67] Hexagon TCG generation - step 07 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 46/67] Hexagon TCG generation - step 08 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 47/67] Hexagon TCG generation - step 09 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 48/67] Hexagon TCG generation - step 10 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 49/67] Hexagon TCG generation - step 11 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 50/67] Hexagon TCG generation - step 12 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 51/67] Hexagon translation Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 52/67] Hexagon Linux user emulation Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 53/67] Hexagon build infrastructure Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 54/67] Hexagon - Add Hexagon Vector eXtensions (HVX) to core definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 55/67] Hexagon HVX support in gdbstub Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 56/67] Hexagon HVX import instruction encodings Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 57/67] Hexagon HVX import semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 58/67] Hexagon HVX import macro definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 59/67] Hexagon HVX semantics generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 60/67] Hexagon HVX instruction decoding Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 61/67] Hexagon HVX instruction utility functions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 62/67] Hexagon HVX macros to interface with the generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 63/67] Hexagon HVX macros referenced in instruction semantics Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 64/67] Hexagon HVX helper to commit vector stores (masked and scatter/gather) Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 65/67] Hexagon HVX TCG generation Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 66/67] Hexagon HVX translation Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 67/67] Hexagon HVX build infrastructure Taylor Simpson
2020-03-25 21:13 ` [RFC PATCH v2 00/67] Hexagon patch series Taylor Simpson
2020-04-30 20:53 ` Taylor Simpson
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