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From: Taylor Simpson <tsimpson@quicinc.com>
To: qemu-devel@nongnu.org
Cc: riku.voipio@iki.fi, richard.henderson@linaro.org,
	laurent@vivier.eu, Taylor Simpson <tsimpson@quicinc.com>,
	philmd@redhat.com, aleksandar.m.mail@gmail.com
Subject: [RFC PATCH v2 38/67] Hexagon TCG generation helpers - step 5
Date: Fri, 28 Feb 2020 10:43:34 -0600	[thread overview]
Message-ID: <1582908244-304-39-git-send-email-tsimpson@quicinc.com> (raw)
In-Reply-To: <1582908244-304-1-git-send-email-tsimpson@quicinc.com>

Helpers for instructions overriden for optimization

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
 target/hexagon/genptr_helpers.h | 314 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 314 insertions(+)

diff --git a/target/hexagon/genptr_helpers.h b/target/hexagon/genptr_helpers.h
index 9917d72..e342f29 100644
--- a/target/hexagon/genptr_helpers.h
+++ b/target/hexagon/genptr_helpers.h
@@ -530,4 +530,318 @@ static inline void gen_cond_return(TCGv pred, TCGv addr)
     tcg_temp_free(zero);
 }
 
+static inline void gen_loop0r(TCGv RsV, int riV, insn_t *insn)
+{
+    TCGv tmp = tcg_temp_new();
+    fIMMEXT(riV);
+    fPCALIGN(riV);
+    /* fWRITE_LOOP_REGS0( fREAD_PC()+riV, RsV); */
+    tcg_gen_addi_tl(tmp, hex_gpr[HEX_REG_PC], riV);
+    gen_log_reg_write(HEX_REG_LC0, RsV, insn->slot, 0);
+    gen_log_reg_write(HEX_REG_SA0, tmp, insn->slot, 0);
+    fSET_LPCFG(0);
+    tcg_temp_free(tmp);
+}
+
+static inline void gen_loop1r(TCGv RsV, int riV, insn_t *insn)
+{
+    TCGv tmp = tcg_temp_new();
+    fIMMEXT(riV);
+    fPCALIGN(riV);
+    /* fWRITE_LOOP_REGS1( fREAD_PC()+riV, RsV); */
+    tcg_gen_addi_tl(tmp, hex_gpr[HEX_REG_PC], riV);
+    gen_log_reg_write(HEX_REG_LC1, RsV, insn->slot, 0);
+    gen_log_reg_write(HEX_REG_SA1, tmp, insn->slot, 0);
+    tcg_temp_free(tmp);
+}
+
+static inline void gen_compare(TCGCond cond, TCGv res, TCGv arg1, TCGv arg2)
+{
+    TCGv one = tcg_const_tl(0xff);
+    TCGv zero = tcg_const_tl(0);
+
+    tcg_gen_movcond_tl(cond, res, arg1, arg2, one, zero);
+
+    tcg_temp_free(one);
+    tcg_temp_free(zero);
+}
+
+static inline void gen_comparei(TCGCond cond, TCGv res, TCGv arg1, int arg2)
+{
+    TCGv tmp = tcg_const_tl(arg2);
+    gen_compare(cond, res, arg1, tmp);
+    tcg_temp_free(tmp);
+}
+
+static inline void gen_compare_i64(TCGCond cond, TCGv res,
+                                   TCGv_i64 arg1, TCGv_i64 arg2)
+{
+    TCGv_i64 one = tcg_const_i64(0xff);
+    TCGv_i64 zero = tcg_const_i64(0);
+    TCGv_i64 temp = tcg_temp_new_i64();
+
+    tcg_gen_movcond_i64(cond, temp, arg1, arg2, one, zero);
+    tcg_gen_extrl_i64_i32(res, temp);
+    tcg_gen_andi_tl(res, res, 0xff);
+
+    tcg_temp_free_i64(one);
+    tcg_temp_free_i64(zero);
+    tcg_temp_free_i64(temp);
+}
+
+static inline void gen_cmpnd_cmp_jmp(int pnum, TCGCond cond, bool sense,
+                                     TCGv arg1, TCGv arg2, int pc_off)
+{
+    TCGv new_pc = tcg_temp_new();
+    TCGv pred = tcg_temp_new();
+    TCGv zero = tcg_const_tl(0);
+    TCGv one = tcg_const_tl(1);
+
+    tcg_gen_addi_tl(new_pc, hex_gpr[HEX_REG_PC], pc_off);
+    gen_compare(cond, pred, arg1, arg2);
+    gen_log_pred_write(pnum, pred);
+    if (!sense) {
+        tcg_gen_xori_tl(pred, pred, 0xff);
+    }
+
+    /* If there are multiple branches in a packet, ignore the second one */
+    tcg_gen_movcond_tl(TCG_COND_NE, pred, hex_branch_taken, zero, zero, pred);
+
+    tcg_gen_movcond_tl(TCG_COND_NE, hex_next_PC, pred, zero,
+                       new_pc, hex_next_PC);
+    tcg_gen_movcond_tl(TCG_COND_NE, hex_branch_taken, pred, zero,
+                       one, hex_branch_taken);
+
+    tcg_temp_free(new_pc);
+    tcg_temp_free(pred);
+    tcg_temp_free(zero);
+    tcg_temp_free(one);
+}
+
+static inline void gen_cmpnd_cmpi_jmp(int pnum, TCGCond cond, bool sense,
+                                      TCGv arg1, int arg2, int pc_off)
+{
+    TCGv tmp = tcg_const_tl(arg2);
+    gen_cmpnd_cmp_jmp(pnum, cond, sense, arg1, tmp, pc_off);
+    tcg_temp_free(tmp);
+
+}
+
+static inline void gen_cmpnd_cmp_n1_jmp(int pnum, TCGCond cond, bool sense,
+                                        TCGv arg, int pc_off)
+{
+    gen_cmpnd_cmpi_jmp(pnum, cond, sense, arg, -1, pc_off);
+}
+
+
+static inline void gen_jump(int pc_off)
+{
+    TCGv new_pc = tcg_temp_new();
+    tcg_gen_addi_tl(new_pc, hex_gpr[HEX_REG_PC], pc_off);
+    gen_write_new_pc(new_pc);
+    tcg_temp_free(new_pc);
+}
+
+static inline void gen_cond_jumpr(TCGv pred, TCGv dst_pc)
+{
+    TCGv zero = tcg_const_tl(0);
+    TCGv one = tcg_const_tl(1);
+    TCGv new_pc = tcg_temp_new();
+
+    tcg_gen_movcond_tl(TCG_COND_EQ, new_pc, pred, zero, hex_next_PC, dst_pc);
+
+    /* If there are multiple jumps in a packet, only the first one is taken */
+    tcg_gen_movcond_tl(TCG_COND_NE, hex_next_PC, hex_branch_taken, zero,
+                       hex_next_PC, new_pc);
+    tcg_gen_movcond_tl(TCG_COND_EQ, hex_branch_taken, pred, zero,
+                       hex_branch_taken, one);
+
+    tcg_temp_free(zero);
+    tcg_temp_free(one);
+    tcg_temp_free(new_pc);
+}
+
+static inline void gen_cond_jump(TCGv pred, int pc_off)
+{
+    TCGv new_pc = tcg_temp_new();
+
+    tcg_gen_addi_tl(new_pc, hex_gpr[HEX_REG_PC], pc_off);
+    gen_cond_jumpr(pred, new_pc);
+
+    tcg_temp_free(new_pc);
+}
+
+static inline void gen_call(int pc_off)
+{
+    gen_log_reg_write(HEX_REG_LR, hex_next_PC, 4, false);
+    gen_jump(pc_off);
+}
+
+static inline void gen_callr(TCGv new_pc)
+{
+    gen_log_reg_write(HEX_REG_LR, hex_next_PC, 4, false);
+    gen_write_new_pc(new_pc);
+}
+
+static inline void gen_endloop0(void)
+{
+    TCGv lpcfg = tcg_temp_local_new();
+
+    GET_USR_FIELD(USR_LPCFG, lpcfg);
+
+    /*
+     *    if (lpcfg == 1) {
+     *        hex_new_pred_value[3] = 0xff;
+     *        hex_pred_written |= 1 << 3;
+     *    }
+     */
+    TCGLabel *label1 = gen_new_label();
+    tcg_gen_brcondi_tl(TCG_COND_NE, lpcfg, 1, label1);
+    {
+        tcg_gen_movi_tl(hex_new_pred_value[3], 0xff);
+        tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << 3);
+    }
+    gen_set_label(label1);
+
+    /*
+     *    if (lpcfg) {
+     *        SET_USR_FIELD(USR_LPCFG, lpcfg - 1);
+     *    }
+     */
+    TCGLabel *label2 = gen_new_label();
+    tcg_gen_brcondi_tl(TCG_COND_EQ, lpcfg, 0, label2);
+    {
+        tcg_gen_subi_tl(lpcfg, lpcfg, 1);
+        SET_USR_FIELD(USR_LPCFG, lpcfg);
+    }
+    gen_set_label(label2);
+
+    /*
+     *    if (hex_gpr[HEX_REG_LC0] > 1) {
+     *        hex_next_PC = hex_gpr[HEX_REG_SA0];
+     *        hex_branch_taken = 1;
+     *        hex_gpr[HEX_REG_LC0] = hex_gpr[HEX_REG_LC0] - 1;
+     *    }
+     */
+    TCGLabel *label3 = gen_new_label();
+    tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC0], 1, label3);
+    {
+        tcg_gen_mov_tl(hex_next_PC, hex_gpr[HEX_REG_SA0]);
+        tcg_gen_movi_tl(hex_branch_taken, 1);
+        TCGv lc0 = tcg_temp_local_new();
+        tcg_gen_mov_tl(lc0, hex_gpr[HEX_REG_LC0]);
+        tcg_gen_subi_tl(lc0, lc0, 1);
+        tcg_gen_mov_tl(hex_new_value[HEX_REG_LC0], lc0);
+        tcg_temp_free(lc0);
+    }
+    gen_set_label(label3);
+
+    tcg_temp_free(lpcfg);
+}
+
+static inline void gen_endloop1(void)
+{
+    /*
+     *    if (hex_gpr[HEX_REG_LC1] > 1) {
+     *        hex_next_PC = hex_gpr[HEX_REG_SA1];
+     *        hex_branch_taken = 1;
+     *        hex_gpr[HEX_REG_LC1] = hex_gpr[HEX_REG_LC1] - 1;
+     *    }
+     */
+    TCGLabel *label = gen_new_label();
+    tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC1], 1, label);
+    {
+        tcg_gen_mov_tl(hex_next_PC, hex_gpr[HEX_REG_SA1]);
+        tcg_gen_movi_tl(hex_branch_taken, 1);
+        TCGv lc1 = tcg_temp_local_new();
+        tcg_gen_mov_tl(lc1, hex_gpr[HEX_REG_LC1]);
+        tcg_gen_subi_tl(lc1, lc1, 1);
+        tcg_gen_mov_tl(hex_new_value[HEX_REG_LC1], lc1);
+        tcg_temp_free(lc1);
+    }
+    gen_set_label(label);
+}
+
+static inline void gen_ashiftr_4_4s(TCGv dst, TCGv src, int32_t shift_amt)
+{
+    tcg_gen_sari_tl(dst, src, shift_amt);
+}
+
+static inline void gen_ashiftl_4_4s(TCGv dst, TCGv src, int32_t shift_amt)
+{
+    if (shift_amt >= 64) {
+        tcg_gen_movi_tl(dst, 0);
+    } else {
+        tcg_gen_shli_tl(dst, src, shift_amt);
+    }
+}
+
+static inline void gen_cmp_jumpnv(TCGCond cond, int rnum, TCGv src, int pc_off)
+{
+    TCGv pred = tcg_temp_new();
+    tcg_gen_setcond_tl(cond, pred, hex_new_value[rnum], src);
+    gen_cond_jump(pred, pc_off);
+    tcg_temp_free(pred);
+}
+
+static inline void gen_cmpi_jumpnv(TCGCond cond, int rnum, int src, int pc_off)
+{
+    TCGv pred = tcg_temp_new();
+    tcg_gen_setcondi_tl(cond, pred, hex_new_value[rnum], src);
+    gen_cond_jump(pred, pc_off);
+    tcg_temp_free(pred);
+}
+
+static inline void gen_asl_r_r_or(TCGv RxV, TCGv RsV, TCGv RtV)
+{
+    TCGv zero = tcg_const_tl(0);
+    TCGv shift_amt = tcg_temp_new();
+    TCGv_i64 shift_amt_i64 = tcg_temp_new_i64();
+    TCGv_i64 shift_left_val_i64 = tcg_temp_new_i64();
+    TCGv shift_left_val = tcg_temp_new();
+    TCGv_i64 shift_right_val_i64 = tcg_temp_new_i64();
+    TCGv shift_right_val = tcg_temp_new();
+    TCGv or_val = tcg_temp_new();
+
+    /* Sign extend 7->32 bits */
+    tcg_gen_shli_tl(shift_amt, RtV, 32 - 7);
+    tcg_gen_sari_tl(shift_amt, shift_amt, 32 - 7);
+    tcg_gen_ext_i32_i64(shift_amt_i64, shift_amt);
+
+    tcg_gen_ext_i32_i64(shift_left_val_i64, RsV);
+    tcg_gen_shl_i64(shift_left_val_i64, shift_left_val_i64, shift_amt_i64);
+    tcg_gen_extrl_i64_i32(shift_left_val, shift_left_val_i64);
+
+    /* ((-(SHAMT)) - 1) */
+    tcg_gen_neg_i64(shift_amt_i64, shift_amt_i64);
+    tcg_gen_subi_i64(shift_amt_i64, shift_amt_i64, 1);
+
+    tcg_gen_ext_i32_i64(shift_right_val_i64, RsV);
+    tcg_gen_sar_i64(shift_right_val_i64, shift_right_val_i64, shift_amt_i64);
+    tcg_gen_sari_i64(shift_right_val_i64, shift_right_val_i64, 1);
+    tcg_gen_extrl_i64_i32(shift_right_val, shift_right_val_i64);
+
+    tcg_gen_movcond_tl(TCG_COND_GE, or_val, shift_amt, zero,
+                       shift_left_val, shift_right_val);
+    tcg_gen_or_tl(RxV, RxV, or_val);
+
+    tcg_temp_free(zero);
+    tcg_temp_free(shift_amt);
+    tcg_temp_free_i64(shift_amt_i64);
+    tcg_temp_free_i64(shift_left_val_i64);
+    tcg_temp_free(shift_left_val);
+    tcg_temp_free_i64(shift_right_val_i64);
+    tcg_temp_free(shift_right_val);
+    tcg_temp_free(or_val);
+}
+
+static inline void gen_lshiftr_4_4u(TCGv dst, TCGv src, int32_t shift_amt)
+{
+    if (shift_amt >= 64) {
+        tcg_gen_movi_tl(dst, 0);
+    } else {
+        tcg_gen_shri_tl(dst, src, shift_amt);
+    }
+}
+
 #endif
-- 
2.7.4


  parent reply	other threads:[~2020-02-28 17:31 UTC|newest]

Thread overview: 72+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-28 16:42 [RFC PATCH v2 00/67] Hexagon patch series Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 01/67] Hexagon Maintainers Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 02/67] Hexagon README Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 03/67] Hexagon ELF Machine Definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 04/67] Hexagon CPU Scalar Core Definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 05/67] Hexagon register names Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 06/67] Hexagon Disassembler Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 07/67] Hexagon CPU Scalar Core Helpers Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 08/67] Hexagon GDB Stub Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 09/67] Hexagon architecture types Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 10/67] Hexagon instruction and packet types Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 11/67] Hexagon register fields Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 12/67] Hexagon instruction attributes Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 13/67] Hexagon register map Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 14/67] Hexagon instruction/packet decode Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 15/67] Hexagon instruction printing Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 16/67] Hexagon arch import - instruction semantics definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 17/67] Hexagon arch import - macro definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 18/67] Hexagon arch import - instruction encoding Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 19/67] Hexagon instruction class definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 20/67] Hexagon instruction utility functions Taylor Simpson
2020-04-09 18:53   ` Brian Cain
2020-04-09 20:22     ` Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 21/67] Hexagon generator phase 1 - C preprocessor for semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 22/67] Hexagon generator phase 2 - qemu_def_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 23/67] Hexagon generator phase 2 - qemu_wrap_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 24/67] Hexagon generator phase 2 - opcodes_def_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 25/67] Hexagon generator phase 2 - op_attribs_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 26/67] Hexagon generator phase 2 - op_regs_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 27/67] Hexagon generator phase 2 - printinsn-generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 28/67] Hexagon generator phase 3 - C preprocessor for decode tree Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 29/67] Hexagon generater phase 4 - Decode tree Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 30/67] Hexagon opcode data structures Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 31/67] Hexagon macros to interface with the generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 32/67] Hexagon macros referenced in instruction semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 33/67] Hexagon instruction classes Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 34/67] Hexagon TCG generation helpers - step 1 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 35/67] Hexagon TCG generation helpers - step 2 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 36/67] Hexagon TCG generation helpers - step 3 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 37/67] Hexagon TCG generation helpers - step 4 Taylor Simpson
2020-02-28 16:43 ` Taylor Simpson [this message]
2020-02-28 16:43 ` [RFC PATCH v2 39/67] Hexagon TCG generation - step 01 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 40/67] Hexagon TCG generation - step 02 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 41/67] Hexagon TCG generation - step 03 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 42/67] Hexagon TCG generation - step 04 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 43/67] Hexagon TCG generation - step 05 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 44/67] Hexagon TCG generation - step 06 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 45/67] Hexagon TCG generation - step 07 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 46/67] Hexagon TCG generation - step 08 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 47/67] Hexagon TCG generation - step 09 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 48/67] Hexagon TCG generation - step 10 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 49/67] Hexagon TCG generation - step 11 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 50/67] Hexagon TCG generation - step 12 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 51/67] Hexagon translation Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 52/67] Hexagon Linux user emulation Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 53/67] Hexagon build infrastructure Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 54/67] Hexagon - Add Hexagon Vector eXtensions (HVX) to core definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 55/67] Hexagon HVX support in gdbstub Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 56/67] Hexagon HVX import instruction encodings Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 57/67] Hexagon HVX import semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 58/67] Hexagon HVX import macro definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 59/67] Hexagon HVX semantics generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 60/67] Hexagon HVX instruction decoding Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 61/67] Hexagon HVX instruction utility functions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 62/67] Hexagon HVX macros to interface with the generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 63/67] Hexagon HVX macros referenced in instruction semantics Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 64/67] Hexagon HVX helper to commit vector stores (masked and scatter/gather) Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 65/67] Hexagon HVX TCG generation Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 66/67] Hexagon HVX translation Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 67/67] Hexagon HVX build infrastructure Taylor Simpson
2020-03-25 21:13 ` [RFC PATCH v2 00/67] Hexagon patch series Taylor Simpson
2020-04-30 20:53   ` Taylor Simpson

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