* [PULL 0/5] riscv-to-apply queue
@ 2023-07-19 4:45 Alistair Francis
2023-07-19 4:45 ` [PULL 1/5] docs/system/target-riscv.rst: tidy CPU firmware section Alistair Francis
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Alistair Francis @ 2023-07-19 4:45 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Alistair Francis
The following changes since commit 361d5397355276e3007825cc17217c1e4d4320f7:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-07-17 15:49:27 +0100)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230719-1
for you to fetch changes up to 32be32509987fbe42cf5c2fd3cea3c2ad6eae179:
target/riscv: Fix LMUL check to use VLEN (2023-07-19 14:37:26 +1000)
----------------------------------------------------------------
Fourth RISC-V PR for 8.1
* Fix LMUL check to use VLEN
* Fix typo field in NUMA error_report
* check priv_ver before auto-enable zca/zcd/zcf
* Fix disas output of upper immediates
* tidy CPU firmware section
----------------------------------------------------------------
Christoph Müllner (1):
riscv/disas: Fix disas output of upper immediates
Daniel Henrique Barboza (2):
docs/system/target-riscv.rst: tidy CPU firmware section
target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf
Rob Bradford (1):
target/riscv: Fix LMUL check to use VLEN
Zhao Liu (1):
hw/riscv: Fix typo field in error_report
docs/system/target-riscv.rst | 24 ++++++++++++++++--------
disas/riscv.h | 2 ++
disas/riscv.c | 19 ++++++++++++++++---
hw/riscv/numa.c | 4 ++--
target/riscv/cpu.c | 3 ++-
target/riscv/vector_helper.c | 4 ++--
6 files changed, 40 insertions(+), 16 deletions(-)
^ permalink raw reply [flat|nested] 9+ messages in thread* [PULL 1/5] docs/system/target-riscv.rst: tidy CPU firmware section 2023-07-19 4:45 [PULL 0/5] riscv-to-apply queue Alistair Francis @ 2023-07-19 4:45 ` Alistair Francis 2023-07-19 4:45 ` [PULL 2/5] riscv/disas: Fix disas output of upper immediates Alistair Francis ` (4 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Alistair Francis @ 2023-07-19 4:45 UTC (permalink / raw) To: qemu-devel Cc: alistair23, Daniel Henrique Barboza, qemu-trivial, Alistair Francis From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> This is how the content of the "RISC-V CPU firmware" section is displayed after the html is generated: "When using the sifive_u or virt machine there are three different firmware boot options: 1. -bios default - This is the default behaviour if no -bios option is included. (...) 3. -bios <file> - Tells QEMU to load the specified file as the firmware." It's all in the same paragraph, in a numbered list, and no special formatting for the options. Tidy it a bit by adding line breaks between items and its description. Remove the numbered list. And apply formatting for the options cited in the middle of the text. Cc: qemu-trivial@nongnu.org Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230712143728.383528-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- docs/system/target-riscv.rst | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index 89a866e4f4..ba195f1518 100644 --- a/docs/system/target-riscv.rst +++ b/docs/system/target-riscv.rst @@ -76,11 +76,19 @@ RISC-V CPU firmware When using the ``sifive_u`` or ``virt`` machine there are three different firmware boot options: -1. ``-bios default`` - This is the default behaviour if no -bios option -is included. This option will load the default OpenSBI firmware automatically. -The firmware is included with the QEMU release and no user interaction is -required. All a user needs to do is specify the kernel they want to boot -with the -kernel option -2. ``-bios none`` - QEMU will not automatically load any firmware. It is up -to the user to load all the images they need. -3. ``-bios <file>`` - Tells QEMU to load the specified file as the firmware. + +* ``-bios default`` + +This is the default behaviour if no ``-bios`` option is included. This option +will load the default OpenSBI firmware automatically. The firmware is included +with the QEMU release and no user interaction is required. All a user needs to +do is specify the kernel they want to boot with the ``-kernel`` option + +* ``-bios none`` + +QEMU will not automatically load any firmware. It is up to the user to load all +the images they need. + +* ``-bios <file>`` + +Tells QEMU to load the specified file as the firmware. -- 2.40.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PULL 2/5] riscv/disas: Fix disas output of upper immediates 2023-07-19 4:45 [PULL 0/5] riscv-to-apply queue Alistair Francis 2023-07-19 4:45 ` [PULL 1/5] docs/system/target-riscv.rst: tidy CPU firmware section Alistair Francis @ 2023-07-19 4:45 ` Alistair Francis 2023-07-19 4:45 ` [PULL 3/5] target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf Alistair Francis ` (3 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Alistair Francis @ 2023-07-19 4:45 UTC (permalink / raw) To: qemu-devel; +Cc: alistair23, Christoph Müllner, Alistair Francis From: Christoph Müllner <christoph.muellner@vrull.eu> The GNU assembler produces the following output for instructions with upper immediates: 00002597 auipc a1,0x2 000024b7 lui s1,0x2 6409 lui s0,0x2 # c.lui The immediate operands of upper immediates are not shifted. However, the QEMU disassembler prints them shifted: 00002597 auipc a1,8192 000024b7 lui s1,8192 6409 lui s0,8192 # c.lui The current implementation extracts the immediate bits and shifts the by 12, so the internal representation of the immediate is the actual immediate. However, the immediates are later printed using rv_fmt_rd_imm or rv_fmt_rd_offset, which don't undo the shift. Let's fix this by using specific output formats for instructions with upper immediates, that take care of the shift. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230711075051.1531007-1-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- disas/riscv.h | 2 ++ disas/riscv.c | 19 ++++++++++++++++--- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/disas/riscv.h b/disas/riscv.h index 9cf901fc1e..8abb578b51 100644 --- a/disas/riscv.h +++ b/disas/riscv.h @@ -227,7 +227,9 @@ enum { #define rv_fmt_pred_succ "O\tp,s" #define rv_fmt_rs1_rs2 "O\t1,2" #define rv_fmt_rd_imm "O\t0,i" +#define rv_fmt_rd_uimm "O\t0,Ui" #define rv_fmt_rd_offset "O\t0,o" +#define rv_fmt_rd_uoffset "O\t0,Uo" #define rv_fmt_rd_rs1_rs2 "O\t0,1,2" #define rv_fmt_frd_rs1 "O\t3,1" #define rv_fmt_frd_rs1_rs2 "O\t3,1,2" diff --git a/disas/riscv.c b/disas/riscv.c index cd7b6e86a7..3873a69157 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -1135,8 +1135,8 @@ static const rv_comp_data rvcp_fsgnjx_q[] = { const rv_opcode_data rvi_opcode_data[] = { { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, - { "lui", rv_codec_u, rv_fmt_rd_imm, NULL, 0, 0, 0 }, - { "auipc", rv_codec_u, rv_fmt_rd_offset, NULL, 0, 0, 0 }, + { "lui", rv_codec_u, rv_fmt_rd_uimm, NULL, 0, 0, 0 }, + { "auipc", rv_codec_u, rv_fmt_rd_uoffset, NULL, 0, 0, 0 }, { "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 }, { "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 }, { "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 }, @@ -1382,7 +1382,7 @@ const rv_opcode_data rvi_opcode_data[] = { rv_op_addi }, { "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi, rv_op_addi, rv_op_addi, rvcd_imm_nz }, - { "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui, + { "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui, rv_op_lui, rv_op_lui, rvcd_imm_nz }, { "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli, rv_op_srli, rv_op_srli, rvcd_imm_nz }, @@ -4694,6 +4694,19 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) dec->pc + dec->imm); append(buf, tmp, buflen); break; + case 'U': + fmt++; + snprintf(tmp, sizeof(tmp), "%d", dec->imm >> 12); + append(buf, tmp, buflen); + if (*fmt == 'o') { + while (strlen(buf) < tab * 2) { + append(buf, " ", buflen); + } + snprintf(tmp, sizeof(tmp), "# 0x%" PRIx64, + dec->pc + dec->imm); + append(buf, tmp, buflen); + } + break; case 'c': { const char *name = csr_name(dec->imm & 0xfff); if (name) { -- 2.40.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PULL 3/5] target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf 2023-07-19 4:45 [PULL 0/5] riscv-to-apply queue Alistair Francis 2023-07-19 4:45 ` [PULL 1/5] docs/system/target-riscv.rst: tidy CPU firmware section Alistair Francis 2023-07-19 4:45 ` [PULL 2/5] riscv/disas: Fix disas output of upper immediates Alistair Francis @ 2023-07-19 4:45 ` Alistair Francis 2023-07-19 4:45 ` [PULL 4/5] hw/riscv: Fix typo field in error_report Alistair Francis ` (2 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Alistair Francis @ 2023-07-19 4:45 UTC (permalink / raw) To: qemu-devel Cc: alistair23, Daniel Henrique Barboza, Conor Dooley, Alistair Francis, Weiwei Li, Conor Dooley From: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Commit bd30559568 made changes in how we're checking and disabling extensions based on env->priv_ver. One of the changes was to move the extension disablement code to the end of realize(), being able to disable extensions after we've auto-enabled some of them. An unfortunate side effect of this change started to happen with CPUs that has an older priv version, like sifive-u54. Starting on commit 2288a5ce43e5 we're auto-enabling zca, zcd and zcf if RVC is enabled, but these extensions are priv version 1.12.0. When running a cpu that has an older priv ver (like sifive-u54) the user is spammed with warnings like these: qemu-system-riscv64: warning: disabling zca extension for hart 0x0000000000000000 because privilege spec version does not match qemu-system-riscv64: warning: disabling zcd extension for hart 0x0000000000000000 because privilege spec version does not match The warnings are part of the code that disables the extension, but in this case we're throwing user warnings for stuff that we enabled on our own, without user intervention. Users are left wondering what they did wrong. A quick 8.1 fix for this nuisance is to check the CPU priv spec before auto-enabling zca/zcd/zcf. A more appropriate fix will include a more robust framework that will account for both priv_ver and user choice when auto-enabling/disabling extensions, but for 8.1 we'll make it do with this simple check. It's also worth noticing that this is the only case where we're auto-enabling extensions based on a criteria (in this case RVC) that doesn't match the priv spec of the extensions we're enabling. There's no need for more 8.1 band-aids. Cc: Conor Dooley <conor@kernel.org> Fixes: 2288a5ce43e5 ("target/riscv: add cfg properties for Zc* extension") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Tested-by: Conor Dooley <conor.dooley@microchip.com> Message-Id: <20230717154141.60898-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9339c0241d..6b93b04453 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1225,7 +1225,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) } } - if (riscv_has_ext(env, RVC)) { + /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ + if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { cpu->cfg.ext_zca = true; if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { cpu->cfg.ext_zcf = true; -- 2.40.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PULL 4/5] hw/riscv: Fix typo field in error_report 2023-07-19 4:45 [PULL 0/5] riscv-to-apply queue Alistair Francis ` (2 preceding siblings ...) 2023-07-19 4:45 ` [PULL 3/5] target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf Alistair Francis @ 2023-07-19 4:45 ` Alistair Francis 2023-07-19 4:45 ` [PULL 5/5] target/riscv: Fix LMUL check to use VLEN Alistair Francis 2023-07-19 19:30 ` [PULL 0/5] riscv-to-apply queue Peter Maydell 5 siblings, 0 replies; 9+ messages in thread From: Alistair Francis @ 2023-07-19 4:45 UTC (permalink / raw) To: qemu-devel; +Cc: alistair23, Zhao Liu, Alistair Francis From: Zhao Liu <zhao1.liu@intel.com> "smp.cpus" means the number of online CPUs and "smp.max_cpus" means the total number of CPUs. riscv_numa_get_default_cpu_node_id() checks "smp.cpus" and the "available CPUs" description in the next error message also indicates online CPUs. So report "smp.cpus" in error_report() instand of "smp.max_cpus". Since "smp.cpus" is "unsigned int", use "%u". Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230718080712.503333-1-zhao1.liu@linux.intel.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- hw/riscv/numa.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c index e0414d5b1b..d319aefb45 100644 --- a/hw/riscv/numa.c +++ b/hw/riscv/numa.c @@ -209,8 +209,8 @@ int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx) if (ms->numa_state->num_nodes > ms->smp.cpus) { error_report("Number of NUMA nodes (%d)" - " cannot exceed the number of available CPUs (%d).", - ms->numa_state->num_nodes, ms->smp.max_cpus); + " cannot exceed the number of available CPUs (%u).", + ms->numa_state->num_nodes, ms->smp.cpus); exit(EXIT_FAILURE); } if (ms->numa_state->num_nodes) { -- 2.40.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PULL 5/5] target/riscv: Fix LMUL check to use VLEN 2023-07-19 4:45 [PULL 0/5] riscv-to-apply queue Alistair Francis ` (3 preceding siblings ...) 2023-07-19 4:45 ` [PULL 4/5] hw/riscv: Fix typo field in error_report Alistair Francis @ 2023-07-19 4:45 ` Alistair Francis 2023-07-19 19:30 ` [PULL 0/5] riscv-to-apply queue Peter Maydell 5 siblings, 0 replies; 9+ messages in thread From: Alistair Francis @ 2023-07-19 4:45 UTC (permalink / raw) To: qemu-devel; +Cc: alistair23, Rob Bradford, Weiwei Li, Alistair Francis From: Rob Bradford <rbradford@rivosinc.com> The previous check was failing with: VLEN=128 ELEN = 64 SEW = 16 and LMUL = 1/8 which is a valid combination. Fix the check to allow valid combinations when VLEN is a multiple of ELEN. From the specification: "In general, the requirement is to support LMUL ≥ SEWMIN/ELEN, where SEWMIN is the narrowest supported SEW value and ELEN is the widest supported SEW value. In the standard extensions, SEWMIN=8. For standard vector extensions with ELEN=32, fractional LMULs of 1/2 and 1/4 must be supported. For standard vector extensions with ELEN=64, fractional LMULs of 1/2, 1/4, and 1/8 must be supported." Elsewhere in the specification it makes clear that VLEN>=ELEN. From inspection this new check allows: VLEN=ELEN=64 1/2, 1/4, 1/8 for SEW >=8 VLEN=ELEN=32 1/2, 1/4 for SEW >=8 Fixes: d9b7609a1fb2 ("target/riscv: rvv-1.0: configure instructions") Signed-off-by: Rob Bradford <rbradford@rivosinc.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-Id: <20230718131316.12283-2-rbradford@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/vector_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index cfacf2ebba..4d06754826 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -43,9 +43,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, xlen - 1 - R_VTYPE_RESERVED_SHIFT); if (lmul & 4) { - /* Fractional LMUL. */ + /* Fractional LMUL - check LMUL * VLEN >= SEW */ if (lmul == 4 || - cpu->cfg.elen >> (8 - lmul) < sew) { + cpu->cfg.vlen >> (8 - lmul) < sew) { vill = true; } } -- 2.40.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PULL 0/5] riscv-to-apply queue 2023-07-19 4:45 [PULL 0/5] riscv-to-apply queue Alistair Francis ` (4 preceding siblings ...) 2023-07-19 4:45 ` [PULL 5/5] target/riscv: Fix LMUL check to use VLEN Alistair Francis @ 2023-07-19 19:30 ` Peter Maydell 5 siblings, 0 replies; 9+ messages in thread From: Peter Maydell @ 2023-07-19 19:30 UTC (permalink / raw) To: Alistair Francis; +Cc: qemu-devel, Alistair Francis On Wed, 19 Jul 2023 at 05:46, Alistair Francis <alistair23@gmail.com> wrote: > > The following changes since commit 361d5397355276e3007825cc17217c1e4d4320f7: > > Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-07-17 15:49:27 +0100) > > are available in the Git repository at: > > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230719-1 > > for you to fetch changes up to 32be32509987fbe42cf5c2fd3cea3c2ad6eae179: > > target/riscv: Fix LMUL check to use VLEN (2023-07-19 14:37:26 +1000) > > ---------------------------------------------------------------- > Fourth RISC-V PR for 8.1 > > * Fix LMUL check to use VLEN > * Fix typo field in NUMA error_report > * check priv_ver before auto-enable zca/zcd/zcf > * Fix disas output of upper immediates > * tidy CPU firmware section > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.1 for any user-visible changes. -- PMM ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PULL 0/5] riscv-to-apply queue
@ 2020-07-22 16:48 Alistair Francis
2020-07-24 9:51 ` Peter Maydell
0 siblings, 1 reply; 9+ messages in thread
From: Alistair Francis @ 2020-07-22 16:48 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis
The following changes since commit 3cbc8970f55c87cb58699b6dc8fe42998bc79dc0:
Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2020-07-21' into staging (2020-07-22 09:13:46 +0100)
are available in the Git repository at:
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200722-1
for you to fetch changes up to 8ba26b0b2b00dd5849a6c0981e358dc7a7cc315d:
target/riscv: Fix the range of pmpcfg of CSR funcion table (2020-07-22 09:41:36 -0700)
----------------------------------------------------------------
This PR contains a few RISC-V fixes.
The main fix is the correction of the goldfish RTC time. On top of that
some small fixes to the recently added vector extensions have been added
(including an assert that fixed a coverity report). There is a change in
the SiFive E debug memory size to match hardware. Finally there is a fix
for PMP accesses.
----------------------------------------------------------------
Bin Meng (1):
hw/riscv: sifive_e: Correct debug block size
Jessica Clarke (1):
goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH
LIU Zhiwei (2):
target/riscv: Quiet Coverity complains about vamo*
target/riscv: fix vector index load/store constraints
Zong Li (1):
target/riscv: Fix the range of pmpcfg of CSR funcion table
include/hw/rtc/goldfish_rtc.h | 1 +
hw/riscv/sifive_e.c | 2 +-
hw/rtc/goldfish_rtc.c | 17 ++++++++++++++---
target/riscv/csr.c | 2 +-
target/riscv/insn_trans/trans_rvv.inc.c | 11 ++++++++++-
5 files changed, 27 insertions(+), 6 deletions(-)
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PULL 0/5] riscv-to-apply queue 2020-07-22 16:48 Alistair Francis @ 2020-07-24 9:51 ` Peter Maydell 0 siblings, 0 replies; 9+ messages in thread From: Peter Maydell @ 2020-07-24 9:51 UTC (permalink / raw) To: Alistair Francis; +Cc: QEMU Developers On Wed, 22 Jul 2020 at 18:00, Alistair Francis <alistair.francis@wdc.com> wrote: > > The following changes since commit 3cbc8970f55c87cb58699b6dc8fe42998bc79dc0: > > Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2020-07-21' into staging (2020-07-22 09:13:46 +0100) > > are available in the Git repository at: > > git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200722-1 > > for you to fetch changes up to 8ba26b0b2b00dd5849a6c0981e358dc7a7cc315d: > > target/riscv: Fix the range of pmpcfg of CSR funcion table (2020-07-22 09:41:36 -0700) > > ---------------------------------------------------------------- > This PR contains a few RISC-V fixes. > > The main fix is the correction of the goldfish RTC time. On top of that > some small fixes to the recently added vector extensions have been added > (including an assert that fixed a coverity report). There is a change in > the SiFive E debug memory size to match hardware. Finally there is a fix > for PMP accesses. Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1 for any user-visible changes. -- PMM ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-07-19 19:31 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-07-19 4:45 [PULL 0/5] riscv-to-apply queue Alistair Francis 2023-07-19 4:45 ` [PULL 1/5] docs/system/target-riscv.rst: tidy CPU firmware section Alistair Francis 2023-07-19 4:45 ` [PULL 2/5] riscv/disas: Fix disas output of upper immediates Alistair Francis 2023-07-19 4:45 ` [PULL 3/5] target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf Alistair Francis 2023-07-19 4:45 ` [PULL 4/5] hw/riscv: Fix typo field in error_report Alistair Francis 2023-07-19 4:45 ` [PULL 5/5] target/riscv: Fix LMUL check to use VLEN Alistair Francis 2023-07-19 19:30 ` [PULL 0/5] riscv-to-apply queue Peter Maydell -- strict thread matches above, loose matches on Subject: below -- 2020-07-22 16:48 Alistair Francis 2020-07-24 9:51 ` Peter Maydell
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).