From: Yakir Yang <ykk@rock-chips.com> To: Heiko Stuebner <heiko@sntech.de>, Thierry Reding <treding@nvidia.com>, Jingoo Han <jingoohan1@gmail.com>, Fabio Estevam <fabio.estevam@freescale.com>, Inki Dae <inki.dae@samsung.com>, joe@perches.com, Russell King <rmk+kernel@arm.linux.org.uk> Cc: djkurtz@google.com, dianders@google.com, seanpaul@google.com, Takashi Iwai <tiwai@suse.de>, ajaynumb@gmail.com, Andrzej Hajda <a.hajda@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Philipp Zabel <p.zabel@pengutronix.de>, David Airlie <airlied@linux.ie>, Gustavo Padovan <gustavo.padovan@collabora.co.uk>, Vincent Palatin <vpalatin@chromium.org>, Mark Yao <mark.yao@rock-chips.com>, Andy Yan <andy.yan@rock-chips.com>, Kumar Gala <galak@codeaurora.org>, Ian Campbell <ijc+devicetree@hellion.org.uk>, Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>, Kishon Vijay Abraham I <kishon@ti.com>, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Yakir Yang <ykk@rock-chips.com> Subject: [PATCH v3 05/14] drm: bridge/analogix_dp: fix link_rate & lane_count bug Date: Wed, 19 Aug 2015 09:50:24 -0500 [thread overview] Message-ID: <1439995824-18312-1-git-send-email-ykk@rock-chips.com> (raw) In-Reply-To: <1439995728-18046-1-git-send-email-ykk@rock-chips.com> link_rate and lane_count already configed in analogix_dp_set_link_train(), so we don't need to config those repeatly after training finished, just remove them out. Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}. Signed-off-by: Yakir Yang <ykk@rock-chips.com> --- Changes in v3: - Take Thierry Reding suggest, link_rate and lane_count shouldn't config to the DT property value directly, but we can take those as hardware limite. For example, RK3288 only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would like "link-rate = 0x0a" "lane-count = 4". Changes in v2: None drivers/gpu/drm/bridge/analogix_dp_core.c | 16 ++++++++-------- drivers/gpu/drm/bridge/analogix_dp_core.h | 9 +++++---- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix_dp_core.c index 480cc13..1778e0a 100644 --- a/drivers/gpu/drm/bridge/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix_dp_core.c @@ -635,6 +635,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, /* * For DP rev.1.1, Maximum link rate of Main Link lanes * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps + * For DP rev.1.2, Maximum link rate of Main Link lanes + * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps */ analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); *bandwidth = data; @@ -668,7 +670,8 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp, analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && - (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { + (dp->link_train.link_rate != LINK_RATE_2_70GBPS) && + (dp->link_train.link_rate != LINK_RATE_5_40GBPS)) { dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", dp->link_train.link_rate); dp->link_train.link_rate = LINK_RATE_1_62GBPS; @@ -901,8 +904,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp) return; } - ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count, - dp->video_info->link_rate); + ret = analogix_dp_set_link_train(dp, dp->video_info->max_lane_count, + dp->video_info->max_link_rate); if (ret) { dev_err(dp->dev, "unable to do link train\n"); return; @@ -912,9 +915,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp) analogix_dp_enable_rx_to_enhanced_mode(dp, 1); analogix_dp_enable_enhanced_mode(dp, 1); - analogix_dp_set_lane_count(dp, dp->video_info->lane_count); - analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate); - analogix_dp_init_video(dp); ret = analogix_dp_config_video(dp); if (ret) @@ -1198,13 +1198,13 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev) } if (of_property_read_u32(dp_node, "analogix,link-rate", - &dp_video_config->link_rate)) { + &dp_video_config->max_link_rate)) { dev_err(dev, "failed to get link-rate\n"); return ERR_PTR(-EINVAL); } if (of_property_read_u32(dp_node, "analogix,lane-count", - &dp_video_config->lane_count)) { + &dp_video_config->max_lane_count)) { dev_err(dev, "failed to get lane-count\n"); return ERR_PTR(-EINVAL); } diff --git a/drivers/gpu/drm/bridge/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix_dp_core.h index 2cefde9..941b34f 100644 --- a/drivers/gpu/drm/bridge/analogix_dp_core.h +++ b/drivers/gpu/drm/bridge/analogix_dp_core.h @@ -21,8 +21,9 @@ #define MAX_EQ_LOOP 5 enum link_rate_type { - LINK_RATE_1_62GBPS = 0x06, - LINK_RATE_2_70GBPS = 0x0a + LINK_RATE_1_62GBPS = DP_LINK_BW_1_62, + LINK_RATE_2_70GBPS = DP_LINK_BW_2_7, + LINK_RATE_5_40GBPS = DP_LINK_BW_5_4, }; enum link_lane_count_type { @@ -128,8 +129,8 @@ struct video_info { enum color_coefficient ycbcr_coeff; enum color_depth color_depth; - enum link_rate_type link_rate; - enum link_lane_count_type lane_count; + enum link_rate_type max_link_rate; + enum link_lane_count_type max_lane_count; }; struct link_train { -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: ykk@rock-chips.com (Yakir Yang) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 05/14] drm: bridge/analogix_dp: fix link_rate & lane_count bug Date: Wed, 19 Aug 2015 09:50:24 -0500 [thread overview] Message-ID: <1439995824-18312-1-git-send-email-ykk@rock-chips.com> (raw) In-Reply-To: <1439995728-18046-1-git-send-email-ykk@rock-chips.com> link_rate and lane_count already configed in analogix_dp_set_link_train(), so we don't need to config those repeatly after training finished, just remove them out. Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}. Signed-off-by: Yakir Yang <ykk@rock-chips.com> --- Changes in v3: - Take Thierry Reding suggest, link_rate and lane_count shouldn't config to the DT property value directly, but we can take those as hardware limite. For example, RK3288 only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would like "link-rate = 0x0a" "lane-count = 4". Changes in v2: None drivers/gpu/drm/bridge/analogix_dp_core.c | 16 ++++++++-------- drivers/gpu/drm/bridge/analogix_dp_core.h | 9 +++++---- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix_dp_core.c index 480cc13..1778e0a 100644 --- a/drivers/gpu/drm/bridge/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix_dp_core.c @@ -635,6 +635,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, /* * For DP rev.1.1, Maximum link rate of Main Link lanes * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps + * For DP rev.1.2, Maximum link rate of Main Link lanes + * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps */ analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); *bandwidth = data; @@ -668,7 +670,8 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp, analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && - (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { + (dp->link_train.link_rate != LINK_RATE_2_70GBPS) && + (dp->link_train.link_rate != LINK_RATE_5_40GBPS)) { dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", dp->link_train.link_rate); dp->link_train.link_rate = LINK_RATE_1_62GBPS; @@ -901,8 +904,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp) return; } - ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count, - dp->video_info->link_rate); + ret = analogix_dp_set_link_train(dp, dp->video_info->max_lane_count, + dp->video_info->max_link_rate); if (ret) { dev_err(dp->dev, "unable to do link train\n"); return; @@ -912,9 +915,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp) analogix_dp_enable_rx_to_enhanced_mode(dp, 1); analogix_dp_enable_enhanced_mode(dp, 1); - analogix_dp_set_lane_count(dp, dp->video_info->lane_count); - analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate); - analogix_dp_init_video(dp); ret = analogix_dp_config_video(dp); if (ret) @@ -1198,13 +1198,13 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev) } if (of_property_read_u32(dp_node, "analogix,link-rate", - &dp_video_config->link_rate)) { + &dp_video_config->max_link_rate)) { dev_err(dev, "failed to get link-rate\n"); return ERR_PTR(-EINVAL); } if (of_property_read_u32(dp_node, "analogix,lane-count", - &dp_video_config->lane_count)) { + &dp_video_config->max_lane_count)) { dev_err(dev, "failed to get lane-count\n"); return ERR_PTR(-EINVAL); } diff --git a/drivers/gpu/drm/bridge/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix_dp_core.h index 2cefde9..941b34f 100644 --- a/drivers/gpu/drm/bridge/analogix_dp_core.h +++ b/drivers/gpu/drm/bridge/analogix_dp_core.h @@ -21,8 +21,9 @@ #define MAX_EQ_LOOP 5 enum link_rate_type { - LINK_RATE_1_62GBPS = 0x06, - LINK_RATE_2_70GBPS = 0x0a + LINK_RATE_1_62GBPS = DP_LINK_BW_1_62, + LINK_RATE_2_70GBPS = DP_LINK_BW_2_7, + LINK_RATE_5_40GBPS = DP_LINK_BW_5_4, }; enum link_lane_count_type { @@ -128,8 +129,8 @@ struct video_info { enum color_coefficient ycbcr_coeff; enum color_depth color_depth; - enum link_rate_type link_rate; - enum link_lane_count_type lane_count; + enum link_rate_type max_link_rate; + enum link_lane_count_type max_lane_count; }; struct link_train { -- 1.9.1
next prev parent reply other threads:[~2015-08-19 14:50 UTC|newest] Thread overview: 187+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-08-19 14:48 [PATCH v3 0/14] Add Analogix Core Display Port Driver Yakir Yang 2015-08-19 14:48 ` Yakir Yang 2015-08-19 14:49 ` [PATCH v3 01/14] drm: exynos/dp: fix code style Yakir Yang 2015-08-19 14:49 ` Yakir Yang 2015-08-19 14:49 ` [PATCH v3 02/14] drm: exynos/dp: convert to drm bridge mode Yakir Yang 2015-08-19 14:49 ` Yakir Yang 2015-08-19 14:50 ` [PATCH v3 03/14] drm: bridge: analogix_dp: split exynos dp driver to bridge dir Yakir Yang 2015-08-19 14:50 ` Yakir Yang 2015-08-19 14:50 ` [PATCH v3 04/14] drm: bridge/analogix_dp: dynamic parse sync_pol & interlace & colorimetry Yakir Yang 2015-08-19 14:50 ` Yakir Yang 2015-08-19 14:50 ` Yakir Yang [this message] 2015-08-19 14:50 ` [PATCH v3 05/14] drm: bridge/analogix_dp: fix link_rate & lane_count bug Yakir Yang 2015-08-20 7:22 ` Jingoo Han 2015-08-20 7:22 ` Jingoo Han 2015-08-20 7:22 ` Jingoo Han 2015-08-20 8:04 ` Yakir Yang 2015-08-20 8:04 ` Yakir Yang 2015-08-20 8:04 ` Yakir Yang 2015-08-19 14:50 ` [PATCH v3 06/14] Documentation: drm/bridge: add document for analogix_dp Yakir Yang 2015-08-19 14:50 ` Yakir Yang 2015-08-23 23:23 ` Rob Herring 2015-08-23 23:23 ` Rob Herring 2015-08-23 23:23 ` Rob Herring 2015-08-24 0:43 ` Krzysztof Kozlowski 2015-08-24 0:43 ` Krzysztof Kozlowski 2015-08-24 0:43 ` Krzysztof Kozlowski 2015-08-24 2:42 ` Yakir Yang 2015-08-24 2:42 ` Yakir Yang 2015-08-24 4:20 ` Krzysztof Kozlowski 2015-08-24 4:20 ` Krzysztof Kozlowski 2015-08-24 4:20 ` Krzysztof Kozlowski 2015-08-24 12:48 ` Yakir Yang 2015-08-24 12:48 ` Yakir Yang 2015-08-24 12:48 ` Yakir Yang 2015-08-24 13:03 ` Heiko Stuebner 2015-08-24 13:03 ` Heiko Stuebner 2015-08-24 13:03 ` Heiko Stuebner 2015-08-25 1:37 ` Yakir Yang 2015-08-25 1:37 ` Yakir Yang 2015-08-25 1:37 ` Yakir Yang 2015-08-24 23:49 ` Krzysztof Kozlowski 2015-08-24 23:49 ` Krzysztof Kozlowski 2015-08-24 23:49 ` Krzysztof Kozlowski [not found] ` <55DBAD90.3040901-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> 2015-08-25 1:32 ` Yakir Yang 2015-08-25 1:33 ` Yakir Yang 2015-08-25 1:33 ` Yakir Yang 2015-08-25 1:33 ` Yakir Yang 2015-08-25 1:35 ` Krzysztof Kozlowski 2015-08-25 1:35 ` Krzysztof Kozlowski 2015-08-25 1:35 ` Krzysztof Kozlowski 2015-08-24 7:40 ` Jingoo Han 2015-08-24 7:40 ` Jingoo Han 2015-08-24 7:40 ` Jingoo Han 2015-08-24 12:55 ` Yakir Yang 2015-08-24 12:55 ` Yakir Yang 2015-08-24 12:55 ` Yakir Yang 2015-08-24 2:19 ` Yakir Yang 2015-08-24 2:19 ` Yakir Yang 2015-08-24 12:57 ` Russell King - ARM Linux 2015-08-24 12:57 ` Russell King - ARM Linux 2015-08-24 12:57 ` Russell King - ARM Linux 2015-08-24 14:48 ` Rob Herring 2015-08-24 14:48 ` Rob Herring 2015-08-24 14:48 ` Rob Herring 2015-08-24 16:16 ` Heiko Stuebner 2015-08-24 16:16 ` Heiko Stuebner 2015-08-24 16:16 ` Heiko Stuebner 2015-08-25 1:21 ` Yakir Yang 2015-08-25 1:21 ` Yakir Yang 2015-08-25 1:21 ` Yakir Yang 2015-08-25 9:12 ` Thierry Reding 2015-08-25 9:12 ` Thierry Reding 2015-08-25 9:12 ` Thierry Reding 2015-08-25 9:29 ` Russell King - ARM Linux 2015-08-25 9:29 ` Russell King - ARM Linux 2015-08-25 9:29 ` Russell King - ARM Linux 2015-08-25 10:40 ` Thierry Reding 2015-08-25 10:40 ` Thierry Reding 2015-08-25 10:40 ` Thierry Reding 2015-08-25 10:52 ` Russell King - ARM Linux 2015-08-25 10:52 ` Russell King - ARM Linux 2015-08-25 10:52 ` Russell King - ARM Linux 2015-08-25 9:41 ` Yakir Yang 2015-08-25 9:41 ` Yakir Yang 2015-08-25 10:06 ` Thierry Reding 2015-08-25 10:06 ` Thierry Reding 2015-08-25 10:06 ` Thierry Reding 2015-08-25 14:02 ` Yakir Yang 2015-08-25 14:02 ` Yakir Yang 2015-08-25 9:15 ` Thierry Reding 2015-08-25 9:15 ` Thierry Reding 2015-08-25 9:15 ` Thierry Reding 2015-08-25 9:37 ` Yakir Yang 2015-08-25 9:37 ` Yakir Yang 2015-08-25 13:27 ` Rob Herring 2015-08-25 13:27 ` Rob Herring 2015-08-25 13:27 ` Rob Herring 2015-08-25 13:48 ` Yakir Yang 2015-08-25 14:16 ` Thierry Reding 2015-08-25 14:16 ` Thierry Reding 2015-08-25 14:16 ` Thierry Reding 2015-08-25 14:23 ` Yakir Yang 2015-08-25 14:23 ` Yakir Yang 2015-08-25 9:58 ` Thierry Reding 2015-08-25 9:58 ` Thierry Reding 2015-08-25 9:58 ` Thierry Reding 2015-08-25 14:03 ` Yakir Yang 2015-08-25 14:03 ` Yakir Yang 2015-08-25 14:21 ` Thierry Reding 2015-08-25 14:21 ` Thierry Reding 2015-08-25 14:21 ` Thierry Reding 2015-08-25 15:57 ` Russell King - ARM Linux 2015-08-25 15:57 ` Russell King - ARM Linux 2015-08-25 15:57 ` Russell King - ARM Linux 2015-08-19 14:50 ` [PATCH v3 07/14] drm: rockchip/dp: add rockchip platform dp driver Yakir Yang 2015-08-19 14:50 ` Yakir Yang 2015-08-19 14:50 ` Yakir Yang 2015-08-19 14:51 ` [PATCH v3 08/14] phy: Add driver for rockchip Display Port PHY Yakir Yang 2015-08-19 14:51 ` Yakir Yang 2015-08-20 4:40 ` Kishon Vijay Abraham I 2015-08-20 4:40 ` Kishon Vijay Abraham I 2015-08-20 4:40 ` Kishon Vijay Abraham I 2015-08-20 6:56 ` Yakir Yang 2015-08-20 7:01 ` Yakir Yang 2015-08-19 14:51 ` [PATCH v3 09/14] drm: bridge/analogix_dp: add platform device type support Yakir Yang 2015-08-19 14:51 ` Yakir Yang 2015-08-19 14:51 ` Yakir Yang 2015-08-19 14:51 ` [PATCH v3 10/14] drm: bridge: analogix_dp: add some rk3288 special registers setting Yakir Yang 2015-08-19 14:51 ` Yakir Yang 2015-08-19 14:51 ` [PATCH v3 11/14] drm: bridge: analogix_dp: try force hpd after plug in lookup failed Yakir Yang 2015-08-19 14:51 ` Yakir Yang 2015-08-19 14:52 ` [PATCH v3 12/14] drm: bridge/analogix_dp: expand the delay time for hpd detect Yakir Yang 2015-08-19 14:52 ` Yakir Yang 2015-08-19 14:52 ` Yakir Yang 2015-08-20 6:11 ` Jingoo Han 2015-08-20 6:11 ` Jingoo Han 2015-08-20 6:11 ` Jingoo Han 2015-08-20 8:02 ` Yakir Yang 2015-08-20 8:02 ` Yakir Yang 2015-08-20 8:02 ` Yakir Yang 2015-08-19 14:52 ` [PATCH v3 13/14] drm: bridge/analogix_dp: move hpd detect to connector detect function Yakir Yang 2015-08-19 14:52 ` Yakir Yang 2015-08-20 7:49 ` Jingoo Han 2015-08-20 7:49 ` Jingoo Han 2015-08-20 7:49 ` Jingoo Han 2015-08-20 8:18 ` Yakir Yang 2015-08-20 8:18 ` Yakir Yang 2015-08-20 8:18 ` Yakir Yang 2015-08-19 14:52 ` [PATCH v3 14/14] drm: bridge/analogix_dp: add edid modes parse in get_modes method Yakir Yang 2015-08-19 14:52 ` Yakir Yang 2015-08-19 23:54 ` [PATCH v3 0/14] Add Analogix Core Display Port Driver Dave Airlie 2015-08-19 23:54 ` Dave Airlie 2015-08-19 23:54 ` Dave Airlie 2015-08-20 1:02 ` Yakir Yang 2015-08-20 1:02 ` Yakir Yang 2015-08-20 1:02 ` Yakir Yang 2015-08-20 4:29 ` Archit Taneja 2015-08-20 4:29 ` Archit Taneja 2015-08-20 4:29 ` Archit Taneja 2015-08-20 5:54 ` Jingoo Han 2015-08-20 5:54 ` Jingoo Han 2015-08-20 5:54 ` Jingoo Han 2015-08-20 6:23 ` Yakir Yang 2015-08-20 6:23 ` Yakir Yang 2015-08-20 6:23 ` Yakir Yang 2015-08-20 6:55 ` Jingoo Han 2015-08-20 6:55 ` Jingoo Han 2015-08-20 6:55 ` Jingoo Han 2015-08-20 8:03 ` Yakir Yang 2015-08-20 8:03 ` Yakir Yang 2015-08-20 8:03 ` Yakir Yang 2015-08-21 8:20 ` Jingoo Han 2015-08-21 8:20 ` Jingoo Han 2015-08-21 8:20 ` Jingoo Han 2015-08-21 10:01 ` Yakir Yang 2015-08-21 11:24 ` Jingoo Han 2015-08-21 13:16 ` Thierry Reding 2015-08-21 13:16 ` Thierry Reding 2015-08-21 13:16 ` Thierry Reding 2015-08-22 10:13 ` Yakir Yang 2015-08-30 12:16 ` Romain Perier 2015-08-30 12:16 ` Romain Perier 2015-08-30 12:16 ` Romain Perier 2015-08-31 2:40 ` Yakir Yang 2015-08-31 2:40 ` Yakir Yang 2015-08-31 2:40 ` Yakir Yang 2015-08-22 9:42 ` Yakir Yang
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