From: Douglas Anderson <dianders@chromium.org> To: ulf.hansson@linaro.org, kishon@ti.com, Heiko Stuebner <heiko@sntech.de>, robh+dt@kernel.org Cc: shawn.lin@rock-chips.com, xzy.xu@rock-chips.com, briannorris@chromium.org, adrian.hunter@intel.com, linux-rockchip@lists.infradead.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Douglas Anderson <dianders@chromium.org>, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/11] Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs Date: Tue, 7 Jun 2016 15:44:36 -0700 [thread overview] Message-ID: <1465339484-969-4-git-send-email-dianders@chromium.org> (raw) In-Reply-To: <1465339484-969-1-git-send-email-dianders@chromium.org> As can be seen in Arasan's datasheet [1] there are several "corecfg" settings in their SDHCI IP Block that are supposed to be controlled by software. Although the datasheet referenced is a bit vague about how to access corecfg, in Figure 5 you can see that for Arasan's PHY (a separate component than their SDHCI component) they describe the "phyctrl" registers as being "FROM SOC CTL REG", implying that it's up to the licensee of the Arasan IP block to implement these registers. It seems sane to assume that the "corecfg" registers in their SDHCI IP block works in a similar way for all licensees of the IP Block. Device tree has a model that allows a device to get a reference to random registers located elsewhere in the SoC: sysctl. Let's leverage this model and allow adding a sysctl reference to access the control registers for the Arasan SDHCI PHYs. Having a reference to the control registers doesn't do much for us on its own since the Arasan spec doesn't specify how these corecfg values are laid out in memory. In the SDHCI driver we'll need a map detailing where each corecfg can be found in each implementation. This map can be found using the primary compatible string of the SDHCI device. In that spirit, document that existing rk3399 device trees already have a specific compatible string, though up to now they've always been relying on the driver supporting the generic. Note that since existing devices seem to work fairly well as-is, we'll list the syscon reference as "optional", but it's likely that we'll run into much fewer problems if we can actually set the proper values in the syscon, so it is strongly suggested that any SoCs where we have a map to set the corecfg also include a reference to the syscon. [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf Signed-off-by: Douglas Anderson <dianders@chromium.org> --- .../devicetree/bindings/mmc/arasan,sdhci.txt | 27 ++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index 31b35c3a5e47..b67e623ca1ff 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt @@ -9,8 +9,12 @@ Device Tree Bindings for the Arasan SDHCI Controller [4] Documentation/devicetree/bindings/phy/phy-bindings.txt Required Properties: - - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or - 'arasan,sdhci-4.9a' or 'arasan,sdhci-5.1' + - compatible: Compatibility string. One of: + - "arasan,sdhci-8.9a" + - "arasan,sdhci-4.9a" + - "arasan,sdhci-5.1" + - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": The PHY in rk3399. + For this device it is strongly suggested to include arasan,soc-ctl-syscon. - reg: From mmc bindings: Register location and length. - clocks: From clock bindings: Handles to clock inputs. - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb" @@ -22,6 +26,11 @@ Required Properties for "arasan,sdhci-5.1": - phys: From PHY bindings: Phandle for the Generic PHY for arasan. - phy-names: MUST be "phy_arasan". +Optional Properties: + - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt) + used to access core corecfg registers. Offsets of registers in this + syscon are determined based on the main compatible string for the device. + Example: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; @@ -42,3 +51,17 @@ Example: phys = <&emmc_phy>; phy-names = "phy_arasan"; } ; + + sdhci: sdhci@fe330000 { + compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; + reg = <0x0 0xfe330000 0x0 0x10000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; + clock-names = "clk_xin", "clk_ahb"; + arasan,soc-ctl-syscon = <&grf>; + assigned-clocks = <&cru SCLK_EMMC>; + assigned-clock-rates = <200000000>; + phys = <&emmc_phy>; + phy-names = "phy_arasan"; + status = "disabled"; + }; -- 2.8.0.rc3.226.g39d4020
WARNING: multiple messages have this Message-ID (diff)
From: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> To: ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, kishon-l0cyMroinI0@public.gmane.org, Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org Cc: mark.rutland-5wv7dgnIgG8@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org, briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, adrian.hunter-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org Subject: [PATCH 03/11] Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs Date: Tue, 7 Jun 2016 15:44:36 -0700 [thread overview] Message-ID: <1465339484-969-4-git-send-email-dianders@chromium.org> (raw) In-Reply-To: <1465339484-969-1-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> As can be seen in Arasan's datasheet [1] there are several "corecfg" settings in their SDHCI IP Block that are supposed to be controlled by software. Although the datasheet referenced is a bit vague about how to access corecfg, in Figure 5 you can see that for Arasan's PHY (a separate component than their SDHCI component) they describe the "phyctrl" registers as being "FROM SOC CTL REG", implying that it's up to the licensee of the Arasan IP block to implement these registers. It seems sane to assume that the "corecfg" registers in their SDHCI IP block works in a similar way for all licensees of the IP Block. Device tree has a model that allows a device to get a reference to random registers located elsewhere in the SoC: sysctl. Let's leverage this model and allow adding a sysctl reference to access the control registers for the Arasan SDHCI PHYs. Having a reference to the control registers doesn't do much for us on its own since the Arasan spec doesn't specify how these corecfg values are laid out in memory. In the SDHCI driver we'll need a map detailing where each corecfg can be found in each implementation. This map can be found using the primary compatible string of the SDHCI device. In that spirit, document that existing rk3399 device trees already have a specific compatible string, though up to now they've always been relying on the driver supporting the generic. Note that since existing devices seem to work fairly well as-is, we'll list the syscon reference as "optional", but it's likely that we'll run into much fewer problems if we can actually set the proper values in the syscon, so it is strongly suggested that any SoCs where we have a map to set the corecfg also include a reference to the syscon. [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf Signed-off-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> --- .../devicetree/bindings/mmc/arasan,sdhci.txt | 27 ++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index 31b35c3a5e47..b67e623ca1ff 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt @@ -9,8 +9,12 @@ Device Tree Bindings for the Arasan SDHCI Controller [4] Documentation/devicetree/bindings/phy/phy-bindings.txt Required Properties: - - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or - 'arasan,sdhci-4.9a' or 'arasan,sdhci-5.1' + - compatible: Compatibility string. One of: + - "arasan,sdhci-8.9a" + - "arasan,sdhci-4.9a" + - "arasan,sdhci-5.1" + - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": The PHY in rk3399. + For this device it is strongly suggested to include arasan,soc-ctl-syscon. - reg: From mmc bindings: Register location and length. - clocks: From clock bindings: Handles to clock inputs. - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb" @@ -22,6 +26,11 @@ Required Properties for "arasan,sdhci-5.1": - phys: From PHY bindings: Phandle for the Generic PHY for arasan. - phy-names: MUST be "phy_arasan". +Optional Properties: + - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt) + used to access core corecfg registers. Offsets of registers in this + syscon are determined based on the main compatible string for the device. + Example: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; @@ -42,3 +51,17 @@ Example: phys = <&emmc_phy>; phy-names = "phy_arasan"; } ; + + sdhci: sdhci@fe330000 { + compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; + reg = <0x0 0xfe330000 0x0 0x10000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; + clock-names = "clk_xin", "clk_ahb"; + arasan,soc-ctl-syscon = <&grf>; + assigned-clocks = <&cru SCLK_EMMC>; + assigned-clock-rates = <200000000>; + phys = <&emmc_phy>; + phy-names = "phy_arasan"; + status = "disabled"; + }; -- 2.8.0.rc3.226.g39d4020
next prev parent reply other threads:[~2016-06-07 22:48 UTC|newest] Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-06-07 22:44 [PATCH 0/11] Changes to support 150 MHz eMMC on rk3399 Douglas Anderson 2016-06-07 22:44 ` Douglas Anderson 2016-06-07 22:44 ` [PATCH 01/11] phy: rockchip-emmc: Increase lock time allowance Douglas Anderson 2016-06-07 22:44 ` Douglas Anderson 2016-06-07 22:44 ` Douglas Anderson 2016-06-13 7:58 ` Shawn Lin 2016-06-13 7:58 ` Shawn Lin 2016-06-13 7:58 ` Shawn Lin 2016-06-13 23:07 ` Doug Anderson 2016-06-13 23:07 ` Doug Anderson 2016-06-13 23:07 ` Doug Anderson 2016-06-07 22:44 ` [PATCH 02/11] mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes Douglas Anderson 2016-06-07 22:44 ` Douglas Anderson 2016-06-07 22:44 ` Douglas Anderson 2016-06-13 8:08 ` Shawn Lin 2016-06-13 8:08 ` Shawn Lin 2016-06-13 8:08 ` Shawn Lin 2016-06-13 23:06 ` Doug Anderson 2016-06-13 23:06 ` Doug Anderson 2016-06-13 23:06 ` Doug Anderson 2016-06-07 22:44 ` Douglas Anderson [this message] 2016-06-07 22:44 ` [PATCH 03/11] Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs Douglas Anderson 2016-06-08 20:17 ` Rob Herring 2016-06-13 8:18 ` Shawn Lin 2016-06-13 9:32 ` Heiko Stübner 2016-06-13 9:32 ` Heiko Stübner 2016-06-13 23:07 ` Doug Anderson 2016-06-07 22:44 ` [PATCH 04/11] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399 Douglas Anderson 2016-06-07 22:44 ` Douglas Anderson 2016-06-07 22:44 ` Douglas Anderson 2016-06-13 8:36 ` Shawn Lin 2016-06-13 8:36 ` Shawn Lin 2016-06-13 23:06 ` Doug Anderson 2016-06-13 23:06 ` Doug Anderson 2016-06-13 23:06 ` Doug Anderson 2016-06-14 0:14 ` Shawn Lin 2016-06-14 0:14 ` Shawn Lin 2016-06-14 0:14 ` Shawn Lin 2016-06-14 0:43 ` Doug Anderson 2016-06-14 0:43 ` Doug Anderson 2016-06-14 0:43 ` Doug Anderson 2016-06-14 0:59 ` Shawn Lin 2016-06-14 0:59 ` Shawn Lin 2016-06-14 0:59 ` Shawn Lin 2016-06-14 2:13 ` Doug Anderson 2016-06-14 2:13 ` Doug Anderson 2016-06-14 2:13 ` Doug Anderson 2016-06-16 1:06 ` Shawn Lin 2016-06-16 1:06 ` Shawn Lin 2016-06-16 1:06 ` Shawn Lin 2016-06-07 22:44 ` [PATCH 05/11] arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399 Douglas Anderson 2016-06-07 22:44 ` Douglas Anderson 2016-06-07 22:44 ` [PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson 2016-06-08 20:19 ` Rob Herring 2016-06-08 20:52 ` Doug Anderson 2016-06-08 20:52 ` Doug Anderson 2016-06-10 13:10 ` Rob Herring 2016-06-13 23:05 ` Doug Anderson 2016-06-07 22:44 ` [PATCH 07/11] " Douglas Anderson 2016-06-07 22:44 ` Douglas Anderson 2016-06-07 22:44 ` Douglas Anderson 2016-06-07 22:44 ` [PATCH 08/11] Documentation: phy: Let the rockchip eMMC PHY get an exported " Douglas Anderson 2016-06-07 22:44 ` Douglas Anderson 2016-06-07 22:44 ` Douglas Anderson 2016-06-10 13:36 ` Rob Herring 2016-06-10 13:36 ` Rob Herring 2016-06-13 23:05 ` Doug Anderson 2016-06-13 23:05 ` Doug Anderson 2016-06-13 23:05 ` Doug Anderson 2016-06-07 22:44 ` [PATCH 09/11] phy: rockchip-emmc: Set phyctrl_frqsel based on " Douglas Anderson 2016-06-07 22:44 ` Douglas Anderson 2016-06-13 8:54 ` Shawn Lin 2016-06-13 8:54 ` Shawn Lin 2016-06-13 8:54 ` Shawn Lin 2016-06-13 23:05 ` Doug Anderson 2016-06-13 23:05 ` Doug Anderson 2016-06-13 23:05 ` Doug Anderson 2016-06-13 23:05 ` Doug Anderson 2016-06-14 0:24 ` Shawn Lin 2016-06-14 0:24 ` Shawn Lin 2016-06-14 0:24 ` Shawn Lin 2016-06-14 0:45 ` Doug Anderson 2016-06-14 0:45 ` Doug Anderson 2016-06-14 0:45 ` Doug Anderson 2016-06-07 22:44 ` [PATCH 10/11] phy: rockchip-emmc: Minor code cleanup in rockchip_emmc_phy_power_off() Douglas Anderson 2016-06-07 22:44 ` Douglas Anderson 2016-06-07 22:44 ` Douglas Anderson 2016-06-13 8:56 ` Shawn Lin 2016-06-13 8:56 ` Shawn Lin 2016-06-13 23:05 ` Doug Anderson 2016-06-13 23:05 ` Doug Anderson 2016-06-13 23:05 ` Doug Anderson 2016-06-07 22:44 ` [PATCH 11/11] arm64: dts: rockchip: Provide emmcclk to PHY for rk3399 Douglas Anderson 2016-06-07 22:44 ` Douglas Anderson
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