From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org
Cc: mathieu.poirier@linaro.org, suzuki.poulose@arm.com,
mike.leach@linaro.org, lcherian@marvell.com,
linux-kernel@vger.kernel.org,
Anshuman Khandual <anshuman.khandual@arm.com>
Subject: [PATCH V3 09/14] arm64: Add TRBE definitions
Date: Wed, 27 Jan 2021 14:25:33 +0530 [thread overview]
Message-ID: <1611737738-1493-10-git-send-email-anshuman.khandual@arm.com> (raw)
In-Reply-To: <1611737738-1493-1-git-send-email-anshuman.khandual@arm.com>
This adds TRBE related registers and corresponding feature macros.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
Changes in V3:
- ID_AA64DFR0_TRBE_SHIFT has been moved here from the TRBE driver
- Changed TRBLIMITR_TRIG_MODE_SHIFT as 3
arch/arm64/include/asm/sysreg.h | 50 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 4acff97..85ae4db 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -329,6 +329,55 @@
/*** End of Statistical Profiling Extension ***/
+/*
+ * TRBE Registers
+ */
+#define SYS_TRBLIMITR_EL1 sys_reg(3, 0, 9, 11, 0)
+#define SYS_TRBPTR_EL1 sys_reg(3, 0, 9, 11, 1)
+#define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2)
+#define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3)
+#define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4)
+#define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6)
+#define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
+
+#define TRBLIMITR_LIMIT_MASK GENMASK_ULL(51, 0)
+#define TRBLIMITR_LIMIT_SHIFT 12
+#define TRBLIMITR_NVM BIT(5)
+#define TRBLIMITR_TRIG_MODE_MASK GENMASK(1, 0)
+#define TRBLIMITR_TRIG_MODE_SHIFT 3
+#define TRBLIMITR_FILL_MODE_MASK GENMASK(1, 0)
+#define TRBLIMITR_FILL_MODE_SHIFT 1
+#define TRBLIMITR_ENABLE BIT(0)
+#define TRBPTR_PTR_MASK GENMASK_ULL(63, 0)
+#define TRBPTR_PTR_SHIFT 0
+#define TRBBASER_BASE_MASK GENMASK_ULL(51, 0)
+#define TRBBASER_BASE_SHIFT 12
+#define TRBSR_EC_MASK GENMASK(5, 0)
+#define TRBSR_EC_SHIFT 26
+#define TRBSR_IRQ BIT(22)
+#define TRBSR_TRG BIT(21)
+#define TRBSR_WRAP BIT(20)
+#define TRBSR_ABORT BIT(18)
+#define TRBSR_STOP BIT(17)
+#define TRBSR_MSS_MASK GENMASK(15, 0)
+#define TRBSR_MSS_SHIFT 0
+#define TRBSR_BSC_MASK GENMASK(5, 0)
+#define TRBSR_BSC_SHIFT 0
+#define TRBSR_FSC_MASK GENMASK(5, 0)
+#define TRBSR_FSC_SHIFT 0
+#define TRBMAR_SHARE_MASK GENMASK(1, 0)
+#define TRBMAR_SHARE_SHIFT 8
+#define TRBMAR_OUTER_MASK GENMASK(3, 0)
+#define TRBMAR_OUTER_SHIFT 4
+#define TRBMAR_INNER_MASK GENMASK(3, 0)
+#define TRBMAR_INNER_SHIFT 0
+#define TRBTRG_TRG_MASK GENMASK(31, 0)
+#define TRBTRG_TRG_SHIFT 0
+#define TRBIDR_FLAG BIT(5)
+#define TRBIDR_PROG BIT(4)
+#define TRBIDR_ALIGN_MASK GENMASK(3, 0)
+#define TRBIDR_ALIGN_SHIFT 0
+
#define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
#define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
@@ -831,6 +880,7 @@
#define ID_AA64MMFR2_CNP_SHIFT 0
/* id_aa64dfr0 */
+#define ID_AA64DFR0_TRBE_SHIFT 44
#define ID_AA64DFR0_TRACE_FILT_SHIFT 40
#define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
#define ID_AA64DFR0_PMSVER_SHIFT 32
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org
Cc: mathieu.poirier@linaro.org,
Anshuman Khandual <anshuman.khandual@arm.com>,
suzuki.poulose@arm.com, linux-kernel@vger.kernel.org,
lcherian@marvell.com, mike.leach@linaro.org
Subject: [PATCH V3 09/14] arm64: Add TRBE definitions
Date: Wed, 27 Jan 2021 14:25:33 +0530 [thread overview]
Message-ID: <1611737738-1493-10-git-send-email-anshuman.khandual@arm.com> (raw)
In-Reply-To: <1611737738-1493-1-git-send-email-anshuman.khandual@arm.com>
This adds TRBE related registers and corresponding feature macros.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
Changes in V3:
- ID_AA64DFR0_TRBE_SHIFT has been moved here from the TRBE driver
- Changed TRBLIMITR_TRIG_MODE_SHIFT as 3
arch/arm64/include/asm/sysreg.h | 50 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 4acff97..85ae4db 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -329,6 +329,55 @@
/*** End of Statistical Profiling Extension ***/
+/*
+ * TRBE Registers
+ */
+#define SYS_TRBLIMITR_EL1 sys_reg(3, 0, 9, 11, 0)
+#define SYS_TRBPTR_EL1 sys_reg(3, 0, 9, 11, 1)
+#define SYS_TRBBASER_EL1 sys_reg(3, 0, 9, 11, 2)
+#define SYS_TRBSR_EL1 sys_reg(3, 0, 9, 11, 3)
+#define SYS_TRBMAR_EL1 sys_reg(3, 0, 9, 11, 4)
+#define SYS_TRBTRG_EL1 sys_reg(3, 0, 9, 11, 6)
+#define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7)
+
+#define TRBLIMITR_LIMIT_MASK GENMASK_ULL(51, 0)
+#define TRBLIMITR_LIMIT_SHIFT 12
+#define TRBLIMITR_NVM BIT(5)
+#define TRBLIMITR_TRIG_MODE_MASK GENMASK(1, 0)
+#define TRBLIMITR_TRIG_MODE_SHIFT 3
+#define TRBLIMITR_FILL_MODE_MASK GENMASK(1, 0)
+#define TRBLIMITR_FILL_MODE_SHIFT 1
+#define TRBLIMITR_ENABLE BIT(0)
+#define TRBPTR_PTR_MASK GENMASK_ULL(63, 0)
+#define TRBPTR_PTR_SHIFT 0
+#define TRBBASER_BASE_MASK GENMASK_ULL(51, 0)
+#define TRBBASER_BASE_SHIFT 12
+#define TRBSR_EC_MASK GENMASK(5, 0)
+#define TRBSR_EC_SHIFT 26
+#define TRBSR_IRQ BIT(22)
+#define TRBSR_TRG BIT(21)
+#define TRBSR_WRAP BIT(20)
+#define TRBSR_ABORT BIT(18)
+#define TRBSR_STOP BIT(17)
+#define TRBSR_MSS_MASK GENMASK(15, 0)
+#define TRBSR_MSS_SHIFT 0
+#define TRBSR_BSC_MASK GENMASK(5, 0)
+#define TRBSR_BSC_SHIFT 0
+#define TRBSR_FSC_MASK GENMASK(5, 0)
+#define TRBSR_FSC_SHIFT 0
+#define TRBMAR_SHARE_MASK GENMASK(1, 0)
+#define TRBMAR_SHARE_SHIFT 8
+#define TRBMAR_OUTER_MASK GENMASK(3, 0)
+#define TRBMAR_OUTER_SHIFT 4
+#define TRBMAR_INNER_MASK GENMASK(3, 0)
+#define TRBMAR_INNER_SHIFT 0
+#define TRBTRG_TRG_MASK GENMASK(31, 0)
+#define TRBTRG_TRG_SHIFT 0
+#define TRBIDR_FLAG BIT(5)
+#define TRBIDR_PROG BIT(4)
+#define TRBIDR_ALIGN_MASK GENMASK(3, 0)
+#define TRBIDR_ALIGN_SHIFT 0
+
#define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
#define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
@@ -831,6 +880,7 @@
#define ID_AA64MMFR2_CNP_SHIFT 0
/* id_aa64dfr0 */
+#define ID_AA64DFR0_TRBE_SHIFT 44
#define ID_AA64DFR0_TRACE_FILT_SHIFT 40
#define ID_AA64DFR0_DOUBLELOCK_SHIFT 36
#define ID_AA64DFR0_PMSVER_SHIFT 32
--
2.7.4
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next prev parent reply other threads:[~2021-01-27 9:59 UTC|newest]
Thread overview: 181+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-27 8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-27 8:55 ` [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-01 23:17 ` Mathieu Poirier
2021-02-01 23:17 ` Mathieu Poirier
2021-02-02 9:42 ` Suzuki K Poulose
2021-02-02 9:42 ` Suzuki K Poulose
2021-02-02 16:33 ` Mike Leach
2021-02-02 16:33 ` Mike Leach
2021-02-02 22:41 ` Suzuki K Poulose
2021-02-02 22:41 ` Suzuki K Poulose
2021-02-04 12:27 ` Mike Leach
2021-02-04 12:27 ` Mike Leach
2021-02-02 16:37 ` Mathieu Poirier
2021-02-02 16:37 ` Mathieu Poirier
2021-01-27 8:55 ` [PATCH V3 02/14] coresight: Do not scan for graph if none is present Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-01 23:44 ` Mathieu Poirier
2021-02-01 23:44 ` Mathieu Poirier
2021-02-02 11:10 ` Mike Leach
2021-02-02 11:10 ` Mike Leach
2021-02-02 14:36 ` Suzuki K Poulose
2021-02-02 14:36 ` Suzuki K Poulose
2021-01-27 8:55 ` [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-02 17:40 ` Mathieu Poirier
2021-02-02 17:40 ` Mathieu Poirier
2021-02-02 18:03 ` Mathieu Poirier
2021-02-02 18:03 ` Mathieu Poirier
2021-02-15 14:08 ` Mike Leach
2021-02-15 14:08 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-02 17:52 ` Mathieu Poirier
2021-02-02 17:52 ` Mathieu Poirier
2021-02-03 15:51 ` Suzuki K Poulose
2021-02-03 15:51 ` Suzuki K Poulose
2021-02-15 14:08 ` Mike Leach
2021-02-15 14:08 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 05/14] coresight: ete: Add support for ETE tracing Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-02 18:56 ` Mathieu Poirier
2021-02-02 18:56 ` Mathieu Poirier
2021-02-02 22:50 ` Suzuki K Poulose
2021-02-02 22:50 ` Suzuki K Poulose
2021-02-15 13:21 ` Mike Leach
2021-02-15 13:21 ` Mike Leach
2021-02-15 14:08 ` Mike Leach
2021-02-15 14:08 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 06/14] dts: bindings: Document device tree bindings for ETE Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-09 19:00 ` Rob Herring
2021-02-09 19:00 ` Rob Herring
2021-02-10 12:33 ` Suzuki K Poulose
2021-02-10 12:33 ` Suzuki K Poulose
2021-02-18 18:33 ` Rob Herring
2021-02-18 18:33 ` Rob Herring
2021-02-18 22:51 ` Suzuki K Poulose
2021-02-18 22:51 ` Suzuki K Poulose
2021-01-27 8:55 ` [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-03 19:05 ` Mathieu Poirier
2021-02-03 19:05 ` Mathieu Poirier
2021-02-03 23:36 ` Suzuki K Poulose
2021-02-03 23:36 ` Suzuki K Poulose
2021-02-15 16:27 ` Mike Leach
2021-02-15 16:27 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-28 9:16 ` Suzuki K Poulose
2021-01-28 9:16 ` Suzuki K Poulose
2021-02-04 18:34 ` Mathieu Poirier
2021-02-04 18:34 ` Mathieu Poirier
2021-02-16 10:40 ` Anshuman Khandual
2021-02-16 10:40 ` Anshuman Khandual
2021-02-16 20:44 ` Mathieu Poirier
2021-02-16 20:44 ` Mathieu Poirier
2021-02-16 10:21 ` Anshuman Khandual
2021-02-16 10:21 ` Anshuman Khandual
2021-02-15 16:27 ` Mike Leach
2021-02-15 16:27 ` Mike Leach
2021-02-15 16:56 ` Mathieu Poirier
2021-02-15 16:56 ` Mathieu Poirier
2021-02-15 17:58 ` Mike Leach
2021-02-15 17:58 ` Mike Leach
2021-02-16 20:30 ` Mathieu Poirier
2021-02-16 20:30 ` Mathieu Poirier
2021-01-27 8:55 ` Anshuman Khandual [this message]
2021-01-27 8:55 ` [PATCH V3 09/14] arm64: Add TRBE definitions Anshuman Khandual
2021-01-28 9:31 ` Suzuki K Poulose
2021-01-28 9:31 ` Suzuki K Poulose
2021-01-28 17:18 ` Catalin Marinas
2021-01-28 17:18 ` Catalin Marinas
2021-02-15 18:06 ` Mike Leach
2021-02-15 18:06 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 10/14] arm64: nvhe: Allow TRBE access at EL1 Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-27 9:58 ` Marc Zyngier
2021-01-27 9:58 ` Marc Zyngier
2021-01-28 9:34 ` Suzuki K Poulose
2021-01-28 9:34 ` Suzuki K Poulose
2021-01-28 9:46 ` Marc Zyngier
2021-01-28 9:46 ` Marc Zyngier
2021-01-28 9:48 ` Suzuki K Poulose
2021-01-28 9:48 ` Suzuki K Poulose
2021-01-27 8:55 ` [PATCH V3 11/14] coresight: sink: Add TRBE driver Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-29 10:23 ` Suzuki K Poulose
2021-02-02 5:55 ` Anshuman Khandual
2021-02-02 5:55 ` Anshuman Khandual
2021-02-05 17:53 ` Mathieu Poirier
2021-02-05 17:53 ` Mathieu Poirier
2021-02-08 4:20 ` Anshuman Khandual
2021-02-08 4:20 ` Anshuman Khandual
2021-02-09 17:39 ` Mathieu Poirier
2021-02-09 17:39 ` Mathieu Poirier
2021-02-10 4:12 ` Anshuman Khandual
2021-02-10 4:12 ` Anshuman Khandual
2021-02-10 16:54 ` Mathieu Poirier
2021-02-10 16:54 ` Mathieu Poirier
2021-02-10 19:00 ` Mathieu Poirier
2021-02-10 19:00 ` Mathieu Poirier
2021-02-12 5:43 ` Anshuman Khandual
2021-02-12 5:43 ` Anshuman Khandual
2021-02-12 17:02 ` Mathieu Poirier
2021-02-12 17:02 ` Mathieu Poirier
2021-02-11 19:00 ` Mathieu Poirier
2021-02-11 19:00 ` Mathieu Poirier
2021-02-12 3:31 ` Anshuman Khandual
2021-02-12 3:31 ` Anshuman Khandual
2021-02-12 16:57 ` Mathieu Poirier
2021-02-12 16:57 ` Mathieu Poirier
2021-02-15 9:26 ` Anshuman Khandual
2021-02-15 9:26 ` Anshuman Khandual
2021-02-12 20:26 ` Mathieu Poirier
2021-02-12 20:26 ` Mathieu Poirier
2021-02-15 9:46 ` Anshuman Khandual
2021-02-15 9:46 ` Anshuman Khandual
2021-02-16 9:00 ` Mike Leach
2021-02-16 9:00 ` Mike Leach
2021-02-16 9:44 ` Anshuman Khandual
2021-02-16 9:44 ` Anshuman Khandual
2021-02-16 12:12 ` Mike Leach
2021-02-16 12:12 ` Mike Leach
2021-02-18 7:50 ` Suzuki K Poulose
2021-02-18 7:50 ` Suzuki K Poulose
2021-02-18 14:30 ` Mike Leach
2021-02-18 14:30 ` Mike Leach
2021-02-18 15:14 ` Suzuki K Poulose
2021-02-18 15:14 ` Suzuki K Poulose
2021-02-22 10:42 ` Mike Leach
2021-02-22 10:42 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 12/14] dts: bindings: Document device tree bindings for Arm TRBE Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-09 19:04 ` Rob Herring
2021-02-09 19:04 ` Rob Herring
2021-01-27 8:55 ` [PATCH V3 13/14] perf: aux: Add flags for the buffer format Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-27 12:51 ` Peter Zijlstra
2021-01-27 12:51 ` Peter Zijlstra
2021-02-16 10:59 ` Mike Leach
2021-02-16 10:59 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 14/14] coresight: etm-perf: Add support for trace " Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-27 12:54 ` Peter Zijlstra
2021-01-27 12:54 ` Peter Zijlstra
2021-01-27 13:00 ` Al Grant
2021-01-27 13:00 ` Al Grant
2021-02-18 3:05 ` Anshuman Khandual
2021-02-18 3:05 ` Anshuman Khandual
2021-01-27 14:12 ` Suzuki K Poulose
2021-01-27 14:12 ` Suzuki K Poulose
2021-02-16 11:01 ` Mike Leach
2021-02-16 11:01 ` Mike Leach
2021-01-27 18:50 ` [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Mathieu Poirier
2021-01-27 18:50 ` Mathieu Poirier
2021-02-01 18:44 ` Mathieu Poirier
2021-02-01 18:44 ` Mathieu Poirier
2021-02-18 4:23 ` Anshuman Khandual
2021-02-18 4:23 ` Anshuman Khandual
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