From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Peter Zijlstra <peterz@infradead.org>,
Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org,
mathieu.poirier@linaro.org, mike.leach@linaro.org,
lcherian@marvell.com, linux-kernel@vger.kernel.org,
Leo Yan <leo.yan@linaro.org>
Subject: Re: [PATCH V3 14/14] coresight: etm-perf: Add support for trace buffer format
Date: Wed, 27 Jan 2021 14:12:15 +0000 [thread overview]
Message-ID: <fdde5dab-e76a-efec-2124-ef42f8ffa818@arm.com> (raw)
In-Reply-To: <YBFiecTmjA30qRaW@hirez.programming.kicks-ass.net>
Hi Peter
On 1/27/21 12:54 PM, Peter Zijlstra wrote:
> On Wed, Jan 27, 2021 at 02:25:38PM +0530, Anshuman Khandual wrote:
>
>> It is possible to have a
>> perf session where some events end up collecting the trace
>> in TMC-ETR while the others in TRBE. Thus we need a way
>> to identify the type of the trace for each AUX record.
>
>> diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
>> index 9a5ca45..169e6b3 100644
>> --- a/include/uapi/linux/perf_event.h
>> +++ b/include/uapi/linux/perf_event.h
>> @@ -1111,6 +1111,10 @@ enum perf_callchain_context {
>> #define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */
>> #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */
>>
>> +/* CoreSight PMU AUX buffer formats */
>> +#define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */
>> +#define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format of the source */
>
> Would CORESIGHT_FORMAT_ETR / CORESIGHT_FORMAT_TRBE be better names?
>
Not really. The format used by the ETR is CORESIGHT frame formatting. And
there are other sinks that uses the formatting. e.g, TMC-ETB (a sink with
internal memory), TMC-ETF (trace fifo with internal memory). So it is really
not tied to ETR.
As for TRBE, it simply pumps the data thrown at it to the memory. As such
calling it TRBE format would be confusing as the format of the buffer is
really Raw trace thrown at it. This can be inferred from the ETM/ETE
looking at the ID registers, which the userspace perf already captures
in the perf.data. So the decoder perf can look at the perf.data and the
AUX records to interpret the buffer correctly.
Suzuki
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Peter Zijlstra <peterz@infradead.org>,
Anshuman Khandual <anshuman.khandual@arm.com>
Cc: mathieu.poirier@linaro.org, coresight@lists.linaro.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Leo Yan <leo.yan@linaro.org>,
lcherian@marvell.com, mike.leach@linaro.org
Subject: Re: [PATCH V3 14/14] coresight: etm-perf: Add support for trace buffer format
Date: Wed, 27 Jan 2021 14:12:15 +0000 [thread overview]
Message-ID: <fdde5dab-e76a-efec-2124-ef42f8ffa818@arm.com> (raw)
In-Reply-To: <YBFiecTmjA30qRaW@hirez.programming.kicks-ass.net>
Hi Peter
On 1/27/21 12:54 PM, Peter Zijlstra wrote:
> On Wed, Jan 27, 2021 at 02:25:38PM +0530, Anshuman Khandual wrote:
>
>> It is possible to have a
>> perf session where some events end up collecting the trace
>> in TMC-ETR while the others in TRBE. Thus we need a way
>> to identify the type of the trace for each AUX record.
>
>> diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
>> index 9a5ca45..169e6b3 100644
>> --- a/include/uapi/linux/perf_event.h
>> +++ b/include/uapi/linux/perf_event.h
>> @@ -1111,6 +1111,10 @@ enum perf_callchain_context {
>> #define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */
>> #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */
>>
>> +/* CoreSight PMU AUX buffer formats */
>> +#define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */
>> +#define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format of the source */
>
> Would CORESIGHT_FORMAT_ETR / CORESIGHT_FORMAT_TRBE be better names?
>
Not really. The format used by the ETR is CORESIGHT frame formatting. And
there are other sinks that uses the formatting. e.g, TMC-ETB (a sink with
internal memory), TMC-ETF (trace fifo with internal memory). So it is really
not tied to ETR.
As for TRBE, it simply pumps the data thrown at it to the memory. As such
calling it TRBE format would be confusing as the format of the buffer is
really Raw trace thrown at it. This can be inferred from the ETM/ETE
looking at the ID registers, which the userspace perf already captures
in the perf.data. So the decoder perf can look at the perf.data and the
AUX records to interpret the buffer correctly.
Suzuki
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-01-27 14:16 UTC|newest]
Thread overview: 181+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-27 8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-27 8:55 ` [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-01 23:17 ` Mathieu Poirier
2021-02-01 23:17 ` Mathieu Poirier
2021-02-02 9:42 ` Suzuki K Poulose
2021-02-02 9:42 ` Suzuki K Poulose
2021-02-02 16:33 ` Mike Leach
2021-02-02 16:33 ` Mike Leach
2021-02-02 22:41 ` Suzuki K Poulose
2021-02-02 22:41 ` Suzuki K Poulose
2021-02-04 12:27 ` Mike Leach
2021-02-04 12:27 ` Mike Leach
2021-02-02 16:37 ` Mathieu Poirier
2021-02-02 16:37 ` Mathieu Poirier
2021-01-27 8:55 ` [PATCH V3 02/14] coresight: Do not scan for graph if none is present Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-01 23:44 ` Mathieu Poirier
2021-02-01 23:44 ` Mathieu Poirier
2021-02-02 11:10 ` Mike Leach
2021-02-02 11:10 ` Mike Leach
2021-02-02 14:36 ` Suzuki K Poulose
2021-02-02 14:36 ` Suzuki K Poulose
2021-01-27 8:55 ` [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-02 17:40 ` Mathieu Poirier
2021-02-02 17:40 ` Mathieu Poirier
2021-02-02 18:03 ` Mathieu Poirier
2021-02-02 18:03 ` Mathieu Poirier
2021-02-15 14:08 ` Mike Leach
2021-02-15 14:08 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-02 17:52 ` Mathieu Poirier
2021-02-02 17:52 ` Mathieu Poirier
2021-02-03 15:51 ` Suzuki K Poulose
2021-02-03 15:51 ` Suzuki K Poulose
2021-02-15 14:08 ` Mike Leach
2021-02-15 14:08 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 05/14] coresight: ete: Add support for ETE tracing Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-02 18:56 ` Mathieu Poirier
2021-02-02 18:56 ` Mathieu Poirier
2021-02-02 22:50 ` Suzuki K Poulose
2021-02-02 22:50 ` Suzuki K Poulose
2021-02-15 13:21 ` Mike Leach
2021-02-15 13:21 ` Mike Leach
2021-02-15 14:08 ` Mike Leach
2021-02-15 14:08 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 06/14] dts: bindings: Document device tree bindings for ETE Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-09 19:00 ` Rob Herring
2021-02-09 19:00 ` Rob Herring
2021-02-10 12:33 ` Suzuki K Poulose
2021-02-10 12:33 ` Suzuki K Poulose
2021-02-18 18:33 ` Rob Herring
2021-02-18 18:33 ` Rob Herring
2021-02-18 22:51 ` Suzuki K Poulose
2021-02-18 22:51 ` Suzuki K Poulose
2021-01-27 8:55 ` [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-03 19:05 ` Mathieu Poirier
2021-02-03 19:05 ` Mathieu Poirier
2021-02-03 23:36 ` Suzuki K Poulose
2021-02-03 23:36 ` Suzuki K Poulose
2021-02-15 16:27 ` Mike Leach
2021-02-15 16:27 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-28 9:16 ` Suzuki K Poulose
2021-01-28 9:16 ` Suzuki K Poulose
2021-02-04 18:34 ` Mathieu Poirier
2021-02-04 18:34 ` Mathieu Poirier
2021-02-16 10:40 ` Anshuman Khandual
2021-02-16 10:40 ` Anshuman Khandual
2021-02-16 20:44 ` Mathieu Poirier
2021-02-16 20:44 ` Mathieu Poirier
2021-02-16 10:21 ` Anshuman Khandual
2021-02-16 10:21 ` Anshuman Khandual
2021-02-15 16:27 ` Mike Leach
2021-02-15 16:27 ` Mike Leach
2021-02-15 16:56 ` Mathieu Poirier
2021-02-15 16:56 ` Mathieu Poirier
2021-02-15 17:58 ` Mike Leach
2021-02-15 17:58 ` Mike Leach
2021-02-16 20:30 ` Mathieu Poirier
2021-02-16 20:30 ` Mathieu Poirier
2021-01-27 8:55 ` [PATCH V3 09/14] arm64: Add TRBE definitions Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-28 9:31 ` Suzuki K Poulose
2021-01-28 9:31 ` Suzuki K Poulose
2021-01-28 17:18 ` Catalin Marinas
2021-01-28 17:18 ` Catalin Marinas
2021-02-15 18:06 ` Mike Leach
2021-02-15 18:06 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 10/14] arm64: nvhe: Allow TRBE access at EL1 Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-27 9:58 ` Marc Zyngier
2021-01-27 9:58 ` Marc Zyngier
2021-01-28 9:34 ` Suzuki K Poulose
2021-01-28 9:34 ` Suzuki K Poulose
2021-01-28 9:46 ` Marc Zyngier
2021-01-28 9:46 ` Marc Zyngier
2021-01-28 9:48 ` Suzuki K Poulose
2021-01-28 9:48 ` Suzuki K Poulose
2021-01-27 8:55 ` [PATCH V3 11/14] coresight: sink: Add TRBE driver Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-29 10:23 ` Suzuki K Poulose
2021-02-02 5:55 ` Anshuman Khandual
2021-02-02 5:55 ` Anshuman Khandual
2021-02-05 17:53 ` Mathieu Poirier
2021-02-05 17:53 ` Mathieu Poirier
2021-02-08 4:20 ` Anshuman Khandual
2021-02-08 4:20 ` Anshuman Khandual
2021-02-09 17:39 ` Mathieu Poirier
2021-02-09 17:39 ` Mathieu Poirier
2021-02-10 4:12 ` Anshuman Khandual
2021-02-10 4:12 ` Anshuman Khandual
2021-02-10 16:54 ` Mathieu Poirier
2021-02-10 16:54 ` Mathieu Poirier
2021-02-10 19:00 ` Mathieu Poirier
2021-02-10 19:00 ` Mathieu Poirier
2021-02-12 5:43 ` Anshuman Khandual
2021-02-12 5:43 ` Anshuman Khandual
2021-02-12 17:02 ` Mathieu Poirier
2021-02-12 17:02 ` Mathieu Poirier
2021-02-11 19:00 ` Mathieu Poirier
2021-02-11 19:00 ` Mathieu Poirier
2021-02-12 3:31 ` Anshuman Khandual
2021-02-12 3:31 ` Anshuman Khandual
2021-02-12 16:57 ` Mathieu Poirier
2021-02-12 16:57 ` Mathieu Poirier
2021-02-15 9:26 ` Anshuman Khandual
2021-02-15 9:26 ` Anshuman Khandual
2021-02-12 20:26 ` Mathieu Poirier
2021-02-12 20:26 ` Mathieu Poirier
2021-02-15 9:46 ` Anshuman Khandual
2021-02-15 9:46 ` Anshuman Khandual
2021-02-16 9:00 ` Mike Leach
2021-02-16 9:00 ` Mike Leach
2021-02-16 9:44 ` Anshuman Khandual
2021-02-16 9:44 ` Anshuman Khandual
2021-02-16 12:12 ` Mike Leach
2021-02-16 12:12 ` Mike Leach
2021-02-18 7:50 ` Suzuki K Poulose
2021-02-18 7:50 ` Suzuki K Poulose
2021-02-18 14:30 ` Mike Leach
2021-02-18 14:30 ` Mike Leach
2021-02-18 15:14 ` Suzuki K Poulose
2021-02-18 15:14 ` Suzuki K Poulose
2021-02-22 10:42 ` Mike Leach
2021-02-22 10:42 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 12/14] dts: bindings: Document device tree bindings for Arm TRBE Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-09 19:04 ` Rob Herring
2021-02-09 19:04 ` Rob Herring
2021-01-27 8:55 ` [PATCH V3 13/14] perf: aux: Add flags for the buffer format Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-27 12:51 ` Peter Zijlstra
2021-01-27 12:51 ` Peter Zijlstra
2021-02-16 10:59 ` Mike Leach
2021-02-16 10:59 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 14/14] coresight: etm-perf: Add support for trace " Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-27 12:54 ` Peter Zijlstra
2021-01-27 12:54 ` Peter Zijlstra
2021-01-27 13:00 ` Al Grant
2021-01-27 13:00 ` Al Grant
2021-02-18 3:05 ` Anshuman Khandual
2021-02-18 3:05 ` Anshuman Khandual
2021-01-27 14:12 ` Suzuki K Poulose [this message]
2021-01-27 14:12 ` Suzuki K Poulose
2021-02-16 11:01 ` Mike Leach
2021-02-16 11:01 ` Mike Leach
2021-01-27 18:50 ` [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Mathieu Poirier
2021-01-27 18:50 ` Mathieu Poirier
2021-02-01 18:44 ` Mathieu Poirier
2021-02-01 18:44 ` Mathieu Poirier
2021-02-18 4:23 ` Anshuman Khandual
2021-02-18 4:23 ` Anshuman Khandual
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