From: Mike Leach <mike.leach@linaro.org>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Coresight ML <coresight@lists.linaro.org>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
"Suzuki K. Poulose" <suzuki.poulose@arm.com>,
Linu Cherian <lcherian@marvell.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access
Date: Mon, 15 Feb 2021 14:08:15 +0000 [thread overview]
Message-ID: <CAJ9a7VgFbnUVqt5G0oSrfbLBrq9b4iRbvQLpz+v7wiv0NrV9Jg@mail.gmail.com> (raw)
In-Reply-To: <1611737738-1493-5-git-send-email-anshuman.khandual@arm.com>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
<anshuman.khandual@arm.com> wrote:
>
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>
> Add support for handling the system registers for Embedded Trace
> Extensions (ETE). ETE shares most of the registers with ETMv4 except
> for some and also adds some new registers. Re-arrange the ETMv4x list
> to share the common definitions and add the ETE sysreg support.
>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-etm4x-core.c | 32 +++++++++++++
> drivers/hwtracing/coresight/coresight-etm4x.h | 52 ++++++++++++++++++----
> 2 files changed, 75 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 9edf8be..9e92d2a 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -114,6 +114,38 @@ void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
> }
> }
>
> +u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
> +{
> + u64 res = 0;
> +
> + switch (offset) {
> + ETE_READ_CASES(res)
> + default :
> + WARN_ONCE(1, "ete: trying to read unsupported register @%x\n",
> + offset);
> + }
> +
> + if (!_relaxed)
> + __iormb(res); /* Imitate the !relaxed I/O helpers */
> +
> + return res;
> +}
> +
> +void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
> +{
> + if (!_relaxed)
> + __iowmb(); /* Imitate the !relaxed I/O helpers */
> + if (!_64bit)
> + val &= GENMASK(31, 0);
> +
> + switch (offset) {
> + ETE_WRITE_CASES(val)
> + default :
> + WARN_ONCE(1, "ete: trying to write to unsupported register @%x\n",
> + offset);
> + }
> +}
> +
> static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
> struct csdev_access *csa)
> {
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 0e86eba..ca24ac5 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -29,6 +29,7 @@
> #define TRCAUXCTLR 0x018
> #define TRCEVENTCTL0R 0x020
> #define TRCEVENTCTL1R 0x024
> +#define TRCRSR 0x028
> #define TRCSTALLCTLR 0x02C
> #define TRCTSCTLR 0x030
> #define TRCSYNCPR 0x034
> @@ -49,6 +50,7 @@
> #define TRCSEQRSTEVR 0x118
> #define TRCSEQSTR 0x11C
> #define TRCEXTINSELR 0x120
> +#define TRCEXTINSELRn(n) (0x120 + (n * 4)) /* n = 0-3 */
> #define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */
> #define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */
> #define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */
> @@ -160,10 +162,22 @@
> #define CASE_NOP(__unused, x) \
> case (x): /* fall through */
>
> +#define ETE_ONLY_SYSREG_LIST(op, val) \
> + CASE_##op((val), TRCRSR) \
> + CASE_##op((val), TRCEXTINSELRn(1)) \
> + CASE_##op((val), TRCEXTINSELRn(2)) \
> + CASE_##op((val), TRCEXTINSELRn(3))
> +
> /* List of registers accessible via System instructions */
> -#define ETM_SYSREG_LIST(op, val) \
> - CASE_##op((val), TRCPRGCTLR) \
> +#define ETM4x_ONLY_SYSREG_LIST(op, val) \
> CASE_##op((val), TRCPROCSELR) \
> + CASE_##op((val), TRCVDCTLR) \
> + CASE_##op((val), TRCVDSACCTLR) \
> + CASE_##op((val), TRCVDARCCTLR) \
> + CASE_##op((val), TRCOSLAR)
> +
> +#define ETM_COMMON_SYSREG_LIST(op, val) \
> + CASE_##op((val), TRCPRGCTLR) \
> CASE_##op((val), TRCSTATR) \
> CASE_##op((val), TRCCONFIGR) \
> CASE_##op((val), TRCAUXCTLR) \
> @@ -180,9 +194,6 @@
> CASE_##op((val), TRCVIIECTLR) \
> CASE_##op((val), TRCVISSCTLR) \
> CASE_##op((val), TRCVIPCSSCTLR) \
> - CASE_##op((val), TRCVDCTLR) \
> - CASE_##op((val), TRCVDSACCTLR) \
> - CASE_##op((val), TRCVDARCCTLR) \
> CASE_##op((val), TRCSEQEVRn(0)) \
> CASE_##op((val), TRCSEQEVRn(1)) \
> CASE_##op((val), TRCSEQEVRn(2)) \
> @@ -277,7 +288,6 @@
> CASE_##op((val), TRCSSPCICRn(5)) \
> CASE_##op((val), TRCSSPCICRn(6)) \
> CASE_##op((val), TRCSSPCICRn(7)) \
> - CASE_##op((val), TRCOSLAR) \
> CASE_##op((val), TRCOSLSR) \
> CASE_##op((val), TRCACVRn(0)) \
> CASE_##op((val), TRCACVRn(1)) \
> @@ -369,12 +379,36 @@
> CASE_##op((val), TRCPIDR2) \
> CASE_##op((val), TRCPIDR3)
>
> -#define ETM4x_READ_SYSREG_CASES(res) ETM_SYSREG_LIST(READ, (res))
> -#define ETM4x_WRITE_SYSREG_CASES(val) ETM_SYSREG_LIST(WRITE, (val))
> +#define ETM4x_READ_SYSREG_CASES(res) \
> + ETM_COMMON_SYSREG_LIST(READ, (res)) \
> + ETM4x_ONLY_SYSREG_LIST(READ, (res))
> +
> +#define ETM4x_WRITE_SYSREG_CASES(val) \
> + ETM_COMMON_SYSREG_LIST(WRITE, (val)) \
> + ETM4x_ONLY_SYSREG_LIST(WRITE, (val))
> +
> +#define ETM_COMMON_SYSREG_LIST_CASES \
> + ETM_COMMON_SYSREG_LIST(NOP, __unused)
> +
> +#define ETM4x_SYSREG_LIST_CASES \
> + ETM_COMMON_SYSREG_LIST_CASES \
> + ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
>
> -#define ETM4x_SYSREG_LIST_CASES ETM_SYSREG_LIST(NOP, __unused)
> #define ETM4x_MMAP_LIST_CASES ETM_MMAP_LIST(NOP, __unused)
>
> +/* ETE only supports system register access */
> +#define ETE_READ_CASES(res) \
> + ETM_COMMON_SYSREG_LIST(READ, (res)) \
> + ETE_ONLY_SYSREG_LIST(READ, (res))
> +
> +#define ETE_WRITE_CASES(val) \
> + ETM_COMMON_SYSREG_LIST(WRITE, (val)) \
> + ETE_ONLY_SYSREG_LIST(WRITE, (val))
> +
> +#define ETE_ONLY_SYSREG_LIST_CASES \
> + ETM_COMMON_SYSREG_LIST_CASES \
> + ETE_ONLY_SYSREG_LIST(NOP, __unused)
> +
> #define read_etm4x_sysreg_offset(offset, _64bit) \
> ({ \
> u64 __val; \
> --
> 2.7.4
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
WARNING: multiple messages have this Message-ID (diff)
From: Mike Leach <mike.leach@linaro.org>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>,
"Suzuki K. Poulose" <suzuki.poulose@arm.com>,
Coresight ML <coresight@lists.linaro.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Linu Cherian <lcherian@marvell.com>
Subject: Re: [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access
Date: Mon, 15 Feb 2021 14:08:15 +0000 [thread overview]
Message-ID: <CAJ9a7VgFbnUVqt5G0oSrfbLBrq9b4iRbvQLpz+v7wiv0NrV9Jg@mail.gmail.com> (raw)
In-Reply-To: <1611737738-1493-5-git-send-email-anshuman.khandual@arm.com>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
On Wed, 27 Jan 2021 at 08:55, Anshuman Khandual
<anshuman.khandual@arm.com> wrote:
>
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>
> Add support for handling the system registers for Embedded Trace
> Extensions (ETE). ETE shares most of the registers with ETMv4 except
> for some and also adds some new registers. Re-arrange the ETMv4x list
> to share the common definitions and add the ETE sysreg support.
>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-etm4x-core.c | 32 +++++++++++++
> drivers/hwtracing/coresight/coresight-etm4x.h | 52 ++++++++++++++++++----
> 2 files changed, 75 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 9edf8be..9e92d2a 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -114,6 +114,38 @@ void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
> }
> }
>
> +u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
> +{
> + u64 res = 0;
> +
> + switch (offset) {
> + ETE_READ_CASES(res)
> + default :
> + WARN_ONCE(1, "ete: trying to read unsupported register @%x\n",
> + offset);
> + }
> +
> + if (!_relaxed)
> + __iormb(res); /* Imitate the !relaxed I/O helpers */
> +
> + return res;
> +}
> +
> +void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
> +{
> + if (!_relaxed)
> + __iowmb(); /* Imitate the !relaxed I/O helpers */
> + if (!_64bit)
> + val &= GENMASK(31, 0);
> +
> + switch (offset) {
> + ETE_WRITE_CASES(val)
> + default :
> + WARN_ONCE(1, "ete: trying to write to unsupported register @%x\n",
> + offset);
> + }
> +}
> +
> static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
> struct csdev_access *csa)
> {
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 0e86eba..ca24ac5 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -29,6 +29,7 @@
> #define TRCAUXCTLR 0x018
> #define TRCEVENTCTL0R 0x020
> #define TRCEVENTCTL1R 0x024
> +#define TRCRSR 0x028
> #define TRCSTALLCTLR 0x02C
> #define TRCTSCTLR 0x030
> #define TRCSYNCPR 0x034
> @@ -49,6 +50,7 @@
> #define TRCSEQRSTEVR 0x118
> #define TRCSEQSTR 0x11C
> #define TRCEXTINSELR 0x120
> +#define TRCEXTINSELRn(n) (0x120 + (n * 4)) /* n = 0-3 */
> #define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */
> #define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */
> #define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */
> @@ -160,10 +162,22 @@
> #define CASE_NOP(__unused, x) \
> case (x): /* fall through */
>
> +#define ETE_ONLY_SYSREG_LIST(op, val) \
> + CASE_##op((val), TRCRSR) \
> + CASE_##op((val), TRCEXTINSELRn(1)) \
> + CASE_##op((val), TRCEXTINSELRn(2)) \
> + CASE_##op((val), TRCEXTINSELRn(3))
> +
> /* List of registers accessible via System instructions */
> -#define ETM_SYSREG_LIST(op, val) \
> - CASE_##op((val), TRCPRGCTLR) \
> +#define ETM4x_ONLY_SYSREG_LIST(op, val) \
> CASE_##op((val), TRCPROCSELR) \
> + CASE_##op((val), TRCVDCTLR) \
> + CASE_##op((val), TRCVDSACCTLR) \
> + CASE_##op((val), TRCVDARCCTLR) \
> + CASE_##op((val), TRCOSLAR)
> +
> +#define ETM_COMMON_SYSREG_LIST(op, val) \
> + CASE_##op((val), TRCPRGCTLR) \
> CASE_##op((val), TRCSTATR) \
> CASE_##op((val), TRCCONFIGR) \
> CASE_##op((val), TRCAUXCTLR) \
> @@ -180,9 +194,6 @@
> CASE_##op((val), TRCVIIECTLR) \
> CASE_##op((val), TRCVISSCTLR) \
> CASE_##op((val), TRCVIPCSSCTLR) \
> - CASE_##op((val), TRCVDCTLR) \
> - CASE_##op((val), TRCVDSACCTLR) \
> - CASE_##op((val), TRCVDARCCTLR) \
> CASE_##op((val), TRCSEQEVRn(0)) \
> CASE_##op((val), TRCSEQEVRn(1)) \
> CASE_##op((val), TRCSEQEVRn(2)) \
> @@ -277,7 +288,6 @@
> CASE_##op((val), TRCSSPCICRn(5)) \
> CASE_##op((val), TRCSSPCICRn(6)) \
> CASE_##op((val), TRCSSPCICRn(7)) \
> - CASE_##op((val), TRCOSLAR) \
> CASE_##op((val), TRCOSLSR) \
> CASE_##op((val), TRCACVRn(0)) \
> CASE_##op((val), TRCACVRn(1)) \
> @@ -369,12 +379,36 @@
> CASE_##op((val), TRCPIDR2) \
> CASE_##op((val), TRCPIDR3)
>
> -#define ETM4x_READ_SYSREG_CASES(res) ETM_SYSREG_LIST(READ, (res))
> -#define ETM4x_WRITE_SYSREG_CASES(val) ETM_SYSREG_LIST(WRITE, (val))
> +#define ETM4x_READ_SYSREG_CASES(res) \
> + ETM_COMMON_SYSREG_LIST(READ, (res)) \
> + ETM4x_ONLY_SYSREG_LIST(READ, (res))
> +
> +#define ETM4x_WRITE_SYSREG_CASES(val) \
> + ETM_COMMON_SYSREG_LIST(WRITE, (val)) \
> + ETM4x_ONLY_SYSREG_LIST(WRITE, (val))
> +
> +#define ETM_COMMON_SYSREG_LIST_CASES \
> + ETM_COMMON_SYSREG_LIST(NOP, __unused)
> +
> +#define ETM4x_SYSREG_LIST_CASES \
> + ETM_COMMON_SYSREG_LIST_CASES \
> + ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
>
> -#define ETM4x_SYSREG_LIST_CASES ETM_SYSREG_LIST(NOP, __unused)
> #define ETM4x_MMAP_LIST_CASES ETM_MMAP_LIST(NOP, __unused)
>
> +/* ETE only supports system register access */
> +#define ETE_READ_CASES(res) \
> + ETM_COMMON_SYSREG_LIST(READ, (res)) \
> + ETE_ONLY_SYSREG_LIST(READ, (res))
> +
> +#define ETE_WRITE_CASES(val) \
> + ETM_COMMON_SYSREG_LIST(WRITE, (val)) \
> + ETE_ONLY_SYSREG_LIST(WRITE, (val))
> +
> +#define ETE_ONLY_SYSREG_LIST_CASES \
> + ETM_COMMON_SYSREG_LIST_CASES \
> + ETE_ONLY_SYSREG_LIST(NOP, __unused)
> +
> #define read_etm4x_sysreg_offset(offset, _64bit) \
> ({ \
> u64 __val; \
> --
> 2.7.4
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-02-15 14:10 UTC|newest]
Thread overview: 181+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-27 8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-27 8:55 ` [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-01 23:17 ` Mathieu Poirier
2021-02-01 23:17 ` Mathieu Poirier
2021-02-02 9:42 ` Suzuki K Poulose
2021-02-02 9:42 ` Suzuki K Poulose
2021-02-02 16:33 ` Mike Leach
2021-02-02 16:33 ` Mike Leach
2021-02-02 22:41 ` Suzuki K Poulose
2021-02-02 22:41 ` Suzuki K Poulose
2021-02-04 12:27 ` Mike Leach
2021-02-04 12:27 ` Mike Leach
2021-02-02 16:37 ` Mathieu Poirier
2021-02-02 16:37 ` Mathieu Poirier
2021-01-27 8:55 ` [PATCH V3 02/14] coresight: Do not scan for graph if none is present Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-01 23:44 ` Mathieu Poirier
2021-02-01 23:44 ` Mathieu Poirier
2021-02-02 11:10 ` Mike Leach
2021-02-02 11:10 ` Mike Leach
2021-02-02 14:36 ` Suzuki K Poulose
2021-02-02 14:36 ` Suzuki K Poulose
2021-01-27 8:55 ` [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-02 17:40 ` Mathieu Poirier
2021-02-02 17:40 ` Mathieu Poirier
2021-02-02 18:03 ` Mathieu Poirier
2021-02-02 18:03 ` Mathieu Poirier
2021-02-15 14:08 ` Mike Leach
2021-02-15 14:08 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-02 17:52 ` Mathieu Poirier
2021-02-02 17:52 ` Mathieu Poirier
2021-02-03 15:51 ` Suzuki K Poulose
2021-02-03 15:51 ` Suzuki K Poulose
2021-02-15 14:08 ` Mike Leach [this message]
2021-02-15 14:08 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 05/14] coresight: ete: Add support for ETE tracing Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-02 18:56 ` Mathieu Poirier
2021-02-02 18:56 ` Mathieu Poirier
2021-02-02 22:50 ` Suzuki K Poulose
2021-02-02 22:50 ` Suzuki K Poulose
2021-02-15 13:21 ` Mike Leach
2021-02-15 13:21 ` Mike Leach
2021-02-15 14:08 ` Mike Leach
2021-02-15 14:08 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 06/14] dts: bindings: Document device tree bindings for ETE Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-09 19:00 ` Rob Herring
2021-02-09 19:00 ` Rob Herring
2021-02-10 12:33 ` Suzuki K Poulose
2021-02-10 12:33 ` Suzuki K Poulose
2021-02-18 18:33 ` Rob Herring
2021-02-18 18:33 ` Rob Herring
2021-02-18 22:51 ` Suzuki K Poulose
2021-02-18 22:51 ` Suzuki K Poulose
2021-01-27 8:55 ` [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-03 19:05 ` Mathieu Poirier
2021-02-03 19:05 ` Mathieu Poirier
2021-02-03 23:36 ` Suzuki K Poulose
2021-02-03 23:36 ` Suzuki K Poulose
2021-02-15 16:27 ` Mike Leach
2021-02-15 16:27 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-28 9:16 ` Suzuki K Poulose
2021-01-28 9:16 ` Suzuki K Poulose
2021-02-04 18:34 ` Mathieu Poirier
2021-02-04 18:34 ` Mathieu Poirier
2021-02-16 10:40 ` Anshuman Khandual
2021-02-16 10:40 ` Anshuman Khandual
2021-02-16 20:44 ` Mathieu Poirier
2021-02-16 20:44 ` Mathieu Poirier
2021-02-16 10:21 ` Anshuman Khandual
2021-02-16 10:21 ` Anshuman Khandual
2021-02-15 16:27 ` Mike Leach
2021-02-15 16:27 ` Mike Leach
2021-02-15 16:56 ` Mathieu Poirier
2021-02-15 16:56 ` Mathieu Poirier
2021-02-15 17:58 ` Mike Leach
2021-02-15 17:58 ` Mike Leach
2021-02-16 20:30 ` Mathieu Poirier
2021-02-16 20:30 ` Mathieu Poirier
2021-01-27 8:55 ` [PATCH V3 09/14] arm64: Add TRBE definitions Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-28 9:31 ` Suzuki K Poulose
2021-01-28 9:31 ` Suzuki K Poulose
2021-01-28 17:18 ` Catalin Marinas
2021-01-28 17:18 ` Catalin Marinas
2021-02-15 18:06 ` Mike Leach
2021-02-15 18:06 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 10/14] arm64: nvhe: Allow TRBE access at EL1 Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-27 9:58 ` Marc Zyngier
2021-01-27 9:58 ` Marc Zyngier
2021-01-28 9:34 ` Suzuki K Poulose
2021-01-28 9:34 ` Suzuki K Poulose
2021-01-28 9:46 ` Marc Zyngier
2021-01-28 9:46 ` Marc Zyngier
2021-01-28 9:48 ` Suzuki K Poulose
2021-01-28 9:48 ` Suzuki K Poulose
2021-01-27 8:55 ` [PATCH V3 11/14] coresight: sink: Add TRBE driver Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-29 10:23 ` Suzuki K Poulose
2021-02-02 5:55 ` Anshuman Khandual
2021-02-02 5:55 ` Anshuman Khandual
2021-02-05 17:53 ` Mathieu Poirier
2021-02-05 17:53 ` Mathieu Poirier
2021-02-08 4:20 ` Anshuman Khandual
2021-02-08 4:20 ` Anshuman Khandual
2021-02-09 17:39 ` Mathieu Poirier
2021-02-09 17:39 ` Mathieu Poirier
2021-02-10 4:12 ` Anshuman Khandual
2021-02-10 4:12 ` Anshuman Khandual
2021-02-10 16:54 ` Mathieu Poirier
2021-02-10 16:54 ` Mathieu Poirier
2021-02-10 19:00 ` Mathieu Poirier
2021-02-10 19:00 ` Mathieu Poirier
2021-02-12 5:43 ` Anshuman Khandual
2021-02-12 5:43 ` Anshuman Khandual
2021-02-12 17:02 ` Mathieu Poirier
2021-02-12 17:02 ` Mathieu Poirier
2021-02-11 19:00 ` Mathieu Poirier
2021-02-11 19:00 ` Mathieu Poirier
2021-02-12 3:31 ` Anshuman Khandual
2021-02-12 3:31 ` Anshuman Khandual
2021-02-12 16:57 ` Mathieu Poirier
2021-02-12 16:57 ` Mathieu Poirier
2021-02-15 9:26 ` Anshuman Khandual
2021-02-15 9:26 ` Anshuman Khandual
2021-02-12 20:26 ` Mathieu Poirier
2021-02-12 20:26 ` Mathieu Poirier
2021-02-15 9:46 ` Anshuman Khandual
2021-02-15 9:46 ` Anshuman Khandual
2021-02-16 9:00 ` Mike Leach
2021-02-16 9:00 ` Mike Leach
2021-02-16 9:44 ` Anshuman Khandual
2021-02-16 9:44 ` Anshuman Khandual
2021-02-16 12:12 ` Mike Leach
2021-02-16 12:12 ` Mike Leach
2021-02-18 7:50 ` Suzuki K Poulose
2021-02-18 7:50 ` Suzuki K Poulose
2021-02-18 14:30 ` Mike Leach
2021-02-18 14:30 ` Mike Leach
2021-02-18 15:14 ` Suzuki K Poulose
2021-02-18 15:14 ` Suzuki K Poulose
2021-02-22 10:42 ` Mike Leach
2021-02-22 10:42 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 12/14] dts: bindings: Document device tree bindings for Arm TRBE Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-02-09 19:04 ` Rob Herring
2021-02-09 19:04 ` Rob Herring
2021-01-27 8:55 ` [PATCH V3 13/14] perf: aux: Add flags for the buffer format Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-27 12:51 ` Peter Zijlstra
2021-01-27 12:51 ` Peter Zijlstra
2021-02-16 10:59 ` Mike Leach
2021-02-16 10:59 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 14/14] coresight: etm-perf: Add support for trace " Anshuman Khandual
2021-01-27 8:55 ` Anshuman Khandual
2021-01-27 12:54 ` Peter Zijlstra
2021-01-27 12:54 ` Peter Zijlstra
2021-01-27 13:00 ` Al Grant
2021-01-27 13:00 ` Al Grant
2021-02-18 3:05 ` Anshuman Khandual
2021-02-18 3:05 ` Anshuman Khandual
2021-01-27 14:12 ` Suzuki K Poulose
2021-01-27 14:12 ` Suzuki K Poulose
2021-02-16 11:01 ` Mike Leach
2021-02-16 11:01 ` Mike Leach
2021-01-27 18:50 ` [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Mathieu Poirier
2021-01-27 18:50 ` Mathieu Poirier
2021-02-01 18:44 ` Mathieu Poirier
2021-02-01 18:44 ` Mathieu Poirier
2021-02-18 4:23 ` Anshuman Khandual
2021-02-18 4:23 ` Anshuman Khandual
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