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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Spurio@rosetta.fi.intel.com,
	Rodrigo Vivi <rodrigo.vivi@intel.com>,
	Ceraolo@rosetta.fi.intel.com
Subject: [PATCH 03/20] drm/i915/icl: Show interrupt registers in debugfs
Date: Tue, 13 Feb 2018 18:37:21 +0200	[thread overview]
Message-ID: <20180213163738.9055-4-mika.kuoppala@linux.intel.com> (raw)
In-Reply-To: <20180213163738.9055-1-mika.kuoppala@linux.intel.com>

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

v2: Update for POR changes. (Daniele Ceraolo Spurio)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 82 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 81 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 960302668649..49d5bed87798 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -703,6 +703,64 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 				   i, I915_READ(GEN8_GT_IER(i)));
 		}
 
+		seq_printf(m, "PCU interrupt mask:\t%08x\n",
+			   I915_READ(GEN8_PCU_IMR));
+		seq_printf(m, "PCU interrupt identity:\t%08x\n",
+			   I915_READ(GEN8_PCU_IIR));
+		seq_printf(m, "PCU interrupt enable:\t%08x\n",
+			   I915_READ(GEN8_PCU_IER));
+	} else if (INTEL_GEN(dev_priv) >= 11) {
+		seq_printf(m, "Master Interrupt Control:  %08x\n",
+			   I915_READ(GEN11_GFX_MSTR_IRQ));
+
+		seq_printf(m, "Render/Copy Intr Enable:   %08x\n",
+			   I915_READ(GEN11_RENDER_COPY_INTR_ENABLE));
+		seq_printf(m, "VCS/VECS Intr Enable:      %08x\n",
+			   I915_READ(GEN11_VCS_VECS_INTR_ENABLE));
+		seq_printf(m, "GUC/SG Intr Enable:\t   %08x\n",
+			   I915_READ(GEN11_GUC_SG_INTR_ENABLE));
+		seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
+			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE));
+		seq_printf(m, "Crypto Intr Enable:\t   %08x\n",
+			   I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE));
+		seq_printf(m, "GUnit/CSME Intr Enable:\t   %08x\n",
+			   I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE));
+
+		seq_printf(m, "Display Interrupt Control:\t%08x\n",
+			   I915_READ(GEN11_DISPLAY_INT_CTL));
+
+		for_each_pipe(dev_priv, pipe) {
+			if (!intel_display_power_is_enabled(dev_priv,
+						POWER_DOMAIN_PIPE(pipe))) {
+				seq_printf(m, "Pipe %c power disabled\n",
+					   pipe_name(pipe));
+				continue;
+			}
+			seq_printf(m, "Pipe %c IMR:\t%08x\n",
+				   pipe_name(pipe),
+				   I915_READ(GEN8_DE_PIPE_IMR(pipe)));
+			seq_printf(m, "Pipe %c IIR:\t%08x\n",
+				   pipe_name(pipe),
+				   I915_READ(GEN8_DE_PIPE_IIR(pipe)));
+			seq_printf(m, "Pipe %c IER:\t%08x\n",
+				   pipe_name(pipe),
+				   I915_READ(GEN8_DE_PIPE_IER(pipe)));
+		}
+
+		seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
+			   I915_READ(GEN8_DE_PORT_IMR));
+		seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
+			   I915_READ(GEN8_DE_PORT_IIR));
+		seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
+			   I915_READ(GEN8_DE_PORT_IER));
+
+		seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
+			   I915_READ(GEN8_DE_MISC_IMR));
+		seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
+			   I915_READ(GEN8_DE_MISC_IIR));
+		seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
+			   I915_READ(GEN8_DE_MISC_IER));
+
 		seq_printf(m, "PCU interrupt mask:\t%08x\n",
 			   I915_READ(GEN8_PCU_IMR));
 		seq_printf(m, "PCU interrupt identity:\t%08x\n",
@@ -846,13 +904,35 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
 			   I915_READ(GTIMR));
 	}
-	if (INTEL_GEN(dev_priv) >= 6) {
+
+	if (INTEL_GEN(dev_priv) >= 11) {
+		seq_printf(m, "RCS Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_RCS0_RSVD_INTR_MASK));
+		seq_printf(m, "BCS Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_BCS_RSVD_INTR_MASK));
+		seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_VCS0_VCS1_INTR_MASK));
+		seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_VCS2_VCS3_INTR_MASK));
+		seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_VECS0_VECS1_INTR_MASK));
+		seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_GUC_SG_INTR_MASK));
+		seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
+			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK));
+		seq_printf(m, "Crypto Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK));
+		seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_GUNIT_CSME_INTR_MASK));
+
+	} else if (INTEL_GEN(dev_priv) >= 6) {
 		for_each_engine(engine, dev_priv, id) {
 			seq_printf(m,
 				   "Graphics Interrupt mask (%s):	%08x\n",
 				   engine->name, I915_READ_IMR(engine));
 		}
 	}
+
 	intel_runtime_pm_put(dev_priv);
 
 	return 0;
-- 
2.14.1

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  parent reply	other threads:[~2018-02-13 16:38 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-13 16:37 [PATCH 00/20] ICL GEM enabling (v2) Mika Kuoppala
2018-02-13 16:37 ` [PATCH 01/20] drm/i915/icl: Add the ICL PCI IDs Mika Kuoppala
2018-02-13 17:38   ` Michel Thierry
2018-02-13 18:48   ` Anuj Phogat
2018-02-13 16:37 ` [PATCH 02/20] drm/i915/icl: add icelake_init_clock_gating() Mika Kuoppala
2018-02-13 16:37 ` Mika Kuoppala [this message]
2018-02-13 19:44   ` [PATCH 03/20] drm/i915/icl: Show interrupt registers in debugfs Daniele Ceraolo Spurio
2018-02-14  9:55     ` Mika Kuoppala
2018-02-14 11:08   ` Mika Kuoppala
2018-02-13 16:37 ` [PATCH 04/20] drm/i915/icl: Prepare for more rings Mika Kuoppala
2018-02-13 16:37 ` [PATCH 05/20] drm/i915/icl: Interrupt handling Mika Kuoppala
2018-02-13 17:06   ` Chris Wilson
2018-02-13 19:18   ` Daniele Ceraolo Spurio
2018-02-13 21:56     ` Oscar Mateo
2018-02-13 22:02       ` Chris Wilson
2018-02-14 13:37   ` Mika Kuoppala
2018-02-14 14:12   ` [PATCH 05/19] " Mika Kuoppala
2018-02-14 14:25     ` Chris Wilson
2018-02-15 16:24       ` Mika Kuoppala
2018-02-15 16:27     ` Mika Kuoppala
2018-02-15 16:35       ` Tvrtko Ursulin
2018-02-15 17:59       ` Daniele Ceraolo Spurio
2018-02-13 16:37 ` [PATCH 06/20] drm/i915/icl: Ringbuffer interrupt handling Mika Kuoppala
2018-02-13 18:44   ` Daniele Ceraolo Spurio
2018-02-13 16:37 ` [PATCH 07/20] drm/i915/icl: Correctly initialize the Gen11 engines Mika Kuoppala
2018-02-13 16:37 ` [PATCH 08/20] drm/i915/icl: new context descriptor support Mika Kuoppala
2018-02-14 23:34   ` [PATCH v5] " Daniele Ceraolo Spurio
2018-02-13 16:37 ` [PATCH 09/20] drm/i915/icl: Enhanced execution list support Mika Kuoppala
2018-02-13 16:37 ` [PATCH 10/20] drm/i915/icl: Add Indirect Context Offset for Gen11 Mika Kuoppala
2018-02-13 16:37 ` [PATCH 11/20] drm/i915/icl: Gen11 forcewake support Mika Kuoppala
2018-02-13 16:37 ` [PATCH 12/20] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances Mika Kuoppala
2018-02-13 17:13   ` Michal Wajdeczko
2018-02-17  8:51   ` Sagar Arun Kamble
2018-02-17  9:04     ` Chris Wilson
2018-02-17 12:10       ` Sagar Arun Kamble
2018-02-17 12:18         ` Chris Wilson
2018-02-17 14:17           ` Sagar Arun Kamble
2018-02-20 19:16             ` Daniele Ceraolo Spurio
2018-02-21 23:35             ` [PATCH v9] " Oscar Mateo
2018-02-22  6:17               ` Sagar Arun Kamble
2018-02-22 23:05                 ` Oscar Mateo
2018-02-26  5:22                   ` Sagar Arun Kamble
2018-02-26 23:04                     ` Oscar Mateo
2018-02-27  5:49                       ` Sagar Arun Kamble
2018-02-28 17:59                         ` Oscar Mateo
2018-03-01  5:07                           ` Sagar Arun Kamble
2018-02-23  2:21               ` kbuild test robot
2018-02-23  3:03               ` kbuild test robot
2018-02-13 16:37 ` [PATCH 13/20] drm/i915/icl: Enable the extra video decode and enhancement boxes for Icelake 11 Mika Kuoppala
2018-02-13 18:05   ` Michel Thierry
2018-02-13 16:37 ` [PATCH 14/20] drm/i915/icl: Update subslice define for ICL 11 Mika Kuoppala
2018-02-13 16:37 ` [PATCH 15/20] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection Mika Kuoppala
2018-02-13 18:27   ` Lionel Landwerlin
2018-02-13 16:37 ` [PATCH 16/20] drm/i915/icl: Add reset control register changes Mika Kuoppala
2018-02-13 16:37 ` [PATCH 17/20] drm/i915/icl: Add configuring MOCS in new Icelake engines Mika Kuoppala
2018-02-13 18:13   ` Michel Thierry
2018-02-13 16:37 ` [PATCH 18/20] drm/i915/icl: Split out the servicing of the Selector and Shared IIR registers Mika Kuoppala
2018-02-13 16:37 ` [PATCH 19/20] drm/i915/icl: Handle RPS interrupts correctly for Gen11 Mika Kuoppala
2018-02-13 16:37 ` [PATCH 20/20] drm/i915/icl: Enable RC6 and RPS in Gen11 Mika Kuoppala
2018-02-13 17:34 ` ✓ Fi.CI.BAT: success for ICL GEM enabling (v2) Patchwork
2018-02-13 21:36 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-02-14 13:30 ` ✗ Fi.CI.CHECKPATCH: warning for ICL GEM enabling (v2) (rev2) Patchwork
2018-02-14 13:44 ` ✓ Fi.CI.BAT: success " Patchwork
2018-02-14 23:41 ` ✗ Fi.CI.BAT: failure for ICL GEM enabling (v2) (rev4) Patchwork
2018-02-15 17:01 ` ✗ Fi.CI.BAT: failure for ICL GEM enabling (v2) (rev5) Patchwork
2018-02-21 23:59 ` ✗ Fi.CI.BAT: failure for ICL GEM enabling (v2) (rev6) Patchwork

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