From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH 05/20] drm/i915/icl: Interrupt handling
Date: Wed, 14 Feb 2018 15:37:20 +0200 [thread overview]
Message-ID: <873723vgj3.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20180213163738.9055-6-mika.kuoppala@linux.intel.com>
Mika Kuoppala <mika.kuoppala@linux.intel.com> writes:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> v2: Rebase.
>
> v3:
> * Remove DPF, it has been removed from SKL+.
> * Fix -internal rebase wrt. execlists interrupt handling.
>
> v4: Rebase.
>
> v5:
> * Updated for POR changes. (Daniele Ceraolo Spurio)
> * Merged with irq handling fixes by Daniele Ceraolo Spurio:
> * Simplify the code by using gen8_cs_irq_handler.
> * Fix interrupt handling for the upstream kernel.
>
> v6:
> * Remove early bringup debug messages (Tvrtko)
> * Add NB about arbitrary spin wait timeout (Tvrtko)
>
> v7 (from Paulo):
> * Don't try to write RO bits to registers.
> * Don't check for PCH types that don't exist. PCH interrupts are not
> here yet.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 210 ++++++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_pm.c | 7 +-
> 2 files changed, 216 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b886bd459acc..3a1de4e2a941 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -415,6 +415,9 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
> if (READ_ONCE(rps->interrupts_enabled))
> return;
>
> + if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
> + return;
> +
> spin_lock_irq(&dev_priv->irq_lock);
> WARN_ON_ONCE(rps->pm_iir);
> WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
> @@ -431,6 +434,9 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
> if (!READ_ONCE(rps->interrupts_enabled))
> return;
>
> + if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
> + return;
> +
> spin_lock_irq(&dev_priv->irq_lock);
> rps->interrupts_enabled = false;
>
> @@ -2746,6 +2752,131 @@ static void __fini_wedge(struct wedge_me *w)
> (W)->i915; \
> __fini_wedge((W)))
>
> +static __always_inline void
> +gen11_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
> +{
> + gen8_cs_irq_handler(engine, iir, 0);
> +}
> +
> +static irqreturn_t
> +gen11_gt_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> +{
> + irqreturn_t ret = IRQ_NONE;
> + u16 irq[2][32];
> + u32 dw, ident;
> + unsigned long tmp;
> + unsigned int bank, bit, engine;
> + unsigned long wait_start, wait_end;
> +
> + memset(irq, 0, sizeof(irq));
> +
> + for (bank = 0; bank < 2; bank++) {
> + if (master_ctl & GEN11_GT_DW_IRQ(bank)) {
> + dw = I915_READ_FW(GEN11_GT_INTR_DW(bank));
> + if (!dw)
> + DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
> + tmp = dw;
> + for_each_set_bit(bit, &tmp, 32) {
> + I915_WRITE_FW(GEN11_IIR_REG_SELECTOR(bank), 1 << bit);
> + wait_start = local_clock() >> 10;
> + /* NB: Specs do not specify how long to spin wait.
> + * Taking 100us as an educated guess */
> + wait_end = wait_start + 100;
> + do {
> + ident = I915_READ_FW(GEN11_INTR_IDENTITY_REG(bank));
> + } while (!(ident & GEN11_INTR_DATA_VALID) &&
> + !time_after((unsigned long)local_clock() >> 10, wait_end));
> +
> + if (!(ident & GEN11_INTR_DATA_VALID))
> + DRM_ERROR("INTR_IDENTITY_REG%u:%u timed out!\n",
> + bank, bit);
> +
> + irq[bank][bit] = ident & GEN11_INTR_ENGINE_MASK;
> + if (!irq[bank][bit])
> + DRM_ERROR("INTR_IDENTITY_REG%u:%u blank!\n",
> + bank, bit);
> + I915_WRITE_FW(GEN11_INTR_IDENTITY_REG(bank), ident);
> + }
> + I915_WRITE_FW(GEN11_GT_INTR_DW(bank), dw);
> + }
> + }
> +
> + if (irq[0][GEN11_RCS0]) {
> + gen11_cs_irq_handler(dev_priv->engine[RCS],
> + irq[0][GEN11_RCS0]);
> + ret = IRQ_HANDLED;
> + }
> +
> + if (irq[0][GEN11_BCS]) {
> + gen11_cs_irq_handler(dev_priv->engine[BCS],
> + irq[0][GEN11_BCS]);
> + ret = IRQ_HANDLED;
> + }
> +
> + for (engine = 0; engine < 4; engine++) {
> + if (irq[1][GEN11_VCS(engine)]) {
> + gen11_cs_irq_handler(dev_priv->engine[_VCS(engine)],
> + irq[1][GEN11_VCS(engine)]);
> + ret = IRQ_HANDLED;
> + }
> + }
> +
> + for (engine = 0; engine < 2; engine++) {
> + if (irq[1][GEN11_VECS(engine)]) {
> + gen11_cs_irq_handler(dev_priv->engine[_VECS(engine)],
> + irq[1][GEN11_VECS(engine)]);
> + ret = IRQ_HANDLED;
> + }
> + }
> +
> + if (irq[0][GEN11_GTPM] & dev_priv->pm_rps_events) {
> + ret = IRQ_HANDLED;
> + gen6_rps_irq_handler(dev_priv, tmp);
This tmp in here looks like it can't be right.
-Mika
> + }
> +
> + return ret;
> +}
> +
> +static irqreturn_t gen11_irq_handler(int irq, void *arg)
> +{
> + struct drm_device *dev = arg;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 master_ctl;
> + u32 disp_ctl;
> + irqreturn_t ret;
> +
> + if (!intel_irqs_enabled(dev_priv))
> + return IRQ_NONE;
> +
> + master_ctl = I915_READ_FW(GEN11_GFX_MSTR_IRQ);
> +
> + master_ctl &= ~GEN11_MASTER_IRQ;
> + if (!master_ctl)
> + return IRQ_NONE;
> +
> + /* Disable interrupts. */
> + I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, 0);
> +
> + /* IRQs are synced during runtime_suspend, we don't require a wakeref */
> + disable_rpm_wakeref_asserts(dev_priv);
> +
> + /* Find, clear, then process each source of interrupt. */
> + ret = gen11_gt_irq_handler(dev_priv, master_ctl);
> +
> + if (master_ctl & GEN11_DISPLAY_IRQ) {
> + disp_ctl = I915_READ_FW(GEN11_DISPLAY_INT_CTL);
> + ret |= gen8_de_irq_handler(dev_priv, disp_ctl);
> + }
> +
> + /* Acknowledge and enable interrupts. */
> + I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
> + POSTING_READ_FW(GEN11_GFX_MSTR_IRQ);
> +
> + enable_rpm_wakeref_asserts(dev_priv);
> +
> + return ret;
> +}
> +
> /**
> * i915_reset_device - do process context error handling work
> * @dev_priv: i915 device private
> @@ -3159,6 +3290,42 @@ static void gen8_irq_reset(struct drm_device *dev)
> ibx_irq_reset(dev_priv);
> }
>
> +static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
> +{
> + /* Disable RCS, BCS, VCS and VECS class engines. */
> + I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0);
> + I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, 0);
> +
> + /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
> + I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~0);
> + I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~0);
> + I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~0);
> + I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~0);
> + I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~0);
> +}
> +
> +static void gen11_irq_reset(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + int pipe;
> +
> + I915_WRITE(GEN11_GFX_MSTR_IRQ, 0);
> + POSTING_READ(GEN11_GFX_MSTR_IRQ);
> +
> + gen11_gt_irq_reset(dev_priv);
> +
> + I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
> +
> + for_each_pipe(dev_priv, pipe)
> + if (intel_display_power_is_enabled(dev_priv,
> + POWER_DOMAIN_PIPE(pipe)))
> + GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
> +
> + GEN3_IRQ_RESET(GEN8_DE_PORT_);
> + GEN3_IRQ_RESET(GEN8_DE_MISC_);
> + GEN3_IRQ_RESET(GEN8_PCU_);
> +}
> +
> void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> u8 pipe_mask)
> {
> @@ -3656,6 +3823,41 @@ static int gen8_irq_postinstall(struct drm_device *dev)
> return 0;
> }
>
> +static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> + const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
> +
> + BUILD_BUG_ON(irqs & 0xffff0000);
> +
> + /* Enable RCS, BCS, VCS and VECS class interrupts. */
> + I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs);
> + I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, irqs << 16 | irqs);
> +
> + /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
> + I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~(irqs << 16));
> + I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~(irqs << 16));
> + I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~(irqs | irqs << 16));
> + I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~(irqs | irqs << 16));
> + I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~(irqs | irqs << 16));
> +
> + dev_priv->pm_imr = 0xffffffff; /* TODO */
> +}
> +
> +static int gen11_irq_postinstall(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + gen11_gt_irq_postinstall(dev_priv);
> + gen8_de_irq_postinstall(dev_priv);
> +
> + I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
> +
> + I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
> + POSTING_READ(GEN11_GFX_MSTR_IRQ);
> +
> + return 0;
> +}
> +
> static int cherryview_irq_postinstall(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -4104,6 +4306,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> dev->driver->enable_vblank = i965_enable_vblank;
> dev->driver->disable_vblank = i965_disable_vblank;
> dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> + } else if (INTEL_GEN(dev_priv) >= 11) {
> + dev->driver->irq_handler = gen11_irq_handler;
> + dev->driver->irq_preinstall = gen11_irq_reset;
> + dev->driver->irq_postinstall = gen11_irq_postinstall;
> + dev->driver->irq_uninstall = gen11_irq_reset;
> + dev->driver->enable_vblank = gen8_enable_vblank;
> + dev->driver->disable_vblank = gen8_disable_vblank;
> + dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> } else if (INTEL_GEN(dev_priv) >= 8) {
> dev->driver->irq_handler = gen8_irq_handler;
> dev->driver->irq_preinstall = gen8_irq_reset;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d88f107b0d50..087f981461e7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8027,7 +8027,10 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
> dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
> intel_disable_gt_powersave(dev_priv);
>
> - gen6_reset_rps_interrupts(dev_priv);
> + if (INTEL_GEN(dev_priv) < 11)
> + gen6_reset_rps_interrupts(dev_priv);
> + else
> + WARN_ON_ONCE(1);
> }
>
> static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
> @@ -8140,6 +8143,8 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
> cherryview_enable_rps(dev_priv);
> } else if (IS_VALLEYVIEW(dev_priv)) {
> valleyview_enable_rps(dev_priv);
> + } else if (WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11)) {
> + /* TODO */
> } else if (INTEL_GEN(dev_priv) >= 9) {
> gen9_enable_rps(dev_priv);
> } else if (IS_BROADWELL(dev_priv)) {
> --
> 2.14.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2018-02-14 13:39 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-13 16:37 [PATCH 00/20] ICL GEM enabling (v2) Mika Kuoppala
2018-02-13 16:37 ` [PATCH 01/20] drm/i915/icl: Add the ICL PCI IDs Mika Kuoppala
2018-02-13 17:38 ` Michel Thierry
2018-02-13 18:48 ` Anuj Phogat
2018-02-13 16:37 ` [PATCH 02/20] drm/i915/icl: add icelake_init_clock_gating() Mika Kuoppala
2018-02-13 16:37 ` [PATCH 03/20] drm/i915/icl: Show interrupt registers in debugfs Mika Kuoppala
2018-02-13 19:44 ` Daniele Ceraolo Spurio
2018-02-14 9:55 ` Mika Kuoppala
2018-02-14 11:08 ` Mika Kuoppala
2018-02-13 16:37 ` [PATCH 04/20] drm/i915/icl: Prepare for more rings Mika Kuoppala
2018-02-13 16:37 ` [PATCH 05/20] drm/i915/icl: Interrupt handling Mika Kuoppala
2018-02-13 17:06 ` Chris Wilson
2018-02-13 19:18 ` Daniele Ceraolo Spurio
2018-02-13 21:56 ` Oscar Mateo
2018-02-13 22:02 ` Chris Wilson
2018-02-14 13:37 ` Mika Kuoppala [this message]
2018-02-14 14:12 ` [PATCH 05/19] " Mika Kuoppala
2018-02-14 14:25 ` Chris Wilson
2018-02-15 16:24 ` Mika Kuoppala
2018-02-15 16:27 ` Mika Kuoppala
2018-02-15 16:35 ` Tvrtko Ursulin
2018-02-15 17:59 ` Daniele Ceraolo Spurio
2018-02-13 16:37 ` [PATCH 06/20] drm/i915/icl: Ringbuffer interrupt handling Mika Kuoppala
2018-02-13 18:44 ` Daniele Ceraolo Spurio
2018-02-13 16:37 ` [PATCH 07/20] drm/i915/icl: Correctly initialize the Gen11 engines Mika Kuoppala
2018-02-13 16:37 ` [PATCH 08/20] drm/i915/icl: new context descriptor support Mika Kuoppala
2018-02-14 23:34 ` [PATCH v5] " Daniele Ceraolo Spurio
2018-02-13 16:37 ` [PATCH 09/20] drm/i915/icl: Enhanced execution list support Mika Kuoppala
2018-02-13 16:37 ` [PATCH 10/20] drm/i915/icl: Add Indirect Context Offset for Gen11 Mika Kuoppala
2018-02-13 16:37 ` [PATCH 11/20] drm/i915/icl: Gen11 forcewake support Mika Kuoppala
2018-02-13 16:37 ` [PATCH 12/20] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances Mika Kuoppala
2018-02-13 17:13 ` Michal Wajdeczko
2018-02-17 8:51 ` Sagar Arun Kamble
2018-02-17 9:04 ` Chris Wilson
2018-02-17 12:10 ` Sagar Arun Kamble
2018-02-17 12:18 ` Chris Wilson
2018-02-17 14:17 ` Sagar Arun Kamble
2018-02-20 19:16 ` Daniele Ceraolo Spurio
2018-02-21 23:35 ` [PATCH v9] " Oscar Mateo
2018-02-22 6:17 ` Sagar Arun Kamble
2018-02-22 23:05 ` Oscar Mateo
2018-02-26 5:22 ` Sagar Arun Kamble
2018-02-26 23:04 ` Oscar Mateo
2018-02-27 5:49 ` Sagar Arun Kamble
2018-02-28 17:59 ` Oscar Mateo
2018-03-01 5:07 ` Sagar Arun Kamble
2018-02-23 2:21 ` kbuild test robot
2018-02-23 3:03 ` kbuild test robot
2018-02-13 16:37 ` [PATCH 13/20] drm/i915/icl: Enable the extra video decode and enhancement boxes for Icelake 11 Mika Kuoppala
2018-02-13 18:05 ` Michel Thierry
2018-02-13 16:37 ` [PATCH 14/20] drm/i915/icl: Update subslice define for ICL 11 Mika Kuoppala
2018-02-13 16:37 ` [PATCH 15/20] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection Mika Kuoppala
2018-02-13 18:27 ` Lionel Landwerlin
2018-02-13 16:37 ` [PATCH 16/20] drm/i915/icl: Add reset control register changes Mika Kuoppala
2018-02-13 16:37 ` [PATCH 17/20] drm/i915/icl: Add configuring MOCS in new Icelake engines Mika Kuoppala
2018-02-13 18:13 ` Michel Thierry
2018-02-13 16:37 ` [PATCH 18/20] drm/i915/icl: Split out the servicing of the Selector and Shared IIR registers Mika Kuoppala
2018-02-13 16:37 ` [PATCH 19/20] drm/i915/icl: Handle RPS interrupts correctly for Gen11 Mika Kuoppala
2018-02-13 16:37 ` [PATCH 20/20] drm/i915/icl: Enable RC6 and RPS in Gen11 Mika Kuoppala
2018-02-13 17:34 ` ✓ Fi.CI.BAT: success for ICL GEM enabling (v2) Patchwork
2018-02-13 21:36 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-02-14 13:30 ` ✗ Fi.CI.CHECKPATCH: warning for ICL GEM enabling (v2) (rev2) Patchwork
2018-02-14 13:44 ` ✓ Fi.CI.BAT: success " Patchwork
2018-02-14 23:41 ` ✗ Fi.CI.BAT: failure for ICL GEM enabling (v2) (rev4) Patchwork
2018-02-15 17:01 ` ✗ Fi.CI.BAT: failure for ICL GEM enabling (v2) (rev5) Patchwork
2018-02-21 23:59 ` ✗ Fi.CI.BAT: failure for ICL GEM enabling (v2) (rev6) Patchwork
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