From: Manasi Navare <manasi.d.navare@intel.com>
To: Animesh Manna <animesh.manna@intel.com>
Cc: jani.nikula@intel.com, nidhi1.gupta@intel.com,
intel-gfx@lists.freedesktop.org
Subject: Re: [RFC 5/7] drm/i915/dp: Register definition for DP compliance register
Date: Sun, 17 Nov 2019 21:00:16 -0800 [thread overview]
Message-ID: <20191118050016.GD1135@intel.com> (raw)
In-Reply-To: <20191115152549.23047-6-animesh.manna@intel.com>
On Fri, Nov 15, 2019 at 08:55:47PM +0530, Animesh Manna wrote:
> DP_COMP_CTL and DP_COMP_PAT register used to program DP
> compliance pattern.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 478f5ff6c554..87774337c2a2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9772,6 +9772,26 @@ enum skl_power_gate {
> #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
> #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
>
> +/* DDI DP Compliance Control */
> +#define DDI_DP_COMP_CTL_A 0x605F0
> +#define DDI_DP_COMP_CTL_B 0x615F0
> +#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, \
> + DDI_DP_COMP_CTL_B)
> +#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
> +#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
> +#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
> +#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
> +#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
> +#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
> +#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
> +#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
> +
> +/* DDI DP Compliance Pattern */
> +#define DDI_DP_COMP_PAT_A 0x605F4
> +#define DDI_DP_COMP_PAT_B 0x615F4
> +#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, \
> + DDI_DP_COMP_PAT_B) + (i) * 4)
> +
> /* Sideband Interface (SBI) is programmed indirectly, via
> * SBI_ADDR, which contains the register offset; and SBI_DATA,
> * which contains the payload */
> --
> 2.22.0
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Manasi Navare <manasi.d.navare@intel.com>
To: Animesh Manna <animesh.manna@intel.com>
Cc: jani.nikula@intel.com, nidhi1.gupta@intel.com,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC 5/7] drm/i915/dp: Register definition for DP compliance register
Date: Sun, 17 Nov 2019 21:00:16 -0800 [thread overview]
Message-ID: <20191118050016.GD1135@intel.com> (raw)
Message-ID: <20191118050016.hfbuc1_1FwyEXlcjfnwIKvWjFwx_S9Fea_C2WO9vEe4@z> (raw)
In-Reply-To: <20191115152549.23047-6-animesh.manna@intel.com>
On Fri, Nov 15, 2019 at 08:55:47PM +0530, Animesh Manna wrote:
> DP_COMP_CTL and DP_COMP_PAT register used to program DP
> compliance pattern.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 478f5ff6c554..87774337c2a2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9772,6 +9772,26 @@ enum skl_power_gate {
> #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
> #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
>
> +/* DDI DP Compliance Control */
> +#define DDI_DP_COMP_CTL_A 0x605F0
> +#define DDI_DP_COMP_CTL_B 0x615F0
> +#define DDI_DP_COMP_CTL(port) _MMIO_PORT(port, DDI_DP_COMP_CTL_A, \
> + DDI_DP_COMP_CTL_B)
> +#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
> +#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
> +#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
> +#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
> +#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
> +#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
> +#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
> +#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
> +
> +/* DDI DP Compliance Pattern */
> +#define DDI_DP_COMP_PAT_A 0x605F4
> +#define DDI_DP_COMP_PAT_B 0x615F4
> +#define DDI_DP_COMP_PAT(port, i) _MMIO(_PORT(port, DDI_DP_COMP_PAT_A, \
> + DDI_DP_COMP_PAT_B) + (i) * 4)
> +
> /* Sideband Interface (SBI) is programmed indirectly, via
> * SBI_ADDR, which contains the register offset; and SBI_DATA,
> * which contains the payload */
> --
> 2.22.0
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-18 4:57 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-15 15:25 [RFC 0/7] DP Phy compliace auto test Animesh Manna
2019-11-15 15:25 ` [Intel-gfx] " Animesh Manna
2019-11-15 15:25 ` [RFC 1/7] drm/dp: get/set phy compliance pattern Animesh Manna
2019-11-15 15:25 ` [Intel-gfx] " Animesh Manna
2019-11-18 4:04 ` Manasi Navare
2019-11-18 4:04 ` [Intel-gfx] " Manasi Navare
2019-11-18 18:39 ` Animesh Manna
2019-11-18 18:39 ` [Intel-gfx] " Animesh Manna
2019-11-15 15:25 ` [RFC 2/7] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation Animesh Manna
2019-11-15 15:25 ` [Intel-gfx] " Animesh Manna
2019-11-15 15:25 ` [RFC 3/7] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
2019-11-15 15:25 ` [Intel-gfx] " Animesh Manna
2019-11-18 4:47 ` Manasi Navare
2019-11-18 4:47 ` [Intel-gfx] " Manasi Navare
2019-11-15 15:25 ` [RFC 4/7] drm/i915/dp: Notify testapp using uevent and debugfs entry Animesh Manna
2019-11-15 15:25 ` [Intel-gfx] " Animesh Manna
2019-11-18 4:58 ` Manasi Navare
2019-11-18 4:58 ` [Intel-gfx] " Manasi Navare
2019-11-18 5:06 ` Manasi Navare
2019-11-18 5:06 ` [Intel-gfx] " Manasi Navare
2019-11-18 18:45 ` Animesh Manna
2019-11-18 18:45 ` [Intel-gfx] " Animesh Manna
2019-11-15 15:25 ` [RFC 5/7] drm/i915/dp: Register definition for DP compliance register Animesh Manna
2019-11-15 15:25 ` [Intel-gfx] " Animesh Manna
2019-11-18 5:00 ` Manasi Navare [this message]
2019-11-18 5:00 ` Manasi Navare
2019-11-15 15:25 ` [RFC 6/7] drm/i915/dp: Update the pattern as per request Animesh Manna
2019-11-15 15:25 ` [Intel-gfx] " Animesh Manna
2019-11-18 6:41 ` Manasi Navare
2019-11-18 6:41 ` [Intel-gfx] " Manasi Navare
2019-11-18 18:47 ` Animesh Manna
2019-11-18 18:47 ` [Intel-gfx] " Animesh Manna
2019-12-11 23:44 ` Manasi Navare
2019-11-15 15:25 ` [RFC 7/7] drm/i915/dp: Program vswing, pre-emphasis, test-pattern Animesh Manna
2019-11-15 15:25 ` [Intel-gfx] " Animesh Manna
2019-11-18 7:53 ` Manasi Navare
2019-11-18 7:53 ` [Intel-gfx] " Manasi Navare
2019-12-11 23:50 ` Manasi Navare
2019-12-13 17:24 ` Animesh Manna
2020-01-14 21:38 ` Manasi Navare
2020-01-20 13:53 ` Manna, Animesh
2020-01-24 0:56 ` Manasi Navare
2019-11-15 19:27 ` ✗ Fi.CI.BUILD: failure for DP Phy compliace auto test Patchwork
2019-11-15 19:27 ` [Intel-gfx] " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191118050016.GD1135@intel.com \
--to=manasi.d.navare@intel.com \
--cc=animesh.manna@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
--cc=nidhi1.gupta@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.