From: Manasi Navare <manasi.d.navare@intel.com> To: Animesh Manna <animesh.manna@intel.com> Cc: jani.nikula@intel.com, nidhi1.gupta@intel.com, intel-gfx@lists.freedesktop.org Subject: Re: [RFC 6/7] drm/i915/dp: Update the pattern as per request Date: Sun, 17 Nov 2019 22:41:47 -0800 [thread overview] Message-ID: <20191118064147.GF1135@intel.com> (raw) In-Reply-To: <20191115152549.23047-7-animesh.manna@intel.com> On Fri, Nov 15, 2019 at 08:55:48PM +0530, Animesh Manna wrote: > set pattern in DP_COMP_CTL. It would be nice to have some brief description here on context of setting a PHY pattern for PHY compliance and that this will be called during pre enable in atomic commit in case of phy compliance request etc..and that the requested phy pattern is read during test handling etc.. something that gives a reader a better idea of the context of this function > > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 55 +++++++++++++++++++++++++ > 1 file changed, 55 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index a2b860cf3b93..df31278a1619 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -4955,6 +4955,61 @@ static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp) > return DP_TEST_ACK; > } > > +static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *dev_priv = > + to_i915(dp_to_dig_port(intel_dp)->base.base.dev); > + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > + struct drm_dp_phy_test_params *data = > + &intel_dp->compliance.test_data.phytest; > + u32 temp; > + > + switch (data->phy_pattern) { > + case DP_PHY_TEST_PATTERN_NONE: > + DRM_DEBUG_KMS("Disable Phy Test Pattern\n"); > + I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), 0x0); > + break; > + case DP_PHY_TEST_PATTERN_D10_2: > + DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n"); > + I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), > + DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2); > + break; > + case DP_PHY_TEST_PATTERN_ERROR_COUNT: > + DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n"); > + I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), > + DDI_DP_COMP_CTL_ENABLE | > + DDI_DP_COMP_CTL_SCRAMBLED_0); > + break; > + case DP_PHY_TEST_PATTERN_PRBS7: > + DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n"); > + I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), > + DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7); > + break; > + case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: > + DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern\n"); > + temp = ((data->custom80[0] << 24) | (data->custom80[1] << 16) | > + (data->custom80[2] << 8) | (data->custom80[3])); > + I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 0), temp); > + temp = ((data->custom80[4] << 24) | (data->custom80[5] << 16) | > + (data->custom80[6] << 8) | (data->custom80[7])); > + I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 1), temp); > + temp = ((data->custom80[8] << 8) | data->custom80[9]); > + I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 2), temp); > + I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), > + DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80); > + break; > + case DP_PHY_TEST_PATTERN_CP2520: > + DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n"); > + temp = ((data->hbr2_reset[1] << 8) | data->hbr2_reset[0]); > + I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), > + DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | > + temp); > + break; > + default: > + DRM_ERROR("Invalid Phy Test PAttern\n"); Here we would definitely want a WARN since ERROR at this point in commit is not good Other than looks good to me. Manasi > + } > +} > + > static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) > { > u8 test_result = DP_TEST_NAK; > -- > 2.22.0 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Manasi Navare <manasi.d.navare@intel.com> To: Animesh Manna <animesh.manna@intel.com> Cc: jani.nikula@intel.com, nidhi1.gupta@intel.com, intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [RFC 6/7] drm/i915/dp: Update the pattern as per request Date: Sun, 17 Nov 2019 22:41:47 -0800 [thread overview] Message-ID: <20191118064147.GF1135@intel.com> (raw) Message-ID: <20191118064147.Chi_j9D47Ve9s0UkKDQGwzr6yAZruu3lyWfQ_YQFO3A@z> (raw) In-Reply-To: <20191115152549.23047-7-animesh.manna@intel.com> On Fri, Nov 15, 2019 at 08:55:48PM +0530, Animesh Manna wrote: > set pattern in DP_COMP_CTL. It would be nice to have some brief description here on context of setting a PHY pattern for PHY compliance and that this will be called during pre enable in atomic commit in case of phy compliance request etc..and that the requested phy pattern is read during test handling etc.. something that gives a reader a better idea of the context of this function > > Signed-off-by: Animesh Manna <animesh.manna@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 55 +++++++++++++++++++++++++ > 1 file changed, 55 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index a2b860cf3b93..df31278a1619 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -4955,6 +4955,61 @@ static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp) > return DP_TEST_ACK; > } > > +static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) > +{ > + struct drm_i915_private *dev_priv = > + to_i915(dp_to_dig_port(intel_dp)->base.base.dev); > + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > + struct drm_dp_phy_test_params *data = > + &intel_dp->compliance.test_data.phytest; > + u32 temp; > + > + switch (data->phy_pattern) { > + case DP_PHY_TEST_PATTERN_NONE: > + DRM_DEBUG_KMS("Disable Phy Test Pattern\n"); > + I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), 0x0); > + break; > + case DP_PHY_TEST_PATTERN_D10_2: > + DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n"); > + I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), > + DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2); > + break; > + case DP_PHY_TEST_PATTERN_ERROR_COUNT: > + DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n"); > + I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), > + DDI_DP_COMP_CTL_ENABLE | > + DDI_DP_COMP_CTL_SCRAMBLED_0); > + break; > + case DP_PHY_TEST_PATTERN_PRBS7: > + DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n"); > + I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), > + DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7); > + break; > + case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: > + DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern\n"); > + temp = ((data->custom80[0] << 24) | (data->custom80[1] << 16) | > + (data->custom80[2] << 8) | (data->custom80[3])); > + I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 0), temp); > + temp = ((data->custom80[4] << 24) | (data->custom80[5] << 16) | > + (data->custom80[6] << 8) | (data->custom80[7])); > + I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 1), temp); > + temp = ((data->custom80[8] << 8) | data->custom80[9]); > + I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 2), temp); > + I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), > + DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80); > + break; > + case DP_PHY_TEST_PATTERN_CP2520: > + DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n"); > + temp = ((data->hbr2_reset[1] << 8) | data->hbr2_reset[0]); > + I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), > + DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | > + temp); > + break; > + default: > + DRM_ERROR("Invalid Phy Test PAttern\n"); Here we would definitely want a WARN since ERROR at this point in commit is not good Other than looks good to me. Manasi > + } > +} > + > static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) > { > u8 test_result = DP_TEST_NAK; > -- > 2.22.0 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-18 6:38 UTC|newest] Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-15 15:25 [RFC 0/7] DP Phy compliace auto test Animesh Manna 2019-11-15 15:25 ` [Intel-gfx] " Animesh Manna 2019-11-15 15:25 ` [RFC 1/7] drm/dp: get/set phy compliance pattern Animesh Manna 2019-11-15 15:25 ` [Intel-gfx] " Animesh Manna 2019-11-18 4:04 ` Manasi Navare 2019-11-18 4:04 ` [Intel-gfx] " Manasi Navare 2019-11-18 18:39 ` Animesh Manna 2019-11-18 18:39 ` [Intel-gfx] " Animesh Manna 2019-11-15 15:25 ` [RFC 2/7] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation Animesh Manna 2019-11-15 15:25 ` [Intel-gfx] " Animesh Manna 2019-11-15 15:25 ` [RFC 3/7] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna 2019-11-15 15:25 ` [Intel-gfx] " Animesh Manna 2019-11-18 4:47 ` Manasi Navare 2019-11-18 4:47 ` [Intel-gfx] " Manasi Navare 2019-11-15 15:25 ` [RFC 4/7] drm/i915/dp: Notify testapp using uevent and debugfs entry Animesh Manna 2019-11-15 15:25 ` [Intel-gfx] " Animesh Manna 2019-11-18 4:58 ` Manasi Navare 2019-11-18 4:58 ` [Intel-gfx] " Manasi Navare 2019-11-18 5:06 ` Manasi Navare 2019-11-18 5:06 ` [Intel-gfx] " Manasi Navare 2019-11-18 18:45 ` Animesh Manna 2019-11-18 18:45 ` [Intel-gfx] " Animesh Manna 2019-11-15 15:25 ` [RFC 5/7] drm/i915/dp: Register definition for DP compliance register Animesh Manna 2019-11-15 15:25 ` [Intel-gfx] " Animesh Manna 2019-11-18 5:00 ` Manasi Navare 2019-11-18 5:00 ` [Intel-gfx] " Manasi Navare 2019-11-15 15:25 ` [RFC 6/7] drm/i915/dp: Update the pattern as per request Animesh Manna 2019-11-15 15:25 ` [Intel-gfx] " Animesh Manna 2019-11-18 6:41 ` Manasi Navare [this message] 2019-11-18 6:41 ` Manasi Navare 2019-11-18 18:47 ` Animesh Manna 2019-11-18 18:47 ` [Intel-gfx] " Animesh Manna 2019-12-11 23:44 ` Manasi Navare 2019-11-15 15:25 ` [RFC 7/7] drm/i915/dp: Program vswing, pre-emphasis, test-pattern Animesh Manna 2019-11-15 15:25 ` [Intel-gfx] " Animesh Manna 2019-11-18 7:53 ` Manasi Navare 2019-11-18 7:53 ` [Intel-gfx] " Manasi Navare 2019-12-11 23:50 ` Manasi Navare 2019-12-13 17:24 ` Animesh Manna 2020-01-14 21:38 ` Manasi Navare 2020-01-20 13:53 ` Manna, Animesh 2020-01-24 0:56 ` Manasi Navare 2019-11-15 19:27 ` ✗ Fi.CI.BUILD: failure for DP Phy compliace auto test Patchwork 2019-11-15 19:27 ` [Intel-gfx] " Patchwork
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