From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 4/9] drm/i915: s/blob_data/lut/
Date: Tue, 3 Mar 2020 19:33:08 +0200 [thread overview]
Message-ID: <20200303173313.28117-5-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20200303173313.28117-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We're talking about LUT contents here so let's call the thing
'lut' rather than 'blob_data'. This is the name the load_lut()
code used before already.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 66 +++++++++++-----------
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index e3abaa1908a9..f90f113355bc 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1694,7 +1694,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
- struct drm_color_lut *blob_data;
+ struct drm_color_lut *lut;
u32 i, val;
blob = drm_property_create_blob(&dev_priv->drm,
@@ -1703,16 +1703,16 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
if (IS_ERR(blob))
return NULL;
- blob_data = blob->data;
+ lut = blob->data;
for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
val = intel_de_read(dev_priv, PALETTE(pipe, i));
- blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+ lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
LGC_PALETTE_RED_MASK, val), 8);
- blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+ lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
LGC_PALETTE_GREEN_MASK, val), 8);
- blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+ lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
LGC_PALETTE_BLUE_MASK, val), 8);
}
@@ -1735,7 +1735,7 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
- struct drm_color_lut *blob_data;
+ struct drm_color_lut *lut;
u32 i, val1, val2;
blob = drm_property_create_blob(&dev_priv->drm,
@@ -1744,25 +1744,25 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
if (IS_ERR(blob))
return NULL;
- blob_data = blob->data;
+ lut = blob->data;
for (i = 0; i < lut_size - 1; i++) {
val1 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
val2 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
- blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
+ lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
REG_FIELD_GET(PALETTE_RED_MASK, val1);
- blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
+ lut[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
- blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
+ lut[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
}
- blob_data[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
+ lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
intel_de_read(dev_priv, PIPEGCMAX(pipe, 0)));
- blob_data[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
+ lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
intel_de_read(dev_priv, PIPEGCMAX(pipe, 1)));
- blob_data[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
+ lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
intel_de_read(dev_priv, PIPEGCMAX(pipe, 2)));
return blob;
@@ -1787,7 +1787,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
- struct drm_color_lut *blob_data;
+ struct drm_color_lut *lut;
u32 i, val;
blob = drm_property_create_blob(&dev_priv->drm,
@@ -1796,17 +1796,17 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
if (IS_ERR(blob))
return NULL;
- blob_data = blob->data;
+ lut = blob->data;
for (i = 0; i < lut_size; i++) {
val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
- blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+ lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
- blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+ lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1));
- blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+ lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
CGM_PIPE_GAMMA_RED_MASK, val), 10);
}
@@ -1828,7 +1828,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
- struct drm_color_lut *blob_data;
+ struct drm_color_lut *lut;
u32 i, val;
blob = drm_property_create_blob(&dev_priv->drm,
@@ -1837,16 +1837,16 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
if (IS_ERR(blob))
return NULL;
- blob_data = blob->data;
+ lut = blob->data;
for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
- blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+ lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
LGC_PALETTE_RED_MASK, val), 8);
- blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+ lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
LGC_PALETTE_GREEN_MASK, val), 8);
- blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+ lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
LGC_PALETTE_BLUE_MASK, val), 8);
}
@@ -1861,7 +1861,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
- struct drm_color_lut *blob_data;
+ struct drm_color_lut *lut;
u32 i, val;
blob = drm_property_create_blob(&dev_priv->drm,
@@ -1870,16 +1870,16 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
if (IS_ERR(blob))
return NULL;
- blob_data = blob->data;
+ lut = blob->data;
for (i = 0; i < lut_size; i++) {
val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i));
- blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+ lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
PREC_PALETTE_RED_MASK, val), 10);
- blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+ lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
PREC_PALETTE_GREEN_MASK, val), 10);
- blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+ lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
PREC_PALETTE_BLUE_MASK, val), 10);
}
@@ -1908,7 +1908,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
int hw_lut_size = ivb_lut_10_size(prec_index);
enum pipe pipe = crtc->pipe;
struct drm_property_blob *blob;
- struct drm_color_lut *blob_data;
+ struct drm_color_lut *lut;
u32 i, val;
blob = drm_property_create_blob(&dev_priv->drm,
@@ -1917,7 +1917,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
if (IS_ERR(blob))
return NULL;
- blob_data = blob->data;
+ lut = blob->data;
intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
prec_index | PAL_PREC_AUTO_INCREMENT);
@@ -1925,11 +1925,11 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
for (i = 0; i < hw_lut_size; i++) {
val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
- blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+ lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
PREC_PAL_DATA_RED_MASK, val), 10);
- blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+ lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
PREC_PAL_DATA_GREEN_MASK, val), 10);
- blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+ lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
PREC_PAL_DATA_BLUE_MASK, val), 10);
}
--
2.24.1
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next prev parent reply other threads:[~2020-03-03 17:33 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 1/9] drm/i915: Polish CHV CGM CSC loading Ville Syrjala
2020-03-06 8:44 ` Sharma, Swati2
2020-03-06 11:49 ` Ville Syrjälä
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 2/9] drm/i915: Clean up i9xx_load_luts_internal() Ville Syrjala
2020-03-06 14:42 ` Sharma, Swati2
2020-03-06 14:46 ` Ville Syrjälä
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 3/9] drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants Ville Syrjala
2020-03-04 2:54 ` kbuild test robot
2020-03-04 2:54 ` kbuild test robot
2020-03-04 11:51 ` Ville Syrjälä
2020-03-04 11:51 ` Ville Syrjälä
2020-03-06 15:00 ` Sharma, Swati2
2020-03-03 17:33 ` Ville Syrjala [this message]
2020-03-06 15:03 ` [Intel-gfx] [PATCH v2 4/9] drm/i915: s/blob_data/lut/ Sharma, Swati2
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 5/9] drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/ Ville Syrjala
2020-03-06 15:18 ` Sharma, Swati2
2020-03-06 15:32 ` Ville Syrjälä
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 6/9] drm/i915: Clean up integer types in color code Ville Syrjala
2020-03-06 15:24 ` Sharma, Swati2
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 7/9] drm/i915: Refactor LUT read functions Ville Syrjala
2020-03-06 15:28 ` Sharma, Swati2
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 8/9] drm/i915: Fix readout of PIPEGCMAX Ville Syrjala
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 9/9] drm/i915: Pass the crtc to the low level read_lut() funcs Ville Syrjala
2020-03-06 15:36 ` Sharma, Swati2
2020-03-03 19:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups (rev3) Patchwork
2020-03-03 19:38 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2020-03-03 20:00 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-03-06 15:40 ` [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Sharma, Swati2
2020-03-09 20:26 ` Ville Syrjälä
2020-03-07 0:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups (rev4) Patchwork
2020-03-07 0:27 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2020-03-07 0:45 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-03-09 13:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-09 19:27 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-03-09 19:46 ` Patchwork
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