From: "Sharma, Swati2" <swati2.sharma@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 7/9] drm/i915: Refactor LUT read functions
Date: Fri, 6 Mar 2020 20:58:47 +0530 [thread overview]
Message-ID: <2f7e752d-ded0-f964-0f31-aecbca0a4f5e@intel.com> (raw)
In-Reply-To: <20200303173313.28117-8-ville.syrjala@linux.intel.com>
On 03-Mar-20 11:03 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract all the 'hw value -> LUT entry' stuff into small helpers
> to make the main 'read out the entire LUT' loop less bogged down
> by such mundane details.
>
Wow!
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Swati Sharma <swati2.sharma@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 122 +++++++++++----------
> 1 file changed, 62 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 934f00817c5c..8796f04e23a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -387,6 +387,19 @@ static void chv_load_cgm_csc(struct intel_crtc *crtc,
> coeffs[8]);
> }
>
> +/* convert hw value with given bit_precision to lut property val */
> +static u32 intel_color_lut_pack(u32 val, int bit_precision)
> +{
> + u32 max = 0xffff >> (16 - bit_precision);
> +
> + val = clamp_val(val, 0, max);
> +
> + if (bit_precision < 16)
> + val <<= 16 - bit_precision;
> +
> + return val;
> +}
> +
> static u32 i9xx_lut_8(const struct drm_color_lut *color)
> {
> return drm_color_lut_extract(color->red, 8) << 16 |
> @@ -394,6 +407,13 @@ static u32 i9xx_lut_8(const struct drm_color_lut *color)
> drm_color_lut_extract(color->blue, 8);
> }
>
> +static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val)
> +{
> + entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8);
> + entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8);
> + entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8);
> +}
> +
> /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
> static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
> {
> @@ -410,6 +430,21 @@ static u32 i965_lut_10p6_udw(const struct drm_color_lut *color)
> (color->blue >> 8);
> }
>
> +static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
> +{
> + entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 |
> + REG_FIELD_GET(PALETTE_RED_MASK, ldw);
> + entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 |
> + REG_FIELD_GET(PALETTE_GREEN_MASK, ldw);
> + entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 |
> + REG_FIELD_GET(PALETTE_BLUE_MASK, ldw);
> +}
> +
> +static u16 i965_lut_11p6_max_pack(u32 val)
> +{
> + return REG_FIELD_GET(PIPEGCMAX_RGB_MASK, val);
> +}
> +
> static u32 ilk_lut_10(const struct drm_color_lut *color)
> {
> return drm_color_lut_extract(color->red, 10) << 20 |
> @@ -417,6 +452,13 @@ static u32 ilk_lut_10(const struct drm_color_lut *color)
> drm_color_lut_extract(color->blue, 10);
> }
>
> +static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
> +{
> + entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10);
> + entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10);
> + entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
> +}
> +
> static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -983,6 +1025,13 @@ static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
> return drm_color_lut_extract(color->red, 14);
> }
>
> +static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
> +{
> + entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10);
> + entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10);
> + entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10);
> +}
> +
> static void chv_load_cgm_degamma(struct intel_crtc *crtc,
> const struct drm_property_blob *blob)
> {
> @@ -1672,19 +1721,6 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
> return true;
> }
>
> -/* convert hw value with given bit_precision to lut property val */
> -static u32 intel_color_lut_pack(u32 val, int bit_precision)
> -{
> - u32 max = 0xffff >> (16 - bit_precision);
> -
> - val = clamp_val(val, 0, max);
> -
> - if (bit_precision < 16)
> - val <<= 16 - bit_precision;
> -
> - return val;
> -}
> -
> static struct drm_property_blob *
> i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
> {
> @@ -1706,12 +1742,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
> for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
> u32 val = intel_de_read(dev_priv, PALETTE(pipe, i));
>
> - lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
> - LGC_PALETTE_RED_MASK, val), 8);
> - lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
> - LGC_PALETTE_GREEN_MASK, val), 8);
> - lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
> - LGC_PALETTE_BLUE_MASK, val), 8);
> + i9xx_lut_8_pack(&lut[i], val);
> }
>
> return blob;
> @@ -1744,23 +1775,15 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
> lut = blob->data;
>
> for (i = 0; i < lut_size - 1; i++) {
> - u32 val1 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
> - u32 val2 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
> + u32 ldw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
> + u32 udw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
>
> - lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
> - REG_FIELD_GET(PALETTE_RED_MASK, val1);
> - lut[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
> - REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
> - lut[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
> - REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
> + i965_lut_10p6_pack(&lut[i], ldw, udw);
> }
>
> - lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
> - intel_de_read(dev_priv, PIPEGCMAX(pipe, 0)));
> - lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
> - intel_de_read(dev_priv, PIPEGCMAX(pipe, 1)));
> - lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
> - intel_de_read(dev_priv, PIPEGCMAX(pipe, 2)));
> + lut[i].red = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 0)));
> + lut[i].green = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 1)));
> + lut[i].blue = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 2)));
>
> return blob;
> }
> @@ -1795,16 +1818,10 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
> lut = blob->data;
>
> for (i = 0; i < lut_size; i++) {
> - u32 val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
> + u32 ldw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
> + u32 udw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1));
>
> - lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
> - CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
> - lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
> - CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
> -
> - val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1));
> - lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
> - CGM_PIPE_GAMMA_RED_MASK, val), 10);
> + chv_cgm_gamma_pack(&lut[i], ldw, udw);
> }
>
> return blob;
> @@ -1839,12 +1856,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
> for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
> u32 val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
>
> - lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
> - LGC_PALETTE_RED_MASK, val), 8);
> - lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
> - LGC_PALETTE_GREEN_MASK, val), 8);
> - lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
> - LGC_PALETTE_BLUE_MASK, val), 8);
> + i9xx_lut_8_pack(&lut[i], val);
> }
>
> return blob;
> @@ -1871,12 +1883,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
> for (i = 0; i < lut_size; i++) {
> u32 val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i));
>
> - lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
> - PREC_PALETTE_RED_MASK, val), 10);
> - lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
> - PREC_PALETTE_GREEN_MASK, val), 10);
> - lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
> - PREC_PALETTE_BLUE_MASK, val), 10);
> + ilk_lut_10_pack(&lut[i], val);
> }
>
> return blob;
> @@ -1920,12 +1927,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
> for (i = 0; i < hw_lut_size; i++) {
> u32 val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
>
> - lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
> - PREC_PAL_DATA_RED_MASK, val), 10);
> - lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
> - PREC_PAL_DATA_GREEN_MASK, val), 10);
> - lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
> - PREC_PAL_DATA_BLUE_MASK, val), 10);
> + ilk_lut_10_pack(&lut[i], val);
> }
>
> intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
>
--
~Swati Sharma
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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next prev parent reply other threads:[~2020-03-06 15:28 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 1/9] drm/i915: Polish CHV CGM CSC loading Ville Syrjala
2020-03-06 8:44 ` Sharma, Swati2
2020-03-06 11:49 ` Ville Syrjälä
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 2/9] drm/i915: Clean up i9xx_load_luts_internal() Ville Syrjala
2020-03-06 14:42 ` Sharma, Swati2
2020-03-06 14:46 ` Ville Syrjälä
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 3/9] drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants Ville Syrjala
2020-03-04 2:54 ` kbuild test robot
2020-03-04 2:54 ` kbuild test robot
2020-03-04 11:51 ` Ville Syrjälä
2020-03-04 11:51 ` Ville Syrjälä
2020-03-06 15:00 ` Sharma, Swati2
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 4/9] drm/i915: s/blob_data/lut/ Ville Syrjala
2020-03-06 15:03 ` Sharma, Swati2
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 5/9] drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/ Ville Syrjala
2020-03-06 15:18 ` Sharma, Swati2
2020-03-06 15:32 ` Ville Syrjälä
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 6/9] drm/i915: Clean up integer types in color code Ville Syrjala
2020-03-06 15:24 ` Sharma, Swati2
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 7/9] drm/i915: Refactor LUT read functions Ville Syrjala
2020-03-06 15:28 ` Sharma, Swati2 [this message]
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 8/9] drm/i915: Fix readout of PIPEGCMAX Ville Syrjala
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 9/9] drm/i915: Pass the crtc to the low level read_lut() funcs Ville Syrjala
2020-03-06 15:36 ` Sharma, Swati2
2020-03-03 19:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups (rev3) Patchwork
2020-03-03 19:38 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2020-03-03 20:00 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-03-06 15:40 ` [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Sharma, Swati2
2020-03-09 20:26 ` Ville Syrjälä
2020-03-07 0:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups (rev4) Patchwork
2020-03-07 0:27 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2020-03-07 0:45 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-03-09 13:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-09 19:27 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-03-09 19:46 ` Patchwork
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