From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: peter.maydell@linaro.org, richard.henderson@linaro.org,
wxy194768@alibaba-inc.com, chihmin.chao@sifive.com,
wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com,
alex.bennee@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH 01/11] riscv: Add RV64I instructions description
Date: Sun, 12 Jul 2020 00:16:45 +0800 [thread overview]
Message-ID: <20200711161655.2856-2-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com>
Avoid using stack pointer(x2), thread pointer(x3), global pointer(x4),
as they are not under control of risu.
Besides, avoid using x0 as base address register, because we can't
emit a valid random address by setting x0.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
rv64.risu | 141 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 141 insertions(+)
create mode 100644 rv64.risu
diff --git a/rv64.risu b/rv64.risu
new file mode 100644
index 0000000..edf0d1f
--- /dev/null
+++ b/rv64.risu
@@ -0,0 +1,141 @@
+# Input file for risugen defining RISC-V instructions
+.mode riscv.rv64
+@RV64I
+
+# x2 stack pointer, x3 global pointer, x4 thread pointer
+# These registers should be reserved for signal handler.
+
+LUI RISCV imm:20 rd:5 0110111 \
+!constraints { greg($rd); }
+
+AUIPC RISCV imm:20 rd:5 0110111 \
+!constraints { greg($rd); }
+
+# Limit to current implementation, the base address register will be overide
+LB RISCV imm:12 rs1:5 000 rd:5 0000011 \
+!constraints { greg($rd) && gbase($rs1); } \
+!memory { align(1); reg_plus_imm($rs1, sextract($imm, 12), $rd); }
+
+LH RISCV imm:12 rs1:5 001 rd:5 0000011 \
+!constraints { greg($rd) && gbase($rs1); } \
+!memory { align(2); reg_plus_imm($rs1, sextract($imm, 12), $rd); }
+
+LW RISCV imm:12 rs1:5 010 rd:5 0000011 \
+!constraints { greg($rd) && gbase($rs1); } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12), $rd); }
+
+LBU RISCV imm:12 rs1:5 100 rd:5 0000011 \
+!constraints { greg($rd) && gbase($rs1); } \
+!memory { align(1); reg_plus_imm($rs1, sextract($imm, 12), $rd); }
+
+LHU RISCV imm:12 rs1:5 101 rd:5 0000011 \
+!constraints { greg($rd) && gbase($rs1); } \
+!memory { align(2); reg_plus_imm($rs1, sextract($imm, 12), $rd); }
+
+SB RISCV imm5:7 rs2:5 rs1:5 000 imm:5 0100011 \
+!constraints { greg($rs2) && gbase($rs1) && $rs2 != $rs1; } \
+!memory { align(1); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+SH RISCV imm5:7 rs2:5 rs1:5 001 imm:5 0100011 \
+!constraints { greg($rs2) && gbase($rs1) && $rs2 != $rs1; } \
+!memory { align(2); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+SW RISCV imm5:7 rs2:5 rs1:5 010 imm:5 0100011 \
+!constraints { greg($rs2) && gbase($rs1) && $rs2 != $rs1; } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+ADDI RISCV imm:12 rs1:5 000 rd:5 0010011 \
+!constraints { greg($rd) && greg($rs1); }
+
+SLTI RISCV imm:12 rs1:5 010 rd:5 0010011 \
+!constraints { greg($rd) && greg($rs1); }
+
+SLTIU RISCV imm:12 rs1:5 011 rd:5 0010011 \
+!constraints { greg($rd) && greg($rs1); }
+
+XORI RISCV imm:12 rs1:5 100 rd:5 0010011 \
+!constraints { greg($rd) && greg($rs1); }
+
+ORI RISCV imm:12 rs1:5 110 rd:5 0010011 \
+!constraints { greg($rd) && greg($rs1); }
+
+ANDI RISCV imm:12 rs1:5 111 rd:5 0010011 \
+!constraints { greg($rd) && greg($rs1); }
+
+ADD RISCV 0000000 rs2:5 rs1:5 000 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SUB RISCV 0100000 rs2:5 rs1:5 000 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SLL RISCV 0000000 rs2:5 rs1:5 001 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SLT RISCV 0000000 rs2:5 rs1:5 010 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SLTU RISCV 0000000 rs2:5 rs1:5 011 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+XOR RISCV 0000000 rs2:5 rs1:5 100 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SRL RISCV 0000000 rs2:5 rs1:5 101 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SRA RISCV 0100000 rs2:5 rs1:5 101 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+OR RISCV 0000000 rs2:5 rs1:5 110 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+AND RISCV 0000000 rs2:5 rs1:5 111 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+LWU RISCV imm:12 rs1:5 110 rd:5 0000011 \
+!constraints { greg($rd) && gbase($rs1); } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12), $rd); }
+
+LD RISCV imm:12 rs1:5 011 rd:5 0000011 \
+!constraints { greg($rd) && gbase($rs1); } \
+!memory { align(8); reg_plus_imm($rs1, sextract($imm, 12), $rd); }
+
+SD RISCV imm5:7 rs2:5 rs1:5 011 imm:5 0100011 \
+!constraints { greg($rs2) && gbase($rs1) && $rs2 != $rs1; } \
+!memory { align(8); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+SLLI RISCV 00000 sham5:7 rs1:5 001 rd:5 0010011 \
+!constraints { greg($rd) && greg($rs1); }
+
+SRLI RISCV 00000 sham5:7 rs1:5 101 rd:5 0010011 \
+!constraints { greg($rd) && greg($rs1); }
+
+SRAI RISCV 01000 sham5:7 rs1:5 101 rd:5 0010011 \
+!constraints { greg($rd) && greg($rs1); }
+
+ADDIW RISCV imm:12 rs1:5 000 rd:5 0011011 \
+!constraints { greg($rd) && greg($rs1); }
+
+SLLIW RISCV 0000000 shamt:5 rs1:5 001 rd:5 0011011 \
+!constraints { greg($rd) && greg($rs1); }
+
+SRLIW RISCV 0000000 shamt:5 rs1:5 101 rd:5 0011011 \
+!constraints { greg($rd) && greg($rs1); }
+
+SRAIW RISCV 0100000 shamt:5 rs1:5 101 rd:5 0011011 \
+!constraints { greg($rd) && greg($rs1); }
+
+ADDW RISCV 0000000 rs2:5 rs1:5 000 rd:5 0011011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SUBW RISCV 0100000 rs2:5 rs1:5 000 rd:5 0011011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SLLW RISCV 0000000 rs2:5 rs1:5 001 rd:5 0011011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SRLW RISCV 0000000 rs2:5 rs1:5 101 rd:5 0011011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SRAW RISCV 0100000 rs2:5 rs1:5 101 rd:5 0011011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
--
2.23.0
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: richard.henderson@linaro.org, Alistair.Francis@wdc.com,
chihmin.chao@sifive.com, alex.bennee@linaro.org,
peter.maydell@linaro.org, wenmeng_zhang@c-sky.com,
wxy194768@alibaba-inc.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH 01/11] riscv: Add RV64I instructions description
Date: Sun, 12 Jul 2020 00:16:45 +0800 [thread overview]
Message-ID: <20200711161655.2856-2-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com>
Avoid using stack pointer(x2), thread pointer(x3), global pointer(x4),
as they are not under control of risu.
Besides, avoid using x0 as base address register, because we can't
emit a valid random address by setting x0.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
rv64.risu | 141 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 141 insertions(+)
create mode 100644 rv64.risu
diff --git a/rv64.risu b/rv64.risu
new file mode 100644
index 0000000..edf0d1f
--- /dev/null
+++ b/rv64.risu
@@ -0,0 +1,141 @@
+# Input file for risugen defining RISC-V instructions
+.mode riscv.rv64
+@RV64I
+
+# x2 stack pointer, x3 global pointer, x4 thread pointer
+# These registers should be reserved for signal handler.
+
+LUI RISCV imm:20 rd:5 0110111 \
+!constraints { greg($rd); }
+
+AUIPC RISCV imm:20 rd:5 0110111 \
+!constraints { greg($rd); }
+
+# Limit to current implementation, the base address register will be overide
+LB RISCV imm:12 rs1:5 000 rd:5 0000011 \
+!constraints { greg($rd) && gbase($rs1); } \
+!memory { align(1); reg_plus_imm($rs1, sextract($imm, 12), $rd); }
+
+LH RISCV imm:12 rs1:5 001 rd:5 0000011 \
+!constraints { greg($rd) && gbase($rs1); } \
+!memory { align(2); reg_plus_imm($rs1, sextract($imm, 12), $rd); }
+
+LW RISCV imm:12 rs1:5 010 rd:5 0000011 \
+!constraints { greg($rd) && gbase($rs1); } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12), $rd); }
+
+LBU RISCV imm:12 rs1:5 100 rd:5 0000011 \
+!constraints { greg($rd) && gbase($rs1); } \
+!memory { align(1); reg_plus_imm($rs1, sextract($imm, 12), $rd); }
+
+LHU RISCV imm:12 rs1:5 101 rd:5 0000011 \
+!constraints { greg($rd) && gbase($rs1); } \
+!memory { align(2); reg_plus_imm($rs1, sextract($imm, 12), $rd); }
+
+SB RISCV imm5:7 rs2:5 rs1:5 000 imm:5 0100011 \
+!constraints { greg($rs2) && gbase($rs1) && $rs2 != $rs1; } \
+!memory { align(1); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+SH RISCV imm5:7 rs2:5 rs1:5 001 imm:5 0100011 \
+!constraints { greg($rs2) && gbase($rs1) && $rs2 != $rs1; } \
+!memory { align(2); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+SW RISCV imm5:7 rs2:5 rs1:5 010 imm:5 0100011 \
+!constraints { greg($rs2) && gbase($rs1) && $rs2 != $rs1; } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+ADDI RISCV imm:12 rs1:5 000 rd:5 0010011 \
+!constraints { greg($rd) && greg($rs1); }
+
+SLTI RISCV imm:12 rs1:5 010 rd:5 0010011 \
+!constraints { greg($rd) && greg($rs1); }
+
+SLTIU RISCV imm:12 rs1:5 011 rd:5 0010011 \
+!constraints { greg($rd) && greg($rs1); }
+
+XORI RISCV imm:12 rs1:5 100 rd:5 0010011 \
+!constraints { greg($rd) && greg($rs1); }
+
+ORI RISCV imm:12 rs1:5 110 rd:5 0010011 \
+!constraints { greg($rd) && greg($rs1); }
+
+ANDI RISCV imm:12 rs1:5 111 rd:5 0010011 \
+!constraints { greg($rd) && greg($rs1); }
+
+ADD RISCV 0000000 rs2:5 rs1:5 000 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SUB RISCV 0100000 rs2:5 rs1:5 000 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SLL RISCV 0000000 rs2:5 rs1:5 001 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SLT RISCV 0000000 rs2:5 rs1:5 010 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SLTU RISCV 0000000 rs2:5 rs1:5 011 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+XOR RISCV 0000000 rs2:5 rs1:5 100 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SRL RISCV 0000000 rs2:5 rs1:5 101 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SRA RISCV 0100000 rs2:5 rs1:5 101 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+OR RISCV 0000000 rs2:5 rs1:5 110 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+AND RISCV 0000000 rs2:5 rs1:5 111 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+LWU RISCV imm:12 rs1:5 110 rd:5 0000011 \
+!constraints { greg($rd) && gbase($rs1); } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12), $rd); }
+
+LD RISCV imm:12 rs1:5 011 rd:5 0000011 \
+!constraints { greg($rd) && gbase($rs1); } \
+!memory { align(8); reg_plus_imm($rs1, sextract($imm, 12), $rd); }
+
+SD RISCV imm5:7 rs2:5 rs1:5 011 imm:5 0100011 \
+!constraints { greg($rs2) && gbase($rs1) && $rs2 != $rs1; } \
+!memory { align(8); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+SLLI RISCV 00000 sham5:7 rs1:5 001 rd:5 0010011 \
+!constraints { greg($rd) && greg($rs1); }
+
+SRLI RISCV 00000 sham5:7 rs1:5 101 rd:5 0010011 \
+!constraints { greg($rd) && greg($rs1); }
+
+SRAI RISCV 01000 sham5:7 rs1:5 101 rd:5 0010011 \
+!constraints { greg($rd) && greg($rs1); }
+
+ADDIW RISCV imm:12 rs1:5 000 rd:5 0011011 \
+!constraints { greg($rd) && greg($rs1); }
+
+SLLIW RISCV 0000000 shamt:5 rs1:5 001 rd:5 0011011 \
+!constraints { greg($rd) && greg($rs1); }
+
+SRLIW RISCV 0000000 shamt:5 rs1:5 101 rd:5 0011011 \
+!constraints { greg($rd) && greg($rs1); }
+
+SRAIW RISCV 0100000 shamt:5 rs1:5 101 rd:5 0011011 \
+!constraints { greg($rd) && greg($rs1); }
+
+ADDW RISCV 0000000 rs2:5 rs1:5 000 rd:5 0011011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SUBW RISCV 0100000 rs2:5 rs1:5 000 rd:5 0011011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SLLW RISCV 0000000 rs2:5 rs1:5 001 rd:5 0011011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SRLW RISCV 0000000 rs2:5 rs1:5 101 rd:5 0011011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+SRAW RISCV 0100000 rs2:5 rs1:5 101 rd:5 0011011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
--
2.23.0
next prev parent reply other threads:[~2020-07-11 16:23 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-11 16:16 [PATCH 00/11] RISC-V risu porting LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei [this message]
2020-07-11 16:16 ` [PATCH 01/11] riscv: Add RV64I instructions description LIU Zhiwei
2020-07-11 16:16 ` [PATCH 02/11] riscv: Add RV64M " LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 03/11] riscv: Add RV64A " LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 04/11] riscv: Add RV64F " LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 05/11] riscv: Add RV64D " LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 06/11] riscv: Add RV64C " LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 07/11] riscv: Generate payload scripts LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 08/11] riscv: Add standard test case LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 09/11] riscv: Define riscv struct reginfo LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 10/11] riscv: Implement payload load interfaces LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 11/11] riscv: Add configure script LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-22 2:50 ` [PATCH 00/11] RISC-V risu porting LIU Zhiwei
2020-07-22 2:50 ` LIU Zhiwei
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