From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: peter.maydell@linaro.org, richard.henderson@linaro.org,
wxy194768@alibaba-inc.com, chihmin.chao@sifive.com,
wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com,
alex.bennee@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH 02/11] riscv: Add RV64M instructions description
Date: Sun, 12 Jul 2020 00:16:46 +0800 [thread overview]
Message-ID: <20200711161655.2856-3-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
rv64.risu | 41 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/rv64.risu b/rv64.risu
index edf0d1f..2c4154e 100644
--- a/rv64.risu
+++ b/rv64.risu
@@ -139,3 +139,44 @@ SRLW RISCV 0000000 rs2:5 rs1:5 101 rd:5 0011011 \
SRAW RISCV 0100000 rs2:5 rs1:5 101 rd:5 0011011 \
!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+@RV64M
+
+MUL RISCV 0000001 rs2:5 rs1:5 000 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+MULH RISCV 0000001 rs2:5 rs1:5 001 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+MULHSU RISCV 0000001 rs2:5 rs1:5 010 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+MULHU RISCV 0000001 rs2:5 rs1:5 011 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+DIV RISCV 0000001 rs2:5 rs1:5 100 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+DIVU RISCV 0000001 rs2:5 rs1:5 101 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+REM RISCV 0000001 rs2:5 rs1:5 110 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+REMU RISCV 0000001 rs2:5 rs1:5 111 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+MULW RISCV 0000001 rs2:5 rs1:5 000 rd:5 0111011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+DIVW RISCV 0000001 rs2:5 rs1:5 100 rd:5 0111011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+DIVUW RISCV 0000001 rs2:5 rs1:5 101 rd:5 0111011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+REMW RISCV 0000001 rs2:5 rs1:5 110 rd:5 0111011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+REMUW RISCV 0000001 rs2:5 rs1:5 111 rd:5 0111011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
--
2.23.0
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: richard.henderson@linaro.org, Alistair.Francis@wdc.com,
chihmin.chao@sifive.com, alex.bennee@linaro.org,
peter.maydell@linaro.org, wenmeng_zhang@c-sky.com,
wxy194768@alibaba-inc.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH 02/11] riscv: Add RV64M instructions description
Date: Sun, 12 Jul 2020 00:16:46 +0800 [thread overview]
Message-ID: <20200711161655.2856-3-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
rv64.risu | 41 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/rv64.risu b/rv64.risu
index edf0d1f..2c4154e 100644
--- a/rv64.risu
+++ b/rv64.risu
@@ -139,3 +139,44 @@ SRLW RISCV 0000000 rs2:5 rs1:5 101 rd:5 0011011 \
SRAW RISCV 0100000 rs2:5 rs1:5 101 rd:5 0011011 \
!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+@RV64M
+
+MUL RISCV 0000001 rs2:5 rs1:5 000 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+MULH RISCV 0000001 rs2:5 rs1:5 001 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+MULHSU RISCV 0000001 rs2:5 rs1:5 010 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+MULHU RISCV 0000001 rs2:5 rs1:5 011 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+DIV RISCV 0000001 rs2:5 rs1:5 100 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+DIVU RISCV 0000001 rs2:5 rs1:5 101 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+REM RISCV 0000001 rs2:5 rs1:5 110 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+REMU RISCV 0000001 rs2:5 rs1:5 111 rd:5 0110011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+MULW RISCV 0000001 rs2:5 rs1:5 000 rd:5 0111011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+DIVW RISCV 0000001 rs2:5 rs1:5 100 rd:5 0111011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+DIVUW RISCV 0000001 rs2:5 rs1:5 101 rd:5 0111011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+REMW RISCV 0000001 rs2:5 rs1:5 110 rd:5 0111011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
+
+REMUW RISCV 0000001 rs2:5 rs1:5 111 rd:5 0111011 \
+!constraints { greg($rd) && greg($rs1) && greg($rs2); }
--
2.23.0
next prev parent reply other threads:[~2020-07-11 16:21 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-11 16:16 [PATCH 00/11] RISC-V risu porting LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 01/11] riscv: Add RV64I instructions description LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei [this message]
2020-07-11 16:16 ` [PATCH 02/11] riscv: Add RV64M " LIU Zhiwei
2020-07-11 16:16 ` [PATCH 03/11] riscv: Add RV64A " LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 04/11] riscv: Add RV64F " LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 05/11] riscv: Add RV64D " LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 06/11] riscv: Add RV64C " LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 07/11] riscv: Generate payload scripts LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 08/11] riscv: Add standard test case LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 09/11] riscv: Define riscv struct reginfo LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 10/11] riscv: Implement payload load interfaces LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 11/11] riscv: Add configure script LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-22 2:50 ` [PATCH 00/11] RISC-V risu porting LIU Zhiwei
2020-07-22 2:50 ` LIU Zhiwei
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