From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: peter.maydell@linaro.org, richard.henderson@linaro.org, wxy194768@alibaba-inc.com, chihmin.chao@sifive.com, wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com, alex.bennee@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH 08/11] riscv: Add standard test case Date: Sun, 12 Jul 2020 00:16:52 +0800 [thread overview] Message-ID: <20200711161655.2856-9-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- test_riscv64.s | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 test_riscv64.s diff --git a/test_riscv64.s b/test_riscv64.s new file mode 100644 index 0000000..22a22b6 --- /dev/null +++ b/test_riscv64.s @@ -0,0 +1,85 @@ +/***************************************************************************** + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * LIU Zhiwei (T-Head) - initial implementation + * based on test_arm.s by Peter Maydell + *****************************************************************************/ + +/* Initialise the gp regs */ +li x1, 1 +#li x2, 2 # stack pointer +#li x3, 3 # global pointer +#li x4, 4 # thread pointer +li x5, 5 +li x6, 6 +li x7, 7 +li x8, 8 +li x9, 9 +li x10, 10 +li x11, 11 +li x12, 12 +li x13, 13 +li x14, 14 +li x15, 15 +li x16, 16 +li x17, 17 +li x18, 18 +li x19, 19 +li x20, 20 +li x21, 21 +li x22, 22 +li x23, 23 +li x24, 24 +li x25, 25 +li x26, 26 +li x27, 27 +li x28, 28 +li x29, 29 +li x30, 30 +li x31, 30 + +/* Initialise the fp regs */ +fcvt.d.lu f0, x0 +fcvt.d.lu f1, x1 +fcvt.d.lu f2, x2 +fcvt.d.lu f3, x3 +fcvt.d.lu f4, x4 +fcvt.d.lu f5, x5 +fcvt.d.lu f6, x6 +fcvt.d.lu f7, x7 +fcvt.d.lu f8, x8 +fcvt.d.lu f9, x9 +fcvt.d.lu f10, x10 +fcvt.d.lu f11, x11 +fcvt.d.lu f12, x12 +fcvt.d.lu f13, x13 +fcvt.d.lu f14, x14 +fcvt.d.lu f15, x15 +fcvt.d.lu f16, x16 +fcvt.d.lu f17, x17 +fcvt.d.lu f18, x18 +fcvt.d.lu f19, x19 +fcvt.d.lu f20, x20 +fcvt.d.lu f21, x21 +fcvt.d.lu f22, x22 +fcvt.d.lu f23, x23 +fcvt.d.lu f24, x24 +fcvt.d.lu f25, x25 +fcvt.d.lu f26, x26 +fcvt.d.lu f27, x27 +fcvt.d.lu f28, x28 +fcvt.d.lu f29, x29 +fcvt.d.lu f30, x30 +fcvt.d.lu f31, x31 + +/* do compare. + * The manual says instr with bits (6:0) == 1 1 0 1 0 1 1 are UNALLOCATED + */ +.int 0x0000006b +/* exit test */ +.int 0x0000016b -- 2.23.0
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: richard.henderson@linaro.org, Alistair.Francis@wdc.com, chihmin.chao@sifive.com, alex.bennee@linaro.org, peter.maydell@linaro.org, wenmeng_zhang@c-sky.com, wxy194768@alibaba-inc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Subject: [PATCH 08/11] riscv: Add standard test case Date: Sun, 12 Jul 2020 00:16:52 +0800 [thread overview] Message-ID: <20200711161655.2856-9-zhiwei_liu@c-sky.com> (raw) In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- test_riscv64.s | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 test_riscv64.s diff --git a/test_riscv64.s b/test_riscv64.s new file mode 100644 index 0000000..22a22b6 --- /dev/null +++ b/test_riscv64.s @@ -0,0 +1,85 @@ +/***************************************************************************** + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * LIU Zhiwei (T-Head) - initial implementation + * based on test_arm.s by Peter Maydell + *****************************************************************************/ + +/* Initialise the gp regs */ +li x1, 1 +#li x2, 2 # stack pointer +#li x3, 3 # global pointer +#li x4, 4 # thread pointer +li x5, 5 +li x6, 6 +li x7, 7 +li x8, 8 +li x9, 9 +li x10, 10 +li x11, 11 +li x12, 12 +li x13, 13 +li x14, 14 +li x15, 15 +li x16, 16 +li x17, 17 +li x18, 18 +li x19, 19 +li x20, 20 +li x21, 21 +li x22, 22 +li x23, 23 +li x24, 24 +li x25, 25 +li x26, 26 +li x27, 27 +li x28, 28 +li x29, 29 +li x30, 30 +li x31, 30 + +/* Initialise the fp regs */ +fcvt.d.lu f0, x0 +fcvt.d.lu f1, x1 +fcvt.d.lu f2, x2 +fcvt.d.lu f3, x3 +fcvt.d.lu f4, x4 +fcvt.d.lu f5, x5 +fcvt.d.lu f6, x6 +fcvt.d.lu f7, x7 +fcvt.d.lu f8, x8 +fcvt.d.lu f9, x9 +fcvt.d.lu f10, x10 +fcvt.d.lu f11, x11 +fcvt.d.lu f12, x12 +fcvt.d.lu f13, x13 +fcvt.d.lu f14, x14 +fcvt.d.lu f15, x15 +fcvt.d.lu f16, x16 +fcvt.d.lu f17, x17 +fcvt.d.lu f18, x18 +fcvt.d.lu f19, x19 +fcvt.d.lu f20, x20 +fcvt.d.lu f21, x21 +fcvt.d.lu f22, x22 +fcvt.d.lu f23, x23 +fcvt.d.lu f24, x24 +fcvt.d.lu f25, x25 +fcvt.d.lu f26, x26 +fcvt.d.lu f27, x27 +fcvt.d.lu f28, x28 +fcvt.d.lu f29, x29 +fcvt.d.lu f30, x30 +fcvt.d.lu f31, x31 + +/* do compare. + * The manual says instr with bits (6:0) == 1 1 0 1 0 1 1 are UNALLOCATED + */ +.int 0x0000006b +/* exit test */ +.int 0x0000016b -- 2.23.0
next prev parent reply other threads:[~2020-07-11 16:23 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-07-11 16:16 [PATCH 00/11] RISC-V risu porting LIU Zhiwei 2020-07-11 16:16 ` LIU Zhiwei 2020-07-11 16:16 ` [PATCH 01/11] riscv: Add RV64I instructions description LIU Zhiwei 2020-07-11 16:16 ` LIU Zhiwei 2020-07-11 16:16 ` [PATCH 02/11] riscv: Add RV64M " LIU Zhiwei 2020-07-11 16:16 ` LIU Zhiwei 2020-07-11 16:16 ` [PATCH 03/11] riscv: Add RV64A " LIU Zhiwei 2020-07-11 16:16 ` LIU Zhiwei 2020-07-11 16:16 ` [PATCH 04/11] riscv: Add RV64F " LIU Zhiwei 2020-07-11 16:16 ` LIU Zhiwei 2020-07-11 16:16 ` [PATCH 05/11] riscv: Add RV64D " LIU Zhiwei 2020-07-11 16:16 ` LIU Zhiwei 2020-07-11 16:16 ` [PATCH 06/11] riscv: Add RV64C " LIU Zhiwei 2020-07-11 16:16 ` LIU Zhiwei 2020-07-11 16:16 ` [PATCH 07/11] riscv: Generate payload scripts LIU Zhiwei 2020-07-11 16:16 ` LIU Zhiwei 2020-07-11 16:16 ` LIU Zhiwei [this message] 2020-07-11 16:16 ` [PATCH 08/11] riscv: Add standard test case LIU Zhiwei 2020-07-11 16:16 ` [PATCH 09/11] riscv: Define riscv struct reginfo LIU Zhiwei 2020-07-11 16:16 ` LIU Zhiwei 2020-07-11 16:16 ` [PATCH 10/11] riscv: Implement payload load interfaces LIU Zhiwei 2020-07-11 16:16 ` LIU Zhiwei 2020-07-11 16:16 ` [PATCH 11/11] riscv: Add configure script LIU Zhiwei 2020-07-11 16:16 ` LIU Zhiwei 2020-07-22 2:50 ` [PATCH 00/11] RISC-V risu porting LIU Zhiwei 2020-07-22 2:50 ` LIU Zhiwei
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