From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: peter.maydell@linaro.org, richard.henderson@linaro.org,
wxy194768@alibaba-inc.com, chihmin.chao@sifive.com,
wenmeng_zhang@c-sky.com, Alistair.Francis@wdc.com,
alex.bennee@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH 04/11] riscv: Add RV64F instructions description
Date: Sun, 12 Jul 2020 00:16:48 +0800 [thread overview]
Message-ID: <20200711161655.2856-5-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com>
For supporting multi-precision, split all 32 fp registers into two groups.
The RV64F instructions will use only 16 fp registers selected by gfp32().
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
rv64.risu | 94 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 94 insertions(+)
diff --git a/rv64.risu b/rv64.risu
index ad5dee9..0dcc9a1 100644
--- a/rv64.risu
+++ b/rv64.risu
@@ -270,3 +270,97 @@ AMOMINU_D RISCV 11000 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \
AMOMAXU_D RISCV 11100 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \
!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\
!memory { align(8); reg($rs1, $rd); }
+
+@RV64F
+
+FLW RISCV imm:12 rs1:5 010 rd:5 0000111 \
+!constraints { gbase($rs1) && gfp32($rd); } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+FSW RISCV imm5:7 rs2:5 rs1:5 010 imm:5 0100111 \
+!constraints { gbase($rs1) && gfp32($rs2); } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+FMADD_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1000011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); }
+
+FMSUB_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1000111 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); }
+
+FNMSUB_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1001011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); }
+
+FNMADD_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1001111 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); }
+
+FADD_S RISCV 0000000 rs2:5 rs1:5 rm:3 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); }
+
+FSUB_S RISCV 0000100 rs2:5 rs1:5 rm:3 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); }
+
+FMUL_S RISCV 0001000 rs2:5 rs1:5 rm:3 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); }
+
+FDIV_S RISCV 0001100 rs2:5 rs1:5 rm:3 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); }
+
+FSQRT_S RISCV 0101100 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rd) && grm($rm); }
+
+FSGNJ_S RISCV 0010000 rs2:5 rs1:5 000 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); }
+
+FSGNJN_S RISCV 0010000 rs2:5 rs1:5 001 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); }
+
+FSGNJX_S RISCV 0010000 rs2:5 rs1:5 010 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); }
+
+FMIN_S RISCV 0010100 rs2:5 rs1:5 000 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); }
+
+FMAX_S RISCV 0010100 rs2:5 rs1:5 001 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); }
+
+FCVT_W_S RISCV 1100000 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rd) && gfp32($rs1) && grm($rm); }
+
+FCVT_WU_S RISCV 1100000 00001 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rd) && gfp32($rs1) && grm($rm); }
+
+FMV_X_W RISCV 1110000 00000 rs1:5 000 rd:5 1010011 \
+!constraints { greg($rd) && gfp32($rs1); }
+
+FEQ_S RISCV 1010000 rs2:5 rs1:5 010 rd:5 1010011 \
+!constraints { greg($rd) && gfp32($rs1) && gfp32($rs2); }
+
+FLT_S RISCV 1010000 rs2:5 rs1:5 001 rd:5 1010011 \
+!constraints { greg($rd) && gfp32($rs1) && gfp32($rs2); }
+
+FLE_S RISCV 1010000 rs2:5 rs1:5 000 rd:5 1010011 \
+!constraints { greg($rd) && gfp32($rs1) && gfp32($rs2); }
+
+FCLASS_S RISCV 1110000 00000 rs1:5 001 rd:5 1010011 \
+!constraints { greg($rd) && gfp32($rs1); }
+
+FCVT_S_W RISCV 1101000 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rs1) && gfp32($rd) && grm($rm); }
+
+FCVT_S_WU RISCV 1101000 00001 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rs1) && gfp32($rd) && grm($rm); }
+
+FMV_W_X RISCV 1111000 00000 rs1:5 000 rd:5 1010011 \
+!constraints { greg($rs1) && gfp32($rd); }
+
+FCVT_L_S RISCV 1100000 00010 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rd) && gfp32($rs1) && grm($rm); }
+
+FCVT_LU_S RISCV 1100000 00011 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rd) && gfp32($rs1) && grm($rm); }
+
+FCVT_S_L RISCV 1101000 00010 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rs1) && gfp32($rd) && grm($rm); }
+
+FCVT_S_LU RISCV 1101000 00011 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rs1) && gfp32($rd) && grm($rm); }
--
2.23.0
WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: richard.henderson@linaro.org, Alistair.Francis@wdc.com,
chihmin.chao@sifive.com, alex.bennee@linaro.org,
peter.maydell@linaro.org, wenmeng_zhang@c-sky.com,
wxy194768@alibaba-inc.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH 04/11] riscv: Add RV64F instructions description
Date: Sun, 12 Jul 2020 00:16:48 +0800 [thread overview]
Message-ID: <20200711161655.2856-5-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200711161655.2856-1-zhiwei_liu@c-sky.com>
For supporting multi-precision, split all 32 fp registers into two groups.
The RV64F instructions will use only 16 fp registers selected by gfp32().
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
rv64.risu | 94 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 94 insertions(+)
diff --git a/rv64.risu b/rv64.risu
index ad5dee9..0dcc9a1 100644
--- a/rv64.risu
+++ b/rv64.risu
@@ -270,3 +270,97 @@ AMOMINU_D RISCV 11000 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \
AMOMAXU_D RISCV 11100 imm:2 rs2:5 rs1:5 011 rd:5 0101111 \
!constraints { greg($rd) && greg($rs2) && gbase($rs1) && $rs2 != $rs1; }\
!memory { align(8); reg($rs1, $rd); }
+
+@RV64F
+
+FLW RISCV imm:12 rs1:5 010 rd:5 0000111 \
+!constraints { gbase($rs1) && gfp32($rd); } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12)); }
+
+FSW RISCV imm5:7 rs2:5 rs1:5 010 imm:5 0100111 \
+!constraints { gbase($rs1) && gfp32($rs2); } \
+!memory { align(4); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); }
+
+FMADD_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1000011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); }
+
+FMSUB_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1000111 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); }
+
+FNMSUB_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1001011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); }
+
+FNMADD_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1001111 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); }
+
+FADD_S RISCV 0000000 rs2:5 rs1:5 rm:3 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); }
+
+FSUB_S RISCV 0000100 rs2:5 rs1:5 rm:3 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); }
+
+FMUL_S RISCV 0001000 rs2:5 rs1:5 rm:3 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); }
+
+FDIV_S RISCV 0001100 rs2:5 rs1:5 rm:3 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd) && grm($rm); }
+
+FSQRT_S RISCV 0101100 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rd) && grm($rm); }
+
+FSGNJ_S RISCV 0010000 rs2:5 rs1:5 000 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); }
+
+FSGNJN_S RISCV 0010000 rs2:5 rs1:5 001 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); }
+
+FSGNJX_S RISCV 0010000 rs2:5 rs1:5 010 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); }
+
+FMIN_S RISCV 0010100 rs2:5 rs1:5 000 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); }
+
+FMAX_S RISCV 0010100 rs2:5 rs1:5 001 rd:5 1010011 \
+!constraints { gfp32($rs1) && gfp32($rs2) && gfp32($rd); }
+
+FCVT_W_S RISCV 1100000 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rd) && gfp32($rs1) && grm($rm); }
+
+FCVT_WU_S RISCV 1100000 00001 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rd) && gfp32($rs1) && grm($rm); }
+
+FMV_X_W RISCV 1110000 00000 rs1:5 000 rd:5 1010011 \
+!constraints { greg($rd) && gfp32($rs1); }
+
+FEQ_S RISCV 1010000 rs2:5 rs1:5 010 rd:5 1010011 \
+!constraints { greg($rd) && gfp32($rs1) && gfp32($rs2); }
+
+FLT_S RISCV 1010000 rs2:5 rs1:5 001 rd:5 1010011 \
+!constraints { greg($rd) && gfp32($rs1) && gfp32($rs2); }
+
+FLE_S RISCV 1010000 rs2:5 rs1:5 000 rd:5 1010011 \
+!constraints { greg($rd) && gfp32($rs1) && gfp32($rs2); }
+
+FCLASS_S RISCV 1110000 00000 rs1:5 001 rd:5 1010011 \
+!constraints { greg($rd) && gfp32($rs1); }
+
+FCVT_S_W RISCV 1101000 00000 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rs1) && gfp32($rd) && grm($rm); }
+
+FCVT_S_WU RISCV 1101000 00001 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rs1) && gfp32($rd) && grm($rm); }
+
+FMV_W_X RISCV 1111000 00000 rs1:5 000 rd:5 1010011 \
+!constraints { greg($rs1) && gfp32($rd); }
+
+FCVT_L_S RISCV 1100000 00010 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rd) && gfp32($rs1) && grm($rm); }
+
+FCVT_LU_S RISCV 1100000 00011 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rd) && gfp32($rs1) && grm($rm); }
+
+FCVT_S_L RISCV 1101000 00010 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rs1) && gfp32($rd) && grm($rm); }
+
+FCVT_S_LU RISCV 1101000 00011 rs1:5 rm:3 rd:5 1010011 \
+!constraints { greg($rs1) && gfp32($rd) && grm($rm); }
--
2.23.0
next prev parent reply other threads:[~2020-07-11 16:20 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-11 16:16 [PATCH 00/11] RISC-V risu porting LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 01/11] riscv: Add RV64I instructions description LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 02/11] riscv: Add RV64M " LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 03/11] riscv: Add RV64A " LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei [this message]
2020-07-11 16:16 ` [PATCH 04/11] riscv: Add RV64F " LIU Zhiwei
2020-07-11 16:16 ` [PATCH 05/11] riscv: Add RV64D " LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 06/11] riscv: Add RV64C " LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 07/11] riscv: Generate payload scripts LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 08/11] riscv: Add standard test case LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 09/11] riscv: Define riscv struct reginfo LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 10/11] riscv: Implement payload load interfaces LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-11 16:16 ` [PATCH 11/11] riscv: Add configure script LIU Zhiwei
2020-07-11 16:16 ` LIU Zhiwei
2020-07-22 2:50 ` [PATCH 00/11] RISC-V risu porting LIU Zhiwei
2020-07-22 2:50 ` LIU Zhiwei
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