From: Yifei Jiang <jiangyifei@huawei.com>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Cc: <kvm-riscv@lists.infradead.org>, <kvm@vger.kernel.org>,
<libvir-list@redhat.com>, <anup@brainfault.org>,
<palmer@dabbelt.com>, <Alistair.Francis@wdc.com>,
<bin.meng@windriver.com>, <fanliang@huawei.com>,
<wu.wubin@huawei.com>, <wanghaibin.wang@huawei.com>,
<wanbo13@huawei.com>, Yifei Jiang <jiangyifei@huawei.com>,
Mingwang Li <limingwang@huawei.com>,
Anup Patel <anup.patel@wdc.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v5 12/13] target/riscv: Support virtual time context synchronization
Date: Wed, 12 Jan 2022 16:13:28 +0800 [thread overview]
Message-ID: <20220112081329.1835-13-jiangyifei@huawei.com> (raw)
In-Reply-To: <20220112081329.1835-1-jiangyifei@huawei.com>
Add virtual time context description to vmstate_kvmtimer. After cpu being
loaded, virtual time context is updated to KVM.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/machine.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 13b9ab375b..098670e680 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -185,6 +185,35 @@ static const VMStateDescription vmstate_rv128 = {
}
};
+static bool kvmtimer_needed(void *opaque)
+{
+ return kvm_enabled();
+}
+
+static int cpu_post_load(void *opaque, int version_id)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ env->kvm_timer_dirty = true;
+ return 0;
+}
+
+static const VMStateDescription vmstate_kvmtimer = {
+ .name = "cpu/kvmtimer",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = kvmtimer_needed,
+ .post_load = cpu_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
+ VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
+ VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
+
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 3,
@@ -240,6 +269,7 @@ const VMStateDescription vmstate_riscv_cpu = {
&vmstate_vector,
&vmstate_pointermasking,
&vmstate_rv128,
+ &vmstate_kvmtimer,
NULL
}
};
--
2.19.1
WARNING: multiple messages have this Message-ID (diff)
From: Yifei Jiang via <qemu-devel@nongnu.org>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Cc: <kvm-riscv@lists.infradead.org>, <kvm@vger.kernel.org>,
<libvir-list@redhat.com>, <anup@brainfault.org>,
<palmer@dabbelt.com>, <Alistair.Francis@wdc.com>,
<bin.meng@windriver.com>, <fanliang@huawei.com>,
<wu.wubin@huawei.com>, <wanghaibin.wang@huawei.com>,
<wanbo13@huawei.com>, Yifei Jiang <jiangyifei@huawei.com>,
Mingwang Li <limingwang@huawei.com>,
Anup Patel <anup.patel@wdc.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v5 12/13] target/riscv: Support virtual time context synchronization
Date: Wed, 12 Jan 2022 16:13:28 +0800 [thread overview]
Message-ID: <20220112081329.1835-13-jiangyifei@huawei.com> (raw)
In-Reply-To: <20220112081329.1835-1-jiangyifei@huawei.com>
Add virtual time context description to vmstate_kvmtimer. After cpu being
loaded, virtual time context is updated to KVM.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/machine.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 13b9ab375b..098670e680 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -185,6 +185,35 @@ static const VMStateDescription vmstate_rv128 = {
}
};
+static bool kvmtimer_needed(void *opaque)
+{
+ return kvm_enabled();
+}
+
+static int cpu_post_load(void *opaque, int version_id)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ env->kvm_timer_dirty = true;
+ return 0;
+}
+
+static const VMStateDescription vmstate_kvmtimer = {
+ .name = "cpu/kvmtimer",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = kvmtimer_needed,
+ .post_load = cpu_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
+ VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
+ VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
+
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 3,
@@ -240,6 +269,7 @@ const VMStateDescription vmstate_riscv_cpu = {
&vmstate_vector,
&vmstate_pointermasking,
&vmstate_rv128,
+ &vmstate_kvmtimer,
NULL
}
};
--
2.19.1
next prev parent reply other threads:[~2022-01-12 8:14 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-12 8:13 [PATCH v5 00/13] Add riscv kvm accel support Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 01/13] update-linux-headers: Add asm-riscv/kvm.h Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 02/13] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 03/13] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 04/13] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 05/13] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 06/13] target/riscv: Support start kernel directly by KVM Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-13 4:35 ` Anup Patel
2022-01-13 4:35 ` Anup Patel
2022-01-12 8:13 ` [PATCH v5 07/13] target/riscv: Support setting external interrupt " Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 08/13] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 09/13] target/riscv: Add host cpu type Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 10/13] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 11/13] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` Yifei Jiang [this message]
2022-01-12 8:13 ` [PATCH v5 12/13] target/riscv: Support virtual time context synchronization Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 13/13] target/riscv: enable riscv kvm accel Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-13 4:30 ` Alistair Francis
2022-01-13 4:30 ` Alistair Francis
2022-01-13 4:41 ` Anup Patel
2022-01-13 4:41 ` Anup Patel
2022-01-17 22:48 ` [PATCH v5 00/13] Add riscv kvm accel support Alistair Francis
2022-01-17 22:48 ` Alistair Francis
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