From: Anup Patel <anup@brainfault.org>
To: Yifei Jiang <jiangyifei@huawei.com>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
kvm-riscv@lists.infradead.org, KVM General <kvm@vger.kernel.org>,
libvir-list@redhat.com, Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
fanliang@huawei.com, "Wubin (H)" <wu.wubin@huawei.com>,
wanghaibin.wang@huawei.com, wanbo13@huawei.com,
Mingwang Li <limingwang@huawei.com>
Subject: Re: [PATCH v5 13/13] target/riscv: enable riscv kvm accel
Date: Thu, 13 Jan 2022 10:11:41 +0530 [thread overview]
Message-ID: <CAAhSdy2oOiiJ=ogzP4+StyvJpqaa-zjPGqKA2hy2T3JcCO7jCA@mail.gmail.com> (raw)
In-Reply-To: <20220112081329.1835-14-jiangyifei@huawei.com>
On Wed, Jan 12, 2022 at 1:44 PM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Add riscv kvm support in meson.build file.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Mingwang Li <limingwang@huawei.com>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> meson.build | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/meson.build b/meson.build
> index c1b1db1e28..06a5476254 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -90,6 +90,8 @@ elif cpu in ['ppc', 'ppc64']
> kvm_targets = ['ppc-softmmu', 'ppc64-softmmu']
> elif cpu in ['mips', 'mips64']
> kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu']
> +elif cpu in ['riscv']
> + kvm_targets = ['riscv32-softmmu', 'riscv64-softmmu']
> else
> kvm_targets = []
> endif
> --
> 2.19.1
>
>
> --
> kvm-riscv mailing list
> kvm-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/kvm-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup@brainfault.org>
To: Yifei Jiang <jiangyifei@huawei.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Mingwang Li <limingwang@huawei.com>,
KVM General <kvm@vger.kernel.org>,
libvir-list@redhat.com, Bin Meng <bin.meng@windriver.com>,
QEMU Developers <qemu-devel@nongnu.org>,
wanbo13@huawei.com, Palmer Dabbelt <palmer@dabbelt.com>,
kvm-riscv@lists.infradead.org, wanghaibin.wang@huawei.com,
Alistair Francis <Alistair.Francis@wdc.com>,
fanliang@huawei.com, "Wubin \(H\)" <wu.wubin@huawei.com>
Subject: Re: [PATCH v5 13/13] target/riscv: enable riscv kvm accel
Date: Thu, 13 Jan 2022 10:11:41 +0530 [thread overview]
Message-ID: <CAAhSdy2oOiiJ=ogzP4+StyvJpqaa-zjPGqKA2hy2T3JcCO7jCA@mail.gmail.com> (raw)
In-Reply-To: <20220112081329.1835-14-jiangyifei@huawei.com>
On Wed, Jan 12, 2022 at 1:44 PM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Add riscv kvm support in meson.build file.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Mingwang Li <limingwang@huawei.com>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> meson.build | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/meson.build b/meson.build
> index c1b1db1e28..06a5476254 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -90,6 +90,8 @@ elif cpu in ['ppc', 'ppc64']
> kvm_targets = ['ppc-softmmu', 'ppc64-softmmu']
> elif cpu in ['mips', 'mips64']
> kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu']
> +elif cpu in ['riscv']
> + kvm_targets = ['riscv32-softmmu', 'riscv64-softmmu']
> else
> kvm_targets = []
> endif
> --
> 2.19.1
>
>
> --
> kvm-riscv mailing list
> kvm-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/kvm-riscv
next prev parent reply other threads:[~2022-01-13 4:41 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-12 8:13 [PATCH v5 00/13] Add riscv kvm accel support Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 01/13] update-linux-headers: Add asm-riscv/kvm.h Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 02/13] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 03/13] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 04/13] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 05/13] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 06/13] target/riscv: Support start kernel directly by KVM Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-13 4:35 ` Anup Patel
2022-01-13 4:35 ` Anup Patel
2022-01-12 8:13 ` [PATCH v5 07/13] target/riscv: Support setting external interrupt " Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 08/13] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 09/13] target/riscv: Add host cpu type Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 10/13] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 11/13] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 12/13] target/riscv: Support virtual time context synchronization Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-12 8:13 ` [PATCH v5 13/13] target/riscv: enable riscv kvm accel Yifei Jiang
2022-01-12 8:13 ` Yifei Jiang via
2022-01-13 4:30 ` Alistair Francis
2022-01-13 4:30 ` Alistair Francis
2022-01-13 4:41 ` Anup Patel [this message]
2022-01-13 4:41 ` Anup Patel
2022-01-17 22:48 ` [PATCH v5 00/13] Add riscv kvm accel support Alistair Francis
2022-01-17 22:48 ` Alistair Francis
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