From: Yifei Jiang <jiangyifei@huawei.com> To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org> Cc: <kvm-riscv@lists.infradead.org>, <kvm@vger.kernel.org>, <libvir-list@redhat.com>, <anup@brainfault.org>, <palmer@dabbelt.com>, <Alistair.Francis@wdc.com>, <bin.meng@windriver.com>, <fanliang@huawei.com>, <wu.wubin@huawei.com>, <wanghaibin.wang@huawei.com>, <wanbo13@huawei.com>, Yifei Jiang <jiangyifei@huawei.com>, Mingwang Li <limingwang@huawei.com>, Alistair Francis <alistair.francis@wdc.com>, Anup Patel <anup.patel@wdc.com> Subject: [PATCH v5 03/13] target/riscv: Implement function kvm_arch_init_vcpu Date: Wed, 12 Jan 2022 16:13:19 +0800 [thread overview] Message-ID: <20220112081329.1835-4-jiangyifei@huawei.com> (raw) In-Reply-To: <20220112081329.1835-1-jiangyifei@huawei.com> Get isa info from kvm while kvm init. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> --- target/riscv/kvm.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 687dd4b621..9e66b4a97f 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -38,6 +38,24 @@ #include "qemu/log.h" #include "hw/loader.h" +static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, + uint64_t idx) +{ + uint64_t id = KVM_REG_RISCV | type | idx; + + switch (riscv_cpu_mxl(env)) { + case MXL_RV32: + id |= KVM_REG_SIZE_U32; + break; + case MXL_RV64: + id |= KVM_REG_SIZE_U64; + break; + default: + g_assert_not_reached(); + } + return id; +} + const KVMCapabilityInfo kvm_arch_required_capabilities[] = { KVM_CAP_LAST_INFO }; @@ -79,7 +97,21 @@ void kvm_arch_init_irq_routing(KVMState *s) int kvm_arch_init_vcpu(CPUState *cs) { - return 0; + int ret = 0; + target_ulong isa; + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + uint64_t id; + + id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, + KVM_REG_RISCV_CONFIG_REG(isa)); + ret = kvm_get_one_reg(cs, id, &isa); + if (ret) { + return ret; + } + env->misa_ext = isa; + + return ret; } int kvm_arch_msi_data_to_gsi(uint32_t data) -- 2.19.1
WARNING: multiple messages have this Message-ID (diff)
From: Yifei Jiang via <qemu-devel@nongnu.org> To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org> Cc: <kvm-riscv@lists.infradead.org>, <kvm@vger.kernel.org>, <libvir-list@redhat.com>, <anup@brainfault.org>, <palmer@dabbelt.com>, <Alistair.Francis@wdc.com>, <bin.meng@windriver.com>, <fanliang@huawei.com>, <wu.wubin@huawei.com>, <wanghaibin.wang@huawei.com>, <wanbo13@huawei.com>, Yifei Jiang <jiangyifei@huawei.com>, Mingwang Li <limingwang@huawei.com>, Alistair Francis <alistair.francis@wdc.com>, Anup Patel <anup.patel@wdc.com> Subject: [PATCH v5 03/13] target/riscv: Implement function kvm_arch_init_vcpu Date: Wed, 12 Jan 2022 16:13:19 +0800 [thread overview] Message-ID: <20220112081329.1835-4-jiangyifei@huawei.com> (raw) In-Reply-To: <20220112081329.1835-1-jiangyifei@huawei.com> Get isa info from kvm while kvm init. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> --- target/riscv/kvm.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 687dd4b621..9e66b4a97f 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -38,6 +38,24 @@ #include "qemu/log.h" #include "hw/loader.h" +static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, + uint64_t idx) +{ + uint64_t id = KVM_REG_RISCV | type | idx; + + switch (riscv_cpu_mxl(env)) { + case MXL_RV32: + id |= KVM_REG_SIZE_U32; + break; + case MXL_RV64: + id |= KVM_REG_SIZE_U64; + break; + default: + g_assert_not_reached(); + } + return id; +} + const KVMCapabilityInfo kvm_arch_required_capabilities[] = { KVM_CAP_LAST_INFO }; @@ -79,7 +97,21 @@ void kvm_arch_init_irq_routing(KVMState *s) int kvm_arch_init_vcpu(CPUState *cs) { - return 0; + int ret = 0; + target_ulong isa; + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + uint64_t id; + + id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, + KVM_REG_RISCV_CONFIG_REG(isa)); + ret = kvm_get_one_reg(cs, id, &isa); + if (ret) { + return ret; + } + env->misa_ext = isa; + + return ret; } int kvm_arch_msi_data_to_gsi(uint32_t data) -- 2.19.1
next prev parent reply other threads:[~2022-01-12 8:13 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-12 8:13 [PATCH v5 00/13] Add riscv kvm accel support Yifei Jiang 2022-01-12 8:13 ` Yifei Jiang via 2022-01-12 8:13 ` [PATCH v5 01/13] update-linux-headers: Add asm-riscv/kvm.h Yifei Jiang 2022-01-12 8:13 ` Yifei Jiang via 2022-01-12 8:13 ` [PATCH v5 02/13] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang 2022-01-12 8:13 ` Yifei Jiang via 2022-01-12 8:13 ` Yifei Jiang [this message] 2022-01-12 8:13 ` [PATCH v5 03/13] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang via 2022-01-12 8:13 ` [PATCH v5 04/13] target/riscv: Implement kvm_arch_get_registers Yifei Jiang 2022-01-12 8:13 ` Yifei Jiang via 2022-01-12 8:13 ` [PATCH v5 05/13] target/riscv: Implement kvm_arch_put_registers Yifei Jiang 2022-01-12 8:13 ` Yifei Jiang via 2022-01-12 8:13 ` [PATCH v5 06/13] target/riscv: Support start kernel directly by KVM Yifei Jiang 2022-01-12 8:13 ` Yifei Jiang via 2022-01-13 4:35 ` Anup Patel 2022-01-13 4:35 ` Anup Patel 2022-01-12 8:13 ` [PATCH v5 07/13] target/riscv: Support setting external interrupt " Yifei Jiang 2022-01-12 8:13 ` Yifei Jiang via 2022-01-12 8:13 ` [PATCH v5 08/13] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang 2022-01-12 8:13 ` Yifei Jiang via 2022-01-12 8:13 ` [PATCH v5 09/13] target/riscv: Add host cpu type Yifei Jiang 2022-01-12 8:13 ` Yifei Jiang via 2022-01-12 8:13 ` [PATCH v5 10/13] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang 2022-01-12 8:13 ` Yifei Jiang via 2022-01-12 8:13 ` [PATCH v5 11/13] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang 2022-01-12 8:13 ` Yifei Jiang via 2022-01-12 8:13 ` [PATCH v5 12/13] target/riscv: Support virtual time context synchronization Yifei Jiang 2022-01-12 8:13 ` Yifei Jiang via 2022-01-12 8:13 ` [PATCH v5 13/13] target/riscv: enable riscv kvm accel Yifei Jiang 2022-01-12 8:13 ` Yifei Jiang via 2022-01-13 4:30 ` Alistair Francis 2022-01-13 4:30 ` Alistair Francis 2022-01-13 4:41 ` Anup Patel 2022-01-13 4:41 ` Anup Patel 2022-01-17 22:48 ` [PATCH v5 00/13] Add riscv kvm accel support Alistair Francis 2022-01-17 22:48 ` Alistair Francis
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