From: Andre Przywara <andre.przywara@arm.com> To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@gmail.com>, Samuel Holland <samuel@sholland.org> Cc: Rob Herring <robh+dt@kernel.org>, Mesih Kilinc <mesihkilinc@gmail.com>, Icenowy Zheng <icenowy@aosc.io>, Jesse Taube <mr.bossman075@gmail.com>, Giulio Benetti <giulio.benetti@benettiengineering.com>, George Hilliard <thirtythreeforty@gmail.com>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH 04/14] ARM: dts: suniv: F1C100: add clock and reset macros Date: Mon, 7 Mar 2022 14:34:11 +0000 [thread overview] Message-ID: <20220307143421.1106209-5-andre.przywara@arm.com> (raw) In-Reply-To: <20220307143421.1106209-1-andre.przywara@arm.com> From: Jesse Taube <mr.bossman075@gmail.com> Include clock and reset macros and replace magic numbers. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index def830101448..922efd5e9457 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -4,6 +4,9 @@ * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com> */ +#include <dt-bindings/clock/suniv-ccu-f1c100s.h> +#include <dt-bindings/reset/suniv-ccu-f1c100s.h> + / { #address-cells = <1>; #size-cells = <1>; @@ -82,7 +85,7 @@ pio: pinctrl@1c20800 { compatible = "allwinner,suniv-f1c100s-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <38>, <39>, <40>; - clocks = <&ccu 37>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -116,8 +119,8 @@ uart0: serial@1c25000 { interrupts = <1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 38>; - resets = <&ccu 24>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; @@ -127,8 +130,8 @@ uart1: serial@1c25400 { interrupts = <2>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 39>; - resets = <&ccu 25>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; status = "disabled"; }; @@ -138,8 +141,8 @@ uart2: serial@1c25800 { interrupts = <3>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 40>; - resets = <&ccu 26>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; status = "disabled"; }; }; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Andre Przywara <andre.przywara@arm.com> To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@gmail.com>, Samuel Holland <samuel@sholland.org> Cc: Rob Herring <robh+dt@kernel.org>, Mesih Kilinc <mesihkilinc@gmail.com>, Icenowy Zheng <icenowy@aosc.io>, Jesse Taube <mr.bossman075@gmail.com>, Giulio Benetti <giulio.benetti@benettiengineering.com>, George Hilliard <thirtythreeforty@gmail.com>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH 04/14] ARM: dts: suniv: F1C100: add clock and reset macros Date: Mon, 7 Mar 2022 14:34:11 +0000 [thread overview] Message-ID: <20220307143421.1106209-5-andre.przywara@arm.com> (raw) In-Reply-To: <20220307143421.1106209-1-andre.przywara@arm.com> From: Jesse Taube <mr.bossman075@gmail.com> Include clock and reset macros and replace magic numbers. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index def830101448..922efd5e9457 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -4,6 +4,9 @@ * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com> */ +#include <dt-bindings/clock/suniv-ccu-f1c100s.h> +#include <dt-bindings/reset/suniv-ccu-f1c100s.h> + / { #address-cells = <1>; #size-cells = <1>; @@ -82,7 +85,7 @@ pio: pinctrl@1c20800 { compatible = "allwinner,suniv-f1c100s-pinctrl"; reg = <0x01c20800 0x400>; interrupts = <38>, <39>, <40>; - clocks = <&ccu 37>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; @@ -116,8 +119,8 @@ uart0: serial@1c25000 { interrupts = <1>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 38>; - resets = <&ccu 24>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; @@ -127,8 +130,8 @@ uart1: serial@1c25400 { interrupts = <2>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 39>; - resets = <&ccu 25>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; status = "disabled"; }; @@ -138,8 +141,8 @@ uart2: serial@1c25800 { interrupts = <3>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&ccu 40>; - resets = <&ccu 26>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; status = "disabled"; }; }; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-03-07 14:34 UTC|newest] Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-03-07 14:34 [PATCH 00/14] ARM: suniv: dts: update Allwinner F1C100 Andre Przywara 2022-03-07 14:34 ` Andre Przywara 2022-03-07 14:34 ` [PATCH 01/14] dt-bindings: watchdog: sunxi: fix F1C100s compatible Andre Przywara 2022-03-07 14:34 ` Andre Przywara 2022-03-08 16:08 ` Rob Herring 2022-03-08 16:08 ` Rob Herring 2022-03-09 23:02 ` Guenter Roeck 2022-03-09 23:02 ` Guenter Roeck 2022-03-10 0:46 ` Samuel Holland 2022-03-10 0:46 ` Samuel Holland 2022-03-14 17:39 ` Andre Przywara 2022-03-14 17:39 ` Andre Przywara 2022-03-07 14:34 ` [PATCH 02/14] ARM: dts: suniv: F1C100: fix watchdog compatible Andre Przywara 2022-03-07 14:34 ` Andre Przywara 2022-03-09 23:03 ` Guenter Roeck 2022-03-09 23:03 ` Guenter Roeck 2022-03-07 14:34 ` [PATCH 03/14] dt-bindings: arm: sunxi: document LicheePi Nano name Andre Przywara 2022-03-07 14:34 ` Andre Przywara 2022-03-08 16:09 ` Rob Herring 2022-03-08 16:09 ` Rob Herring 2022-03-11 1:27 ` Samuel Holland 2022-03-11 1:27 ` Samuel Holland 2022-03-07 14:34 ` Andre Przywara [this message] 2022-03-07 14:34 ` [PATCH 04/14] ARM: dts: suniv: F1C100: add clock and reset macros Andre Przywara 2022-03-11 1:30 ` Samuel Holland 2022-03-11 1:30 ` Samuel Holland 2022-03-07 14:34 ` [PATCH 05/14] ARM: dts: suniv: F1C100: fix CPU node Andre Przywara 2022-03-07 14:34 ` Andre Przywara 2022-03-08 2:44 ` Jesse Taube 2022-03-08 2:44 ` Jesse Taube 2022-03-08 4:23 ` Icenowy Zheng 2022-03-08 4:23 ` Icenowy Zheng 2022-03-08 10:42 ` Andre Przywara 2022-03-08 10:42 ` Andre Przywara 2022-03-07 14:34 ` [PATCH 06/14] ARM: dts: suniv: F1C100: fix timer node Andre Przywara 2022-03-07 14:34 ` Andre Przywara 2022-03-11 2:19 ` Samuel Holland 2022-03-11 2:19 ` Samuel Holland 2022-03-07 14:34 ` [PATCH 07/14] dt-bindings: mmc: sunxi: add Allwinner F1c100s compatible Andre Przywara 2022-03-07 14:34 ` Andre Przywara 2022-03-08 16:10 ` Rob Herring 2022-03-08 16:10 ` Rob Herring 2022-03-11 2:19 ` Samuel Holland 2022-03-11 2:19 ` Samuel Holland 2022-03-11 15:41 ` Ulf Hansson 2022-03-11 15:41 ` Ulf Hansson 2022-03-07 14:34 ` [PATCH 08/14] ARM: dts: suniv: F1C100: add MMC controllers Andre Przywara 2022-03-07 14:34 ` Andre Przywara 2022-03-11 2:19 ` Samuel Holland 2022-03-11 2:19 ` Samuel Holland 2022-03-07 14:34 ` [PATCH 09/14] ARM: dts: suniv: licheepi-nano: add microSD card Andre Przywara 2022-03-07 14:34 ` Andre Przywara 2022-03-11 2:19 ` Samuel Holland 2022-03-11 2:19 ` Samuel Holland 2022-03-07 14:34 ` [PATCH 10/14] dt-bindings: spi: sunxi: document F1C100 controllers Andre Przywara 2022-03-07 14:34 ` Andre Przywara 2022-03-08 16:10 ` Rob Herring 2022-03-08 16:10 ` Rob Herring 2022-03-11 2:19 ` Samuel Holland 2022-03-11 2:19 ` Samuel Holland 2022-03-07 14:34 ` [PATCH 11/14] ARM: dts: suniv: F1C100: add SPI support Andre Przywara 2022-03-07 14:34 ` Andre Przywara 2022-03-11 2:19 ` Samuel Holland 2022-03-11 2:19 ` Samuel Holland 2022-03-11 13:33 ` Andre Przywara 2022-03-11 13:33 ` Andre Przywara 2022-03-07 14:34 ` [PATCH 12/14] ARM: dts: suniv: licheepi-nano: add SPI flash Andre Przywara 2022-03-07 14:34 ` Andre Przywara 2022-03-11 2:20 ` Samuel Holland 2022-03-11 2:20 ` Samuel Holland 2022-03-07 14:34 ` [PATCH 13/14] ARM: configs: sync multi_v5_defconfig from savedefconfig Andre Przywara 2022-03-07 14:34 ` Andre Przywara 2022-03-08 9:38 ` Arnd Bergmann 2022-03-08 9:38 ` Arnd Bergmann 2022-03-08 12:07 ` Andre Przywara 2022-03-08 12:07 ` Andre Przywara 2022-03-08 13:33 ` Arnd Bergmann 2022-03-08 13:33 ` Arnd Bergmann 2022-03-08 13:40 ` Arnd Bergmann 2022-03-08 13:40 ` Arnd Bergmann 2022-03-08 14:30 ` Nicolas Ferre 2022-03-08 14:30 ` Nicolas Ferre 2022-03-08 15:17 ` Arnd Bergmann 2022-03-08 15:17 ` Arnd Bergmann 2022-03-10 10:33 ` Andre Przywara 2022-03-10 10:33 ` Andre Przywara 2022-03-07 14:34 ` [PATCH 14/14] ARM: configs: multi_v5: Enable Allwinner F1C100 Andre Przywara 2022-03-07 14:34 ` Andre Przywara 2022-03-07 18:03 ` [PATCH 00/14] ARM: suniv: dts: update " Jesse Taube 2022-03-07 18:03 ` Jesse Taube 2022-03-07 18:22 ` Giulio Benetti 2022-03-07 18:22 ` Giulio Benetti 2022-03-11 1:38 ` Jesse Taube 2022-03-11 1:38 ` Jesse Taube
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