From: Conor Dooley <mail@conchuod.ie>
To: Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
Anup Patel <anup@brainfault.org>,
Conor Dooley <conor.dooley@microchip.com>,
Guo Ren <guoren@kernel.org>, Sagar Kadam <sagar.kadam@sifive.com>,
Jessica Clarke <jrtc27@jrtc27.com>,
Andrew Jones <ajones@ventanamicro.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org,
Rob Herring <robh@kernel.org>
Subject: [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible
Date: Tue, 23 Aug 2022 19:33:18 +0100 [thread overview]
Message-ID: <20220823183319.3314940-3-mail@conchuod.ie> (raw)
In-Reply-To: <20220823183319.3314940-1-mail@conchuod.ie>
From: Conor Dooley <conor.dooley@microchip.com>
While "real" hardware might not use the compatible string "riscv,plic0"
it is present in the driver & QEMU uses it for automatically generated
virt machine dtbs. To avoid dt-validate problems with QEMU produced
dtbs, such as the following, add it to the binding.
riscv-virt.dtb: plic@c000000: compatible: 'oneOf' conditional failed, one must be fixed:
'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'starfive,jh7100-plic', 'canaan,k210-plic']
'sifive,plic-1.0.0' is not one of ['allwinner,sun20i-d1-plic']
'sifive,plic-1.0.0' was expected
'thead,c900-plic' was expected
riscv-virt.dtb: plic@c000000: '#address-cells' is a required property
Reported-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 92e0f8c3eff2..99e01f4d0a69 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -66,6 +66,11 @@ properties:
- enum:
- allwinner,sun20i-d1-plic
- const: thead,c900-plic
+ - items:
+ - const: sifive,plic-1.0.0
+ - const: riscv,plic0
+ deprecated: true
+ description: For the QEMU virt machine only
reg:
maxItems: 1
--
2.37.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <mail@conchuod.ie>
To: Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
Anup Patel <anup@brainfault.org>,
Conor Dooley <conor.dooley@microchip.com>,
Guo Ren <guoren@kernel.org>, Sagar Kadam <sagar.kadam@sifive.com>,
Jessica Clarke <jrtc27@jrtc27.com>,
Andrew Jones <ajones@ventanamicro.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org,
Rob Herring <robh@kernel.org>
Subject: [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible
Date: Tue, 23 Aug 2022 19:33:18 +0100 [thread overview]
Message-ID: <20220823183319.3314940-3-mail@conchuod.ie> (raw)
In-Reply-To: <20220823183319.3314940-1-mail@conchuod.ie>
From: Conor Dooley <conor.dooley@microchip.com>
While "real" hardware might not use the compatible string "riscv,plic0"
it is present in the driver & QEMU uses it for automatically generated
virt machine dtbs. To avoid dt-validate problems with QEMU produced
dtbs, such as the following, add it to the binding.
riscv-virt.dtb: plic@c000000: compatible: 'oneOf' conditional failed, one must be fixed:
'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'starfive,jh7100-plic', 'canaan,k210-plic']
'sifive,plic-1.0.0' is not one of ['allwinner,sun20i-d1-plic']
'sifive,plic-1.0.0' was expected
'thead,c900-plic' was expected
riscv-virt.dtb: plic@c000000: '#address-cells' is a required property
Reported-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 92e0f8c3eff2..99e01f4d0a69 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -66,6 +66,11 @@ properties:
- enum:
- allwinner,sun20i-d1-plic
- const: thead,c900-plic
+ - items:
+ - const: sifive,plic-1.0.0
+ - const: riscv,plic0
+ deprecated: true
+ description: For the QEMU virt machine only
reg:
maxItems: 1
--
2.37.1
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <mail@conchuod.ie>
To: Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
Anup Patel <anup@brainfault.org>,
Conor Dooley <conor.dooley@microchip.com>,
Guo Ren <guoren@kernel.org>, Sagar Kadam <sagar.kadam@sifive.com>,
Jessica Clarke <jrtc27@jrtc27.com>,
Andrew Jones <ajones@ventanamicro.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, qemu-riscv@nongnu.org,
Rob Herring <robh@kernel.org>
Subject: [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive, plic: add legacy riscv compatible
Date: Tue, 23 Aug 2022 19:33:18 +0100 [thread overview]
Message-ID: <20220823183319.3314940-3-mail@conchuod.ie> (raw)
In-Reply-To: <20220823183319.3314940-1-mail@conchuod.ie>
From: Conor Dooley <conor.dooley@microchip.com>
While "real" hardware might not use the compatible string "riscv,plic0"
it is present in the driver & QEMU uses it for automatically generated
virt machine dtbs. To avoid dt-validate problems with QEMU produced
dtbs, such as the following, add it to the binding.
riscv-virt.dtb: plic@c000000: compatible: 'oneOf' conditional failed, one must be fixed:
'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'starfive,jh7100-plic', 'canaan,k210-plic']
'sifive,plic-1.0.0' is not one of ['allwinner,sun20i-d1-plic']
'sifive,plic-1.0.0' was expected
'thead,c900-plic' was expected
riscv-virt.dtb: plic@c000000: '#address-cells' is a required property
Reported-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 92e0f8c3eff2..99e01f4d0a69 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -66,6 +66,11 @@ properties:
- enum:
- allwinner,sun20i-d1-plic
- const: thead,c900-plic
+ - items:
+ - const: sifive,plic-1.0.0
+ - const: riscv,plic0
+ deprecated: true
+ description: For the QEMU virt machine only
reg:
maxItems: 1
--
2.37.1
next prev parent reply other threads:[~2022-08-23 18:34 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-23 18:33 [PATCH v4 0/4] Fix dt-validate issues on qemu dtbdumps due to dt-bindings Conor Dooley
2022-08-23 18:33 ` Conor Dooley
2022-08-23 18:33 ` [PATCH v4 1/4] dt-bindings: timer: sifive,clint: add legacy riscv compatible Conor Dooley
2022-08-23 18:33 ` [PATCH v4 1/4] dt-bindings: timer: sifive, clint: " Conor Dooley
2022-08-23 18:33 ` [PATCH v4 1/4] dt-bindings: timer: sifive,clint: " Conor Dooley
2022-08-24 18:02 ` Heiko Stübner
2022-08-24 18:02 ` [PATCH v4 1/4] dt-bindings: timer: sifive, clint: " Heiko Stübner
2022-08-24 18:02 ` [PATCH v4 1/4] dt-bindings: timer: sifive,clint: " Heiko Stübner
2022-08-23 18:33 ` Conor Dooley [this message]
2022-08-23 18:33 ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive, plic: " Conor Dooley
2022-08-23 18:33 ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: " Conor Dooley
2022-08-24 17:44 ` Heiko Stübner
2022-08-24 17:44 ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive, plic: " Heiko Stübner
2022-08-24 17:44 ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: " Heiko Stübner
2022-08-24 17:55 ` Conor.Dooley
2022-08-24 17:55 ` Conor.Dooley
2022-08-24 18:00 ` Heiko Stübner
2022-08-24 18:00 ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive, plic: " Heiko Stübner
2022-08-24 18:00 ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: " Heiko Stübner
2022-08-24 18:02 ` Heiko Stübner
2022-08-24 18:02 ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive, plic: " Heiko Stübner
2022-08-24 18:02 ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: " Heiko Stübner
2022-08-23 18:33 ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators Conor Dooley
2022-08-23 18:33 ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv, isa " Conor Dooley
2022-08-23 18:33 ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa " Conor Dooley
2022-08-24 17:41 ` Heiko Stübner
2022-08-24 17:41 ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv, isa " Heiko Stübner
2022-08-24 17:41 ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa " Heiko Stübner
2022-08-30 18:03 ` Rob Herring
2022-08-30 18:03 ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv, isa " Rob Herring
2022-08-30 18:03 ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa " Rob Herring
2022-08-23 18:33 ` [PATCH v4 4/4] dt-bindings: riscv: isa string bonus content Conor Dooley
2022-08-23 18:33 ` Conor Dooley
2022-08-24 13:26 ` Rob Herring
2022-08-24 13:26 ` Rob Herring
2022-09-15 18:45 ` [PATCH v4 0/4] Fix dt-validate issues on qemu dtbdumps due to dt-bindings Conor.Dooley
2022-09-15 18:45 ` Conor.Dooley
2022-10-13 5:15 ` (subset) " Palmer Dabbelt
2022-10-13 5:15 ` Palmer Dabbelt
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