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From: Rob Herring <robh@kernel.org>
To: Conor Dooley <mail@conchuod.ie>
Cc: Guo Ren <guoren@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	linux-kernel@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Jessica Clarke <jrtc27@jrtc27.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	qemu-riscv@nongnu.org, Anup Patel <anup@brainfault.org>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Marc Zyngier <maz@kernel.org>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	Sagar Kadam <sagar.kadam@sifive.com>
Subject: Re: [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators
Date: Tue, 30 Aug 2022 13:03:41 -0500	[thread overview]
Message-ID: <20220830180341.GA1769896-robh@kernel.org> (raw)
In-Reply-To: <20220823183319.3314940-4-mail@conchuod.ie>

On Tue, 23 Aug 2022 19:33:19 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> The QEMU virt and spike machines currently export a riscv,isa string of
> "rv64imafdcsuh",
> 
> While the RISC-V foundation has been ratifying a bunch of extenstions
> etc, the kernel has remained relatively static with what hardware is
> supported - but the same is not true of QEMU. Using the virt machine
> and running dt-validate on the dumped dtb fails, partly due to the
> unexpected isa string.
> 
> Rather than enumerate the many many possbilities, change the pattern
> to a regex, with the following assumptions:
> - ima are required
> - the single letter order is fixed & we don't care about things that
>   can't even do "ima"
> - the standard multi letter extensions are all in a "_z<foo>" format
>   where the first letter of <foo> is a valid single letter extension
> - _s & _h are used for supervisor and hyper visor extensions
> - convention says that after the first two chars, a standard multi
>   letter extension name could be an english word (ifencei anyone?) so
>   it's not worth restricting the charset
> - as the above is just convention, don't apply any charset restrictions
>   to reduce future churn
> - vendor ISA extensions begind with _x and have no charset restrictions
> - we don't care about an e extension from an OS pov
> - that attempting to validate the contents of the multiletter extensions
>   with dt-validate beyond the formatting is a futile, massively verbose
>   or unwieldy exercise at best
> 
> The following limitations also apply:
> - multi letter extension ordering is not enforced. dt-schema does not
>   appear to allow for named match groups, so the resulting regex would
>   be even more of a headache
> - ditto for the numbered extensions
> 
> Finally, add me as a maintainer of the binding so that when it breaks
> in the future, I can be held responsible!
> 
> Reported-by: Rob Herring <robh@kernel.org>
> Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Acked-by: Guo Ren <guoren@kernel.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> Palmer, feel free to drop the maintainer addition. I just mostly want
> to clean up my own mess on this when they decide to ratify more
> extensions & this comes back up again.
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Conor Dooley <mail@conchuod.ie>
Cc: Guo Ren <guoren@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	linux-kernel@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Jessica Clarke <jrtc27@jrtc27.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	qemu-riscv@nongnu.org, Anup Patel <anup@brainfault.org>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Marc Zyngier <maz@kernel.org>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	Sagar Kadam <sagar.kadam@sifive.com>
Subject: Re: [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators
Date: Tue, 30 Aug 2022 13:03:41 -0500	[thread overview]
Message-ID: <20220830180341.GA1769896-robh@kernel.org> (raw)
In-Reply-To: <20220823183319.3314940-4-mail@conchuod.ie>

On Tue, 23 Aug 2022 19:33:19 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> The QEMU virt and spike machines currently export a riscv,isa string of
> "rv64imafdcsuh",
> 
> While the RISC-V foundation has been ratifying a bunch of extenstions
> etc, the kernel has remained relatively static with what hardware is
> supported - but the same is not true of QEMU. Using the virt machine
> and running dt-validate on the dumped dtb fails, partly due to the
> unexpected isa string.
> 
> Rather than enumerate the many many possbilities, change the pattern
> to a regex, with the following assumptions:
> - ima are required
> - the single letter order is fixed & we don't care about things that
>   can't even do "ima"
> - the standard multi letter extensions are all in a "_z<foo>" format
>   where the first letter of <foo> is a valid single letter extension
> - _s & _h are used for supervisor and hyper visor extensions
> - convention says that after the first two chars, a standard multi
>   letter extension name could be an english word (ifencei anyone?) so
>   it's not worth restricting the charset
> - as the above is just convention, don't apply any charset restrictions
>   to reduce future churn
> - vendor ISA extensions begind with _x and have no charset restrictions
> - we don't care about an e extension from an OS pov
> - that attempting to validate the contents of the multiletter extensions
>   with dt-validate beyond the formatting is a futile, massively verbose
>   or unwieldy exercise at best
> 
> The following limitations also apply:
> - multi letter extension ordering is not enforced. dt-schema does not
>   appear to allow for named match groups, so the resulting regex would
>   be even more of a headache
> - ditto for the numbered extensions
> 
> Finally, add me as a maintainer of the binding so that when it breaks
> in the future, I can be held responsible!
> 
> Reported-by: Rob Herring <robh@kernel.org>
> Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Acked-by: Guo Ren <guoren@kernel.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> Palmer, feel free to drop the maintainer addition. I just mostly want
> to clean up my own mess on this when they decide to ratify more
> extensions & this comes back up again.
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Conor Dooley <mail@conchuod.ie>
Cc: Guo Ren <guoren@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	linux-kernel@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Jessica Clarke <jrtc27@jrtc27.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	qemu-riscv@nongnu.org, Anup Patel <anup@brainfault.org>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Marc Zyngier <maz@kernel.org>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	Sagar Kadam <sagar.kadam@sifive.com>
Subject: Re: [PATCH v4 3/4] dt-bindings: riscv: add new riscv, isa strings for emulators
Date: Tue, 30 Aug 2022 13:03:41 -0500	[thread overview]
Message-ID: <20220830180341.GA1769896-robh@kernel.org> (raw)
In-Reply-To: <20220823183319.3314940-4-mail@conchuod.ie>

On Tue, 23 Aug 2022 19:33:19 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> The QEMU virt and spike machines currently export a riscv,isa string of
> "rv64imafdcsuh",
> 
> While the RISC-V foundation has been ratifying a bunch of extenstions
> etc, the kernel has remained relatively static with what hardware is
> supported - but the same is not true of QEMU. Using the virt machine
> and running dt-validate on the dumped dtb fails, partly due to the
> unexpected isa string.
> 
> Rather than enumerate the many many possbilities, change the pattern
> to a regex, with the following assumptions:
> - ima are required
> - the single letter order is fixed & we don't care about things that
>   can't even do "ima"
> - the standard multi letter extensions are all in a "_z<foo>" format
>   where the first letter of <foo> is a valid single letter extension
> - _s & _h are used for supervisor and hyper visor extensions
> - convention says that after the first two chars, a standard multi
>   letter extension name could be an english word (ifencei anyone?) so
>   it's not worth restricting the charset
> - as the above is just convention, don't apply any charset restrictions
>   to reduce future churn
> - vendor ISA extensions begind with _x and have no charset restrictions
> - we don't care about an e extension from an OS pov
> - that attempting to validate the contents of the multiletter extensions
>   with dt-validate beyond the formatting is a futile, massively verbose
>   or unwieldy exercise at best
> 
> The following limitations also apply:
> - multi letter extension ordering is not enforced. dt-schema does not
>   appear to allow for named match groups, so the resulting regex would
>   be even more of a headache
> - ditto for the numbered extensions
> 
> Finally, add me as a maintainer of the binding so that when it breaks
> in the future, I can be held responsible!
> 
> Reported-by: Rob Herring <robh@kernel.org>
> Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Acked-by: Guo Ren <guoren@kernel.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> Palmer, feel free to drop the maintainer addition. I just mostly want
> to clean up my own mess on this when they decide to ratify more
> extensions & this comes back up again.
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>


  parent reply	other threads:[~2022-08-30 18:04 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-23 18:33 [PATCH v4 0/4] Fix dt-validate issues on qemu dtbdumps due to dt-bindings Conor Dooley
2022-08-23 18:33 ` Conor Dooley
2022-08-23 18:33 ` [PATCH v4 1/4] dt-bindings: timer: sifive,clint: add legacy riscv compatible Conor Dooley
2022-08-23 18:33   ` [PATCH v4 1/4] dt-bindings: timer: sifive, clint: " Conor Dooley
2022-08-23 18:33   ` [PATCH v4 1/4] dt-bindings: timer: sifive,clint: " Conor Dooley
2022-08-24 18:02   ` Heiko Stübner
2022-08-24 18:02     ` [PATCH v4 1/4] dt-bindings: timer: sifive, clint: " Heiko Stübner
2022-08-24 18:02     ` [PATCH v4 1/4] dt-bindings: timer: sifive,clint: " Heiko Stübner
2022-08-23 18:33 ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: " Conor Dooley
2022-08-23 18:33   ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive, plic: " Conor Dooley
2022-08-23 18:33   ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: " Conor Dooley
2022-08-24 17:44   ` Heiko Stübner
2022-08-24 17:44     ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive, plic: " Heiko Stübner
2022-08-24 17:44     ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: " Heiko Stübner
2022-08-24 17:55     ` Conor.Dooley
2022-08-24 17:55       ` Conor.Dooley
2022-08-24 18:00       ` Heiko Stübner
2022-08-24 18:00         ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive, plic: " Heiko Stübner
2022-08-24 18:00         ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: " Heiko Stübner
2022-08-24 18:02   ` Heiko Stübner
2022-08-24 18:02     ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive, plic: " Heiko Stübner
2022-08-24 18:02     ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: " Heiko Stübner
2022-08-23 18:33 ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators Conor Dooley
2022-08-23 18:33   ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv, isa " Conor Dooley
2022-08-23 18:33   ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa " Conor Dooley
2022-08-24 17:41   ` Heiko Stübner
2022-08-24 17:41     ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv, isa " Heiko Stübner
2022-08-24 17:41     ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa " Heiko Stübner
2022-08-30 18:03   ` Rob Herring [this message]
2022-08-30 18:03     ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv, isa " Rob Herring
2022-08-30 18:03     ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa " Rob Herring
2022-08-23 18:33 ` [PATCH v4 4/4] dt-bindings: riscv: isa string bonus content Conor Dooley
2022-08-23 18:33   ` Conor Dooley
2022-08-24 13:26   ` Rob Herring
2022-08-24 13:26     ` Rob Herring
2022-09-15 18:45 ` [PATCH v4 0/4] Fix dt-validate issues on qemu dtbdumps due to dt-bindings Conor.Dooley
2022-09-15 18:45   ` Conor.Dooley
2022-10-13  5:15 ` (subset) " Palmer Dabbelt
2022-10-13  5:15   ` Palmer Dabbelt

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