From: <Conor.Dooley@microchip.com> To: <heiko@sntech.de>, <tglx@linutronix.de>, <maz@kernel.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <palmer@dabbelt.com>, <paul.walmsley@sifive.com>, <aou@eecs.berkeley.edu>, <linux-riscv@lists.infradead.org> Cc: <daniel.lezcano@linaro.org>, <anup@brainfault.org>, <Conor.Dooley@microchip.com>, <guoren@kernel.org>, <sagar.kadam@sifive.com>, <jrtc27@jrtc27.com>, <ajones@ventanamicro.com>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <qemu-riscv@nongnu.org>, <robh@kernel.org> Subject: Re: [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible Date: Wed, 24 Aug 2022 17:55:17 +0000 [thread overview] Message-ID: <95fe8df7-581e-f7ec-be1f-1c6e06cb30a4@microchip.com> (raw) In-Reply-To: <3948407.AJdgDx1Vlc@diego> On 24/08/2022 18:44, Heiko Stübner wrote: > Am Dienstag, 23. August 2022, 20:33:18 CEST schrieb Conor Dooley: >> From: Conor Dooley <conor.dooley@microchip.com> >> >> While "real" hardware might not use the compatible string "riscv,plic0" >> it is present in the driver & QEMU uses it for automatically generated >> virt machine dtbs. To avoid dt-validate problems with QEMU produced >> dtbs, such as the following, add it to the binding. >> >> riscv-virt.dtb: plic@c000000: compatible: 'oneOf' conditional failed, one must be fixed: >> 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'starfive,jh7100-plic', 'canaan,k210-plic'] >> 'sifive,plic-1.0.0' is not one of ['allwinner,sun20i-d1-plic'] >> 'sifive,plic-1.0.0' was expected >> 'thead,c900-plic' was expected >> riscv-virt.dtb: plic@c000000: '#address-cells' is a required property >> >> Reported-by: Rob Herring <robh@kernel.org> >> Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/ >> Reviewed-by: Rob Herring <robh@kernel.org> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >> --- >> .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml >> index 92e0f8c3eff2..99e01f4d0a69 100644 >> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml >> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml >> @@ -66,6 +66,11 @@ properties: >> - enum: >> - allwinner,sun20i-d1-plic >> - const: thead,c900-plic >> + - items: >> + - const: sifive,plic-1.0.0 >> + - const: riscv,plic0 >> + deprecated: true > > hmm, when setting this to deprecated, does this mean qemu was changed > to not use that compatible anymore? > > I.e. reading deprecated I'd assume that this is kept around for old qemu builds? I did not make that change to QEMU. From v1 [0]: Rob: > Conor: >> In arm's virt.c they use the generic gic compatible & I don't see any >> evidence of other archs using "qemu,foo" bindings. I suppose there's >> always the option of just removing the "riscv,plic0" from the riscv's >> virt.c > > I think we're pretty much stuck with what's in use already. > I'm on the fence whether to mark it deprecated though if there is no > plan to 'fix' it. Doesn't really matter until the tools can selectively > remove deprecated properties from validation. My interpretation was "do not use this compatible in any new devicetrees". I don't really have any strong feelings here. Maybe the description is sufficient? Thanks, Conor, 0 - https://lore.kernel.org/linux-riscv/20220809141436.GA1706120-robh@kernel.org/ > >> + description: For the QEMU virt machine only >> >> reg: >> maxItems: 1 >> > > > >
WARNING: multiple messages have this Message-ID (diff)
From: <Conor.Dooley@microchip.com> To: <heiko@sntech.de>, <tglx@linutronix.de>, <maz@kernel.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <palmer@dabbelt.com>, <paul.walmsley@sifive.com>, <aou@eecs.berkeley.edu>, <linux-riscv@lists.infradead.org> Cc: <daniel.lezcano@linaro.org>, <anup@brainfault.org>, <Conor.Dooley@microchip.com>, <guoren@kernel.org>, <sagar.kadam@sifive.com>, <jrtc27@jrtc27.com>, <ajones@ventanamicro.com>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <qemu-riscv@nongnu.org>, <robh@kernel.org> Subject: Re: [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: add legacy riscv compatible Date: Wed, 24 Aug 2022 17:55:17 +0000 [thread overview] Message-ID: <95fe8df7-581e-f7ec-be1f-1c6e06cb30a4@microchip.com> (raw) In-Reply-To: <3948407.AJdgDx1Vlc@diego> On 24/08/2022 18:44, Heiko Stübner wrote: > Am Dienstag, 23. August 2022, 20:33:18 CEST schrieb Conor Dooley: >> From: Conor Dooley <conor.dooley@microchip.com> >> >> While "real" hardware might not use the compatible string "riscv,plic0" >> it is present in the driver & QEMU uses it for automatically generated >> virt machine dtbs. To avoid dt-validate problems with QEMU produced >> dtbs, such as the following, add it to the binding. >> >> riscv-virt.dtb: plic@c000000: compatible: 'oneOf' conditional failed, one must be fixed: >> 'sifive,plic-1.0.0' is not one of ['sifive,fu540-c000-plic', 'starfive,jh7100-plic', 'canaan,k210-plic'] >> 'sifive,plic-1.0.0' is not one of ['allwinner,sun20i-d1-plic'] >> 'sifive,plic-1.0.0' was expected >> 'thead,c900-plic' was expected >> riscv-virt.dtb: plic@c000000: '#address-cells' is a required property >> >> Reported-by: Rob Herring <robh@kernel.org> >> Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/ >> Reviewed-by: Rob Herring <robh@kernel.org> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >> --- >> .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml >> index 92e0f8c3eff2..99e01f4d0a69 100644 >> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml >> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml >> @@ -66,6 +66,11 @@ properties: >> - enum: >> - allwinner,sun20i-d1-plic >> - const: thead,c900-plic >> + - items: >> + - const: sifive,plic-1.0.0 >> + - const: riscv,plic0 >> + deprecated: true > > hmm, when setting this to deprecated, does this mean qemu was changed > to not use that compatible anymore? > > I.e. reading deprecated I'd assume that this is kept around for old qemu builds? I did not make that change to QEMU. From v1 [0]: Rob: > Conor: >> In arm's virt.c they use the generic gic compatible & I don't see any >> evidence of other archs using "qemu,foo" bindings. I suppose there's >> always the option of just removing the "riscv,plic0" from the riscv's >> virt.c > > I think we're pretty much stuck with what's in use already. > I'm on the fence whether to mark it deprecated though if there is no > plan to 'fix' it. Doesn't really matter until the tools can selectively > remove deprecated properties from validation. My interpretation was "do not use this compatible in any new devicetrees". I don't really have any strong feelings here. Maybe the description is sufficient? Thanks, Conor, 0 - https://lore.kernel.org/linux-riscv/20220809141436.GA1706120-robh@kernel.org/ > >> + description: For the QEMU virt machine only >> >> reg: >> maxItems: 1 >> > > > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-08-24 17:55 UTC|newest] Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-08-23 18:33 [PATCH v4 0/4] Fix dt-validate issues on qemu dtbdumps due to dt-bindings Conor Dooley 2022-08-23 18:33 ` Conor Dooley 2022-08-23 18:33 ` [PATCH v4 1/4] dt-bindings: timer: sifive,clint: add legacy riscv compatible Conor Dooley 2022-08-23 18:33 ` [PATCH v4 1/4] dt-bindings: timer: sifive, clint: " Conor Dooley 2022-08-23 18:33 ` [PATCH v4 1/4] dt-bindings: timer: sifive,clint: " Conor Dooley 2022-08-24 18:02 ` Heiko Stübner 2022-08-24 18:02 ` [PATCH v4 1/4] dt-bindings: timer: sifive, clint: " Heiko Stübner 2022-08-24 18:02 ` [PATCH v4 1/4] dt-bindings: timer: sifive,clint: " Heiko Stübner 2022-08-23 18:33 ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: " Conor Dooley 2022-08-23 18:33 ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive, plic: " Conor Dooley 2022-08-23 18:33 ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: " Conor Dooley 2022-08-24 17:44 ` Heiko Stübner 2022-08-24 17:44 ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive, plic: " Heiko Stübner 2022-08-24 17:44 ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: " Heiko Stübner 2022-08-24 17:55 ` Conor.Dooley [this message] 2022-08-24 17:55 ` Conor.Dooley 2022-08-24 18:00 ` Heiko Stübner 2022-08-24 18:00 ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive, plic: " Heiko Stübner 2022-08-24 18:00 ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: " Heiko Stübner 2022-08-24 18:02 ` Heiko Stübner 2022-08-24 18:02 ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive, plic: " Heiko Stübner 2022-08-24 18:02 ` [PATCH v4 2/4] dt-bindings: interrupt-controller: sifive,plic: " Heiko Stübner 2022-08-23 18:33 ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa strings for emulators Conor Dooley 2022-08-23 18:33 ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv, isa " Conor Dooley 2022-08-23 18:33 ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa " Conor Dooley 2022-08-24 17:41 ` Heiko Stübner 2022-08-24 17:41 ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv, isa " Heiko Stübner 2022-08-24 17:41 ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa " Heiko Stübner 2022-08-30 18:03 ` Rob Herring 2022-08-30 18:03 ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv, isa " Rob Herring 2022-08-30 18:03 ` [PATCH v4 3/4] dt-bindings: riscv: add new riscv,isa " Rob Herring 2022-08-23 18:33 ` [PATCH v4 4/4] dt-bindings: riscv: isa string bonus content Conor Dooley 2022-08-23 18:33 ` Conor Dooley 2022-08-24 13:26 ` Rob Herring 2022-08-24 13:26 ` Rob Herring 2022-09-15 18:45 ` [PATCH v4 0/4] Fix dt-validate issues on qemu dtbdumps due to dt-bindings Conor.Dooley 2022-09-15 18:45 ` Conor.Dooley 2022-10-13 5:15 ` (subset) " Palmer Dabbelt 2022-10-13 5:15 ` Palmer Dabbelt
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