From: Claudiu <claudiu.beznea@tuxon.dev> To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Subject: [PATCH 16/17] arm64: dts: renesas: r9a08g045: Update #power-domain-cells = <1> Date: Thu, 8 Feb 2024 14:42:59 +0200 [thread overview] Message-ID: <20240208124300.2740313-17-claudiu.beznea.uj@bp.renesas.com> (raw) In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Update CPG #power-domain-cells = <1> and move all the IPs to be part of the IP specific power domain as the driver has been modified to support multiple power domains. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index dfee878c0f49..11be621aaa82 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -62,7 +62,7 @@ scif0: serial@1004b800 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_SCIF0>; resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>; status = "disabled"; }; @@ -74,7 +74,7 @@ cpg: clock-controller@11010000 { clock-names = "extal"; #clock-cells = <2>; #reset-cells = <1>; - #power-domain-cells = <0>; + #power-domain-cells = <1>; }; sysc: system-controller@11020000 { @@ -99,7 +99,7 @@ pinctrl: pinctrl@11030000 { interrupt-parent = <&irqc>; gpio-ranges = <&pinctrl 0 0 152>; clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_ALWAYS_ON>; resets = <&cpg R9A08G045_GPIO_RSTN>, <&cpg R9A08G045_GPIO_PORT_RESETN>, <&cpg R9A08G045_GPIO_SPARE_RESETN>; @@ -168,7 +168,7 @@ irqc: interrupt-controller@11050000 { clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>, <&cpg CPG_MOD R9A08G045_IA55_PCLK>; clock-names = "clk", "pclk"; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_ALWAYS_ON>; resets = <&cpg R9A08G045_IA55_RESETN>; }; @@ -183,7 +183,7 @@ sdhi0: mmc@11c00000 { <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A08G045_SDHI0_IXRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_SDHI0>; status = "disabled"; }; @@ -198,7 +198,7 @@ sdhi1: mmc@11c10000 { <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A08G045_SDHI1_IXRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_SDHI1>; status = "disabled"; }; @@ -213,7 +213,7 @@ sdhi2: mmc@11c20000 { <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A08G045_SDHI2_IXRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_SDHI2>; status = "disabled"; }; @@ -230,7 +230,7 @@ eth0: ethernet@11c30000 { <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; clock-names = "axi", "chi", "refclk"; resets = <&cpg R9A08G045_ETH0_RST_HW_N>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_ETHER0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -249,7 +249,7 @@ eth1: ethernet@11c40000 { <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>; clock-names = "axi", "chi", "refclk"; resets = <&cpg R9A08G045_ETH1_RST_HW_N>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_ETHER1>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -275,7 +275,7 @@ wdt0: watchdog@12800800 { <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "wdt", "perrout"; resets = <&cpg R9A08G045_WDT0_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_WDT0>; status = "disabled"; }; }; -- 2.39.2
WARNING: multiple messages have this Message-ID (diff)
From: Claudiu <claudiu.beznea@tuxon.dev> To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, claudiu.beznea@tuxon.dev, Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Subject: [PATCH 16/17] arm64: dts: renesas: r9a08g045: Update #power-domain-cells = <1> Date: Thu, 8 Feb 2024 14:42:59 +0200 [thread overview] Message-ID: <20240208124300.2740313-17-claudiu.beznea.uj@bp.renesas.com> (raw) In-Reply-To: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Update CPG #power-domain-cells = <1> and move all the IPs to be part of the IP specific power domain as the driver has been modified to support multiple power domains. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index dfee878c0f49..11be621aaa82 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -62,7 +62,7 @@ scif0: serial@1004b800 { "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>; clock-names = "fck"; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_SCIF0>; resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>; status = "disabled"; }; @@ -74,7 +74,7 @@ cpg: clock-controller@11010000 { clock-names = "extal"; #clock-cells = <2>; #reset-cells = <1>; - #power-domain-cells = <0>; + #power-domain-cells = <1>; }; sysc: system-controller@11020000 { @@ -99,7 +99,7 @@ pinctrl: pinctrl@11030000 { interrupt-parent = <&irqc>; gpio-ranges = <&pinctrl 0 0 152>; clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_ALWAYS_ON>; resets = <&cpg R9A08G045_GPIO_RSTN>, <&cpg R9A08G045_GPIO_PORT_RESETN>, <&cpg R9A08G045_GPIO_SPARE_RESETN>; @@ -168,7 +168,7 @@ irqc: interrupt-controller@11050000 { clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>, <&cpg CPG_MOD R9A08G045_IA55_PCLK>; clock-names = "clk", "pclk"; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_ALWAYS_ON>; resets = <&cpg R9A08G045_IA55_RESETN>; }; @@ -183,7 +183,7 @@ sdhi0: mmc@11c00000 { <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A08G045_SDHI0_IXRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_SDHI0>; status = "disabled"; }; @@ -198,7 +198,7 @@ sdhi1: mmc@11c10000 { <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A08G045_SDHI1_IXRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_SDHI1>; status = "disabled"; }; @@ -213,7 +213,7 @@ sdhi2: mmc@11c20000 { <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>; clock-names = "core", "clkh", "cd", "aclk"; resets = <&cpg R9A08G045_SDHI2_IXRST>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_SDHI2>; status = "disabled"; }; @@ -230,7 +230,7 @@ eth0: ethernet@11c30000 { <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; clock-names = "axi", "chi", "refclk"; resets = <&cpg R9A08G045_ETH0_RST_HW_N>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_ETHER0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -249,7 +249,7 @@ eth1: ethernet@11c40000 { <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>; clock-names = "axi", "chi", "refclk"; resets = <&cpg R9A08G045_ETH1_RST_HW_N>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_ETHER1>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -275,7 +275,7 @@ wdt0: watchdog@12800800 { <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "wdt", "perrout"; resets = <&cpg R9A08G045_WDT0_PRESETN>; - power-domains = <&cpg>; + power-domains = <&cpg R9A08G045_PD_WDT0>; status = "disabled"; }; }; -- 2.39.2 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-02-08 12:44 UTC|newest] Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-02-08 12:42 [PATCH 00/17] clk: renesas: rzg2l: Add support for power domains Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-08 12:42 ` [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-08 14:30 ` Biju Das 2024-02-08 14:30 ` Biju Das 2024-02-08 15:45 ` claudiu beznea 2024-02-08 15:45 ` claudiu beznea 2024-02-08 16:28 ` Biju Das 2024-02-08 16:28 ` Biju Das 2024-02-08 16:53 ` claudiu beznea 2024-02-08 16:53 ` claudiu beznea 2024-02-08 19:20 ` Biju Das 2024-02-08 19:20 ` Biju Das 2024-02-12 8:02 ` claudiu beznea 2024-02-12 8:02 ` claudiu beznea 2024-02-12 8:59 ` Biju Das 2024-02-12 8:59 ` Biju Das 2024-02-12 10:17 ` claudiu beznea 2024-02-12 10:17 ` claudiu beznea 2024-02-12 10:32 ` Biju Das 2024-02-12 10:32 ` Biju Das 2024-02-12 11:08 ` claudiu beznea 2024-02-12 11:08 ` claudiu beznea 2024-02-16 14:01 ` Geert Uytterhoeven 2024-02-16 14:01 ` Geert Uytterhoeven 2024-02-19 7:36 ` claudiu beznea 2024-02-19 7:36 ` claudiu beznea 2024-02-08 12:42 ` [PATCH 02/17] dt-bindings: clock: r9a07g044-cpg: " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-08 14:39 ` Biju Das 2024-02-08 14:39 ` Biju Das 2024-02-08 15:55 ` claudiu beznea 2024-02-08 15:55 ` claudiu beznea 2024-02-16 14:02 ` Geert Uytterhoeven 2024-02-16 14:02 ` Geert Uytterhoeven 2024-02-08 12:42 ` [PATCH 03/17] dt-bindings: clock: r9a07g054-cpg: " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:02 ` Geert Uytterhoeven 2024-02-16 14:02 ` Geert Uytterhoeven 2024-02-08 12:42 ` [PATCH 04/17] dt-bindings: clock: r9a08g045-cpg: " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:03 ` Geert Uytterhoeven 2024-02-16 14:03 ` Geert Uytterhoeven 2024-02-08 12:42 ` [PATCH 05/17] dt-bindings: clock: r9a09g011-cpg: Add always-on " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:03 ` Geert Uytterhoeven 2024-02-16 14:03 ` Geert Uytterhoeven 2024-02-19 7:39 ` claudiu beznea 2024-02-19 7:39 ` claudiu beznea 2024-02-08 12:42 ` [PATCH 06/17] dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-09 7:56 ` Krzysztof Kozlowski 2024-02-09 7:56 ` Krzysztof Kozlowski 2024-02-09 11:57 ` claudiu beznea 2024-02-09 11:57 ` claudiu beznea 2024-02-16 14:04 ` Geert Uytterhoeven 2024-02-16 14:04 ` Geert Uytterhoeven 2024-02-19 8:18 ` claudiu beznea 2024-02-19 8:18 ` claudiu beznea 2024-02-08 12:42 ` [PATCH 07/17] clk: renesas: rzg2l: Extend power domain support Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:08 ` Geert Uytterhoeven 2024-02-16 14:08 ` Geert Uytterhoeven 2024-02-19 8:24 ` claudiu beznea 2024-02-19 8:24 ` claudiu beznea 2024-02-19 8:48 ` Geert Uytterhoeven 2024-02-19 8:48 ` Geert Uytterhoeven 2024-02-19 9:04 ` claudiu beznea 2024-02-19 9:04 ` claudiu beznea 2024-02-20 19:32 ` Geert Uytterhoeven 2024-02-20 19:32 ` Geert Uytterhoeven 2024-02-21 6:14 ` claudiu beznea 2024-02-21 6:14 ` claudiu beznea 2024-02-08 12:42 ` [PATCH 08/17] clk: renesas: r9a07g043: Add initial support for power domains Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:09 ` Geert Uytterhoeven 2024-02-16 14:09 ` Geert Uytterhoeven 2024-02-19 8:25 ` claudiu beznea 2024-02-19 8:25 ` claudiu beznea 2024-02-08 12:42 ` [PATCH 09/17] clk: renesas: r9a07g044: " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:09 ` Geert Uytterhoeven 2024-02-16 14:09 ` Geert Uytterhoeven 2024-02-08 12:42 ` [PATCH 10/17] clk: renesas: r9a08g045: Add " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:10 ` Geert Uytterhoeven 2024-02-16 14:10 ` Geert Uytterhoeven 2024-02-21 13:35 ` claudiu beznea 2024-02-21 13:35 ` claudiu beznea 2024-02-08 12:42 ` [PATCH 11/17] clk: renesas: r9a09g011: Add initial " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:10 ` Geert Uytterhoeven 2024-02-16 14:10 ` Geert Uytterhoeven 2024-02-08 12:42 ` [PATCH 12/17] arm64: dts: renesas: rzg3s-smarc-som: Guard the ethernet IRQ GPIOs with proper flags Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:17 ` Geert Uytterhoeven 2024-02-16 14:17 ` Geert Uytterhoeven 2024-02-19 8:29 ` claudiu beznea 2024-02-19 8:29 ` claudiu beznea 2024-02-08 12:42 ` [PATCH 13/17] arm64: dts: renesas: r9a07g043: Update #power-domain-cells = <1> Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:11 ` Geert Uytterhoeven 2024-02-16 14:11 ` Geert Uytterhoeven 2024-02-08 12:42 ` [PATCH 14/17] arm64: dts: renesas: r9a07g044: " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:11 ` Geert Uytterhoeven 2024-02-16 14:11 ` Geert Uytterhoeven 2024-02-08 12:42 ` [PATCH 15/17] arm64: dts: renesas: r9a07g054: " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:11 ` Geert Uytterhoeven 2024-02-16 14:11 ` Geert Uytterhoeven 2024-02-08 12:42 ` Claudiu [this message] 2024-02-08 12:42 ` [PATCH 16/17] arm64: dts: renesas: r9a08g045: " Claudiu 2024-02-16 14:12 ` Geert Uytterhoeven 2024-02-16 14:12 ` Geert Uytterhoeven 2024-02-08 12:43 ` [PATCH 17/17] arm64: dts: renesas: r9a09g011: " Claudiu 2024-02-08 12:43 ` Claudiu 2024-02-16 14:12 ` Geert Uytterhoeven 2024-02-16 14:12 ` Geert Uytterhoeven
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