From: claudiu beznea <claudiu.beznea@tuxon.dev> To: Geert Uytterhoeven <geert@linux-m68k.org> Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Subject: Re: [PATCH 07/17] clk: renesas: rzg2l: Extend power domain support Date: Mon, 19 Feb 2024 11:04:36 +0200 [thread overview] Message-ID: <ba089899-3625-43b2-9ba4-f2fb0e8ac03e@tuxon.dev> (raw) In-Reply-To: <CAMuHMdX0HDK2w1N-k_R9ud_CVotRgAd2CjOoHTsWkSE_Rb7zyQ@mail.gmail.com> Hi, Geert, On 19.02.2024 10:48, Geert Uytterhoeven wrote: > Hi Claudiu, > > On Mon, Feb 19, 2024 at 9:24 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote: >> On 16.02.2024 16:08, Geert Uytterhoeven wrote: >>> On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: >>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >>>> >>>> RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra >>>> power when clocks are disabled by activating module standby. This is done >>>> through MSTOP-specific registers that are part of CPG. Each individual >>>> module has one or more bits associated with one MSTOP register (see table >>>> "Registers for Module Standby Mode" from HW manuals). Hardware manual >>>> associates modules' clocks with one or more MSTOP bits. There are 3 mappings >>>> available (identified by researching RZ/G2L, RZ/G3S, RZ/V2L HW manuals): >>>> >>>> case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X}) >>>> case 2: N clocks mapped to 1 MSTOP bit (with N={0, ..., X}) >>>> case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, ..., Y}) >>>> >>>> Case 3 has been currently identified on RZ/V2L for the VCPL4 module. >>>> >>>> To cover all three cases, the individual platform drivers will provide to >>>> clock driver MSTOP register offset and associated bits in this register >>>> as a bitmask and the clock driver will apply this bitmask to proper >>>> MSTOP register. >>>> >>>> Apart from MSTOP support, RZ/G3S can save more power by powering down the >>>> individual IPs (after MSTOP has been set) if proper bits in >>>> CPG_PWRDN_IP{1,2} registers are set. >>>> >>>> The MSTOP and IP power down support were implemented through power >>>> domains. Platform-specific clock drivers will register an array of >>>> type struct rzg2l_cpg_pm_domain_init_data, which will be used to >>>> instantiate properly the power domains. >>>> >>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >>> >>> Thanks for your patch! >>> >>>> --- a/drivers/clk/renesas/rzg2l-cpg.c >>>> +++ b/drivers/clk/renesas/rzg2l-cpg.c >>>> @@ -1559,9 +1556,34 @@ static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv, >>>> return true; >>>> } >> [ ... ] >> >>> >>>> @@ -234,6 +246,54 @@ struct rzg2l_reset { >>>> #define DEF_RST(_id, _off, _bit) \ >>>> DEF_RST_MON(_id, _off, _bit, -1) >>>> >>>> +/** >>>> + * struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure >>>> + * @mstop: MSTOP configuration (MSB = register offset, LSB = bitmask) >>>> + * @pwrdn: PWRDN configuration (MSB = register offset, LSB = register bit) >>>> + */ >>>> +struct rzg2l_cpg_pm_domain_conf { >>>> + u32 mstop; >>>> + u32 pwrdn; >>> >>> Why not >>> >>> u16 mstop_off; >>> u16 mstop_mask; >>> u16 pwrdn_off; >>> u16 pwrdn_mask; >>> >>> so you can drop the MSTOP*() and PWRDN*() macros below? >> >> I did it like this to align with the already existing approach for this >> kind of things available in this driver. I can do it as you proposed. > > The other fields do not align nicely with byte or word boundaries. > > I can see the value of the MSTOP(name, bitmask) and > PWRDN(name, bitmask) macros, but I'd rather get rid of the *_MASK() > and *_OFF() variants. Sure, I'll do proper adjustments in the next version. Thank you, Claudiu Beznea > >> For the rest of your comments on this patch: I agree and will adjust the >> patch in the next version. > > Thanks! > > Gr{oetje,eeting}s, > > Geert > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: claudiu beznea <claudiu.beznea@tuxon.dev> To: Geert Uytterhoeven <geert@linux-m68k.org> Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Subject: Re: [PATCH 07/17] clk: renesas: rzg2l: Extend power domain support Date: Mon, 19 Feb 2024 11:04:36 +0200 [thread overview] Message-ID: <ba089899-3625-43b2-9ba4-f2fb0e8ac03e@tuxon.dev> (raw) In-Reply-To: <CAMuHMdX0HDK2w1N-k_R9ud_CVotRgAd2CjOoHTsWkSE_Rb7zyQ@mail.gmail.com> Hi, Geert, On 19.02.2024 10:48, Geert Uytterhoeven wrote: > Hi Claudiu, > > On Mon, Feb 19, 2024 at 9:24 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote: >> On 16.02.2024 16:08, Geert Uytterhoeven wrote: >>> On Thu, Feb 8, 2024 at 1:44 PM Claudiu <claudiu.beznea@tuxon.dev> wrote: >>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >>>> >>>> RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra >>>> power when clocks are disabled by activating module standby. This is done >>>> through MSTOP-specific registers that are part of CPG. Each individual >>>> module has one or more bits associated with one MSTOP register (see table >>>> "Registers for Module Standby Mode" from HW manuals). Hardware manual >>>> associates modules' clocks with one or more MSTOP bits. There are 3 mappings >>>> available (identified by researching RZ/G2L, RZ/G3S, RZ/V2L HW manuals): >>>> >>>> case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X}) >>>> case 2: N clocks mapped to 1 MSTOP bit (with N={0, ..., X}) >>>> case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, ..., Y}) >>>> >>>> Case 3 has been currently identified on RZ/V2L for the VCPL4 module. >>>> >>>> To cover all three cases, the individual platform drivers will provide to >>>> clock driver MSTOP register offset and associated bits in this register >>>> as a bitmask and the clock driver will apply this bitmask to proper >>>> MSTOP register. >>>> >>>> Apart from MSTOP support, RZ/G3S can save more power by powering down the >>>> individual IPs (after MSTOP has been set) if proper bits in >>>> CPG_PWRDN_IP{1,2} registers are set. >>>> >>>> The MSTOP and IP power down support were implemented through power >>>> domains. Platform-specific clock drivers will register an array of >>>> type struct rzg2l_cpg_pm_domain_init_data, which will be used to >>>> instantiate properly the power domains. >>>> >>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> >>> >>> Thanks for your patch! >>> >>>> --- a/drivers/clk/renesas/rzg2l-cpg.c >>>> +++ b/drivers/clk/renesas/rzg2l-cpg.c >>>> @@ -1559,9 +1556,34 @@ static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv, >>>> return true; >>>> } >> [ ... ] >> >>> >>>> @@ -234,6 +246,54 @@ struct rzg2l_reset { >>>> #define DEF_RST(_id, _off, _bit) \ >>>> DEF_RST_MON(_id, _off, _bit, -1) >>>> >>>> +/** >>>> + * struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure >>>> + * @mstop: MSTOP configuration (MSB = register offset, LSB = bitmask) >>>> + * @pwrdn: PWRDN configuration (MSB = register offset, LSB = register bit) >>>> + */ >>>> +struct rzg2l_cpg_pm_domain_conf { >>>> + u32 mstop; >>>> + u32 pwrdn; >>> >>> Why not >>> >>> u16 mstop_off; >>> u16 mstop_mask; >>> u16 pwrdn_off; >>> u16 pwrdn_mask; >>> >>> so you can drop the MSTOP*() and PWRDN*() macros below? >> >> I did it like this to align with the already existing approach for this >> kind of things available in this driver. I can do it as you proposed. > > The other fields do not align nicely with byte or word boundaries. > > I can see the value of the MSTOP(name, bitmask) and > PWRDN(name, bitmask) macros, but I'd rather get rid of the *_MASK() > and *_OFF() variants. Sure, I'll do proper adjustments in the next version. Thank you, Claudiu Beznea > >> For the rest of your comments on this patch: I agree and will adjust the >> patch in the next version. > > Thanks! > > Gr{oetje,eeting}s, > > Geert >
next prev parent reply other threads:[~2024-02-19 9:05 UTC|newest] Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-02-08 12:42 [PATCH 00/17] clk: renesas: rzg2l: Add support for power domains Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-08 12:42 ` [PATCH 01/17] dt-bindings: clock: r9a07g043-cpg: Add power domain IDs Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-08 14:30 ` Biju Das 2024-02-08 14:30 ` Biju Das 2024-02-08 15:45 ` claudiu beznea 2024-02-08 15:45 ` claudiu beznea 2024-02-08 16:28 ` Biju Das 2024-02-08 16:28 ` Biju Das 2024-02-08 16:53 ` claudiu beznea 2024-02-08 16:53 ` claudiu beznea 2024-02-08 19:20 ` Biju Das 2024-02-08 19:20 ` Biju Das 2024-02-12 8:02 ` claudiu beznea 2024-02-12 8:02 ` claudiu beznea 2024-02-12 8:59 ` Biju Das 2024-02-12 8:59 ` Biju Das 2024-02-12 10:17 ` claudiu beznea 2024-02-12 10:17 ` claudiu beznea 2024-02-12 10:32 ` Biju Das 2024-02-12 10:32 ` Biju Das 2024-02-12 11:08 ` claudiu beznea 2024-02-12 11:08 ` claudiu beznea 2024-02-16 14:01 ` Geert Uytterhoeven 2024-02-16 14:01 ` Geert Uytterhoeven 2024-02-19 7:36 ` claudiu beznea 2024-02-19 7:36 ` claudiu beznea 2024-02-08 12:42 ` [PATCH 02/17] dt-bindings: clock: r9a07g044-cpg: " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-08 14:39 ` Biju Das 2024-02-08 14:39 ` Biju Das 2024-02-08 15:55 ` claudiu beznea 2024-02-08 15:55 ` claudiu beznea 2024-02-16 14:02 ` Geert Uytterhoeven 2024-02-16 14:02 ` Geert Uytterhoeven 2024-02-08 12:42 ` [PATCH 03/17] dt-bindings: clock: r9a07g054-cpg: " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:02 ` Geert Uytterhoeven 2024-02-16 14:02 ` Geert Uytterhoeven 2024-02-08 12:42 ` [PATCH 04/17] dt-bindings: clock: r9a08g045-cpg: " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:03 ` Geert Uytterhoeven 2024-02-16 14:03 ` Geert Uytterhoeven 2024-02-08 12:42 ` [PATCH 05/17] dt-bindings: clock: r9a09g011-cpg: Add always-on " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:03 ` Geert Uytterhoeven 2024-02-16 14:03 ` Geert Uytterhoeven 2024-02-19 7:39 ` claudiu beznea 2024-02-19 7:39 ` claudiu beznea 2024-02-08 12:42 ` [PATCH 06/17] dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-09 7:56 ` Krzysztof Kozlowski 2024-02-09 7:56 ` Krzysztof Kozlowski 2024-02-09 11:57 ` claudiu beznea 2024-02-09 11:57 ` claudiu beznea 2024-02-16 14:04 ` Geert Uytterhoeven 2024-02-16 14:04 ` Geert Uytterhoeven 2024-02-19 8:18 ` claudiu beznea 2024-02-19 8:18 ` claudiu beznea 2024-02-08 12:42 ` [PATCH 07/17] clk: renesas: rzg2l: Extend power domain support Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:08 ` Geert Uytterhoeven 2024-02-16 14:08 ` Geert Uytterhoeven 2024-02-19 8:24 ` claudiu beznea 2024-02-19 8:24 ` claudiu beznea 2024-02-19 8:48 ` Geert Uytterhoeven 2024-02-19 8:48 ` Geert Uytterhoeven 2024-02-19 9:04 ` claudiu beznea [this message] 2024-02-19 9:04 ` claudiu beznea 2024-02-20 19:32 ` Geert Uytterhoeven 2024-02-20 19:32 ` Geert Uytterhoeven 2024-02-21 6:14 ` claudiu beznea 2024-02-21 6:14 ` claudiu beznea 2024-02-08 12:42 ` [PATCH 08/17] clk: renesas: r9a07g043: Add initial support for power domains Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:09 ` Geert Uytterhoeven 2024-02-16 14:09 ` Geert Uytterhoeven 2024-02-19 8:25 ` claudiu beznea 2024-02-19 8:25 ` claudiu beznea 2024-02-08 12:42 ` [PATCH 09/17] clk: renesas: r9a07g044: " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:09 ` Geert Uytterhoeven 2024-02-16 14:09 ` Geert Uytterhoeven 2024-02-08 12:42 ` [PATCH 10/17] clk: renesas: r9a08g045: Add " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:10 ` Geert Uytterhoeven 2024-02-16 14:10 ` Geert Uytterhoeven 2024-02-21 13:35 ` claudiu beznea 2024-02-21 13:35 ` claudiu beznea 2024-02-08 12:42 ` [PATCH 11/17] clk: renesas: r9a09g011: Add initial " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:10 ` Geert Uytterhoeven 2024-02-16 14:10 ` Geert Uytterhoeven 2024-02-08 12:42 ` [PATCH 12/17] arm64: dts: renesas: rzg3s-smarc-som: Guard the ethernet IRQ GPIOs with proper flags Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:17 ` Geert Uytterhoeven 2024-02-16 14:17 ` Geert Uytterhoeven 2024-02-19 8:29 ` claudiu beznea 2024-02-19 8:29 ` claudiu beznea 2024-02-08 12:42 ` [PATCH 13/17] arm64: dts: renesas: r9a07g043: Update #power-domain-cells = <1> Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:11 ` Geert Uytterhoeven 2024-02-16 14:11 ` Geert Uytterhoeven 2024-02-08 12:42 ` [PATCH 14/17] arm64: dts: renesas: r9a07g044: " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:11 ` Geert Uytterhoeven 2024-02-16 14:11 ` Geert Uytterhoeven 2024-02-08 12:42 ` [PATCH 15/17] arm64: dts: renesas: r9a07g054: " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:11 ` Geert Uytterhoeven 2024-02-16 14:11 ` Geert Uytterhoeven 2024-02-08 12:42 ` [PATCH 16/17] arm64: dts: renesas: r9a08g045: " Claudiu 2024-02-08 12:42 ` Claudiu 2024-02-16 14:12 ` Geert Uytterhoeven 2024-02-16 14:12 ` Geert Uytterhoeven 2024-02-08 12:43 ` [PATCH 17/17] arm64: dts: renesas: r9a09g011: " Claudiu 2024-02-08 12:43 ` Claudiu 2024-02-16 14:12 ` Geert Uytterhoeven 2024-02-16 14:12 ` Geert Uytterhoeven
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