Re: [PATCH v9 5/5] iommu/arm-smmu: Add support for qcom,smmu-v2 variant

From: Yisheng Xie <xieyisheng1-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
To: Vivek Gautam
	<vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
	Tomasz Figa <tfiga-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-msm
	<linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>,
	Linux Kernel Mailing List
	<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"list-Y9sIeH5OGRo@public.gmane.org:IOMMU DRIVERS"
	<iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>,
	gaojianbo-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org
Subject: Re: [PATCH v9 5/5] iommu/arm-smmu: Add support for qcom,smmu-v2 variant
Date: Thu, 12 Apr 2018 09:55:35 +0800	[thread overview]
Message-ID: <76065271-c6e6-2ce7-8608-c18b621055ce@huawei.com> (raw)
In-Reply-To: <ff1c730f-0009-58e5-cf4a-45fe9ab93d1e-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>

Hi Vivek,

On 2018/4/11 13:15, Vivek Gautam wrote:
> Hi Yisheng,
> 
> 
> On 4/11/2018 6:52 AM, Yisheng Xie wrote:
>> Hi Tomasz,
>>
>> On 2018/4/10 21:14, Tomasz Figa wrote:
>>> Hi Yisheng,
>>>
>>> Sorry, I think we missed your question here.
>>>
>>> On Wed, Mar 28, 2018 at 3:12 PM Yisheng Xie <xieyisheng1-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> wrote:
>>>
>>>> Hi Vivek,
>>>> On 2018/3/28 12:37, Vivek Gautam wrote:
>>>>> Hi Yisheng
>>>>>
>>>>>
>>>>> On 3/28/2018 6:54 AM, Yisheng Xie wrote:
>>>>>> Hi Vivek,
>>>>>>
>>>>>> On 2018/3/13 16:55, Vivek Gautam wrote:
>>>>>>> +- power-domains:  Specifiers for power domains required to be
>>> powered on for
>>>>>>> +                  the SMMU to operate, as per generic power domain
>>> bindings.
>>>>>>> +
>>>>>> In this patchset, power-domains is not used right? And you just do the
>>> clock gating,
>>>>>> but not power gating, right?
>>>>> We are handling the power-domains too. Please see the example in this
>>> binding doc.
>>>
>>>> I see, but I do not find the point in code of these patchset, do you mean
>>> PMIC(e.g mmcc)
>>>> will gate the power domain of SMMU(e.g. MDSS_GDSC of mmcc) when PMIC
>>> suspend?
>>>
>>>
>>> If respective SoC power domains is registered as a standard genpd PM
>>> domain, then the runtime PM subsystem will take care of power domain
>>> control at runtime suspend and resume.
>>>
>> Get it, thanks for your explain, I should have learned about this.
> 
> Sorry, i missed your subsequent question, and Tomasz has explained it now.

Never mind about that.

> Let me know if you have further questions.

Presently, no other questions. Thanks for your kind help.

Thanks
Yisheng
> 
> regards
> Vivek
>>
>> Thanks
>> Yisheng
>>
>>> Best regards,
>>> Tomasz
>>>
>>> .
>>>
>> -- 
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> 
> 
> .
> 