From: "Bjørn Mork" <bjorn@mork.no>
To: Huang Ying <ying.huang@intel.com>
Cc: huang ying <huang.ying.caritas@gmail.com>,
"Rafael J. Wysocki" <rjw@sisk.pl>,
Zheng Yan <zheng.z.yan@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
linux-pci@vger.kernel.org, linux-usb@vger.kernel.org,
Alan Stern <stern@rowland.harvard.edu>
Subject: Re: bisected regression, v3.5 -> next-20120724: PCI PM causes USB hotplug failure
Date: Thu, 26 Jul 2012 14:04:27 +0200 [thread overview]
Message-ID: <87r4rysp84.fsf@nemi.mork.no> (raw)
In-Reply-To: <87fw8eyecd.fsf@nemi.mork.no> (=?utf-8?Q?=22Bj=C3=B8rn?= Mork"'s message of "Thu, 26 Jul 2012 13:02:58 +0200")
Bjørn Mork <bjorn@mork.no> writes:
> Capabilities: [c8] Power Management version 3
> Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
> Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
>
> Capabilities: [a0] Power Management version 2
> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
> Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
>
That was from the previous captured lspci output. But I assume you
might be interested in the state when the driver fails. The default with
your newest patch is to allow d3cold for the WiFi device but disallow it
for the bridge (PCIe port). Which I guess is the intention based on the
patch description.
This seems to work. The PCIe port ends up in D3:
nemi:/home/bjorn# lspci -vvnns 00:1c.1
00:1c.1 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 2 [8086:2942] (rev 03) (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Bus: primary=00, secondary=03, subordinate=03, sec-latency=0
I/O behind bridge: 00003000-00003fff
Memory behind bridge: f0500000-f05fffff
Prefetchable memory behind bridge: 00000000c0400000-00000000c05fffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
ExtTag- RBE+ FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 128 bytes, MaxReadReq 128 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us
ClockPM- Surprise- LLActRep+ BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+
Slot #1, PowerLimit 6.500W; Interlock- NoCompl-
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
Changed: MRL- PresDet- LinkState+
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
Address: fee0300c Data: 4143
Capabilities: [90] Subsystem: Lenovo Device [17aa:20f3]
Capabilities: [a0] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D3 NoSoftRst- PME-Enable+ DSel=0 DScale=0 PME-
Capabilities: [100 v1] Virtual Channel
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
Arb: Fixed+ WRR32- WRR64- WRR128-
Ctrl: ArbSelect=Fixed
Status: InProgress-
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01
Status: NegoPending- InProgress-
Capabilities: [180 v1] Root Complex Link
Desc: PortNumber=02 ComponentID=02 EltType=Config
Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+
Addr: 00000000fed1c000
Kernel driver in use: pcieport
Attempting to read the WiFi device config at this point is futile:
nemi:/home/bjorn# lspci -vvnns 03:00.0
03:00.0 Network controller [0280]: Intel Corporation Ultimate N WiFi Link 5300 [8086:4236] (rev ff) (prog-if ff)
!!! Unknown header type 7f
Does that work as expected BTW? Would be nice if any attempt to read
config would wake the brigde to allow it, would it not? I have
absolutely no idea whether that's is achievable..
But any attempt to load a driver for the WiFi device should most
definitely wake the bridge. But it does not:
nemi:/home/bjorn# modprobe iwldvm; lspci -vvnns 00:1c.1
00:1c.1 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 2 [8086:2942] (rev 03) (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Bus: primary=00, secondary=03, subordinate=03, sec-latency=0
I/O behind bridge: 00003000-00003fff
Memory behind bridge: f0500000-f05fffff
Prefetchable memory behind bridge: 00000000c0400000-00000000c05fffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
ExtTag- RBE+ FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 128 bytes, MaxReadReq 128 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us
ClockPM- Surprise- LLActRep+ BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+
Slot #1, PowerLimit 6.500W; Interlock- NoCompl-
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
Changed: MRL- PresDet- LinkState+
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit-
Address: fee0300c Data: 4143
Capabilities: [90] Subsystem: Lenovo Device [17aa:20f3]
Capabilities: [a0] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D3 NoSoftRst- PME-Enable+ DSel=0 DScale=0 PME-
Capabilities: [100 v1] Virtual Channel
Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
Arb: Fixed+ WRR32- WRR64- WRR128-
Ctrl: ArbSelect=Fixed
Status: InProgress-
VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-
Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01
Status: NegoPending- InProgress-
Capabilities: [180 v1] Root Complex Link
Desc: PortNumber=02 ComponentID=02 EltType=Config
Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+
Addr: 00000000fed1c000
Kernel driver in use: pcieport
I have tried all 4 combinations of d3cold_allowed for these 2 devices,
but none of them make any difference. The default with your patches is
to disallow it for the PCIe port. One strange issue is that the PCIe
port goes into the same stat even if I set d3cold_allowed to 1:
Capabilities: [a0] Power Management version 2
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D3 NoSoftRst- PME-Enable+ DSel=0 DScale=0 PME-
Should't the status then be "D4" or "D3cold" or whatever lspci will call
it? At least different? The d3cold_allowed setting does not seem to
change anything for this port.
Bjørn
next prev parent reply other threads:[~2012-07-26 12:04 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <Pine.LNX.4.44L0.1207241312050.1164-100000@iolanthe.rowland.org>
[not found] ` <87r4s0opck.fsf@nemi.mork.no>
2012-07-25 4:08 ` bisected regression, v3.5 -> next-20120724: PCI PM causes USB hotplug failure Bjørn Mork
2012-07-25 4:34 ` Huang Ying
2012-07-25 9:58 ` Bjørn Mork
2012-07-25 13:30 ` huang ying
2012-07-25 13:58 ` Bjørn Mork
2012-07-25 18:56 ` Rafael J. Wysocki
2012-07-25 20:02 ` Rafael J. Wysocki
2012-07-25 22:36 ` Bjørn Mork
2012-07-26 2:38 ` Huang Ying
2012-07-26 2:38 ` Huang Ying
2012-07-26 8:54 ` Huang Ying
2012-07-26 10:35 ` Bjørn Mork
2012-07-26 11:02 ` Bjørn Mork
2012-07-26 12:04 ` Bjørn Mork [this message]
2012-07-26 15:03 ` Alan Stern
2012-07-26 16:24 ` Bjørn Mork
2012-07-27 5:35 ` Huang Ying
2012-07-27 9:11 ` Bjørn Mork
2012-07-30 3:15 ` Huang Ying
2012-07-30 8:08 ` Bjørn Mork
2012-07-30 13:31 ` huang ying
2012-07-30 16:57 ` Bjørn Mork
2012-07-31 0:22 ` Huang Ying
2012-07-30 14:19 ` Alan Stern
2012-07-31 0:24 ` Huang Ying
2012-07-31 3:18 ` Huang Ying
2012-07-31 17:07 ` Alan Stern
2012-07-27 15:03 ` Alan Stern
2012-07-27 19:11 ` Rafael J. Wysocki
2012-07-27 19:39 ` Alan Stern
2012-07-27 19:54 ` Rafael J. Wysocki
2012-07-28 16:12 ` Alan Stern
2012-07-28 20:26 ` Rafael J. Wysocki
2012-07-28 21:12 ` Alan Stern
2012-07-29 13:55 ` Rafael J. Wysocki
2012-07-29 14:55 ` Alan Stern
2012-07-29 19:18 ` Rafael J. Wysocki
2012-07-31 20:31 ` Do we need asynchronous pm_runtime_get()? (was: Re: bisected regression ...) Rafael J. Wysocki
2012-07-31 21:05 ` Alan Stern
2012-07-31 21:34 ` Rafael J. Wysocki
2012-07-31 21:49 ` Rafael J. Wysocki
2012-08-01 14:36 ` Alan Stern
2012-08-01 21:24 ` Rafael J. Wysocki
2012-08-02 20:16 ` Alan Stern
2012-08-02 21:26 ` Rafael J. Wysocki
2012-08-03 2:20 ` Alan Stern
2012-08-03 3:37 ` Ming Lei
2012-08-03 14:28 ` Alan Stern
2012-08-04 19:47 ` Rafael J. Wysocki
2012-08-04 20:25 ` Alan Stern
2012-08-04 20:48 ` Rafael J. Wysocki
2012-08-04 20:48 ` Alan Stern
2012-08-04 21:15 ` Rafael J. Wysocki
2012-08-04 22:13 ` Alan Stern
2012-08-05 15:26 ` Rafael J. Wysocki
2012-08-06 13:30 ` Ming Lei
2012-08-06 14:47 ` Alan Stern
2012-08-07 1:35 ` Ming Lei
2012-08-07 11:23 ` Rafael J. Wysocki
2012-08-07 15:14 ` Ming Lei
2012-08-07 15:42 ` Alan Stern
2012-08-07 16:30 ` Ming Lei
2012-08-07 20:57 ` Rafael J. Wysocki
2012-08-07 20:45 ` Rafael J. Wysocki
2012-08-08 2:02 ` Ming Lei
2012-08-08 18:42 ` Alan Stern
2012-08-08 20:16 ` Rafael J. Wysocki
2012-08-09 5:55 ` Ming Lei
2012-08-09 10:46 ` Rafael J. Wysocki
2012-08-09 10:55 ` Ming Lei
2012-08-09 19:41 ` Rafael J. Wysocki
2012-08-10 3:19 ` Ming Lei
2012-08-10 20:29 ` Rafael J. Wysocki
2012-08-08 22:27 ` Rafael J. Wysocki
2012-08-06 15:48 ` Alan Stern
2012-08-06 20:30 ` Rafael J. Wysocki
2012-08-07 12:28 ` Rafael J. Wysocki
2012-08-07 17:15 ` Alan Stern
2012-08-07 21:31 ` Rafael J. Wysocki
2012-08-03 14:05 ` Alan Stern
2012-08-04 20:08 ` Rafael J. Wysocki
2012-08-04 20:42 ` Alan Stern
2012-08-04 20:59 ` Rafael J. Wysocki
2012-08-04 19:35 ` Rafael J. Wysocki
2012-07-29 20:12 ` bisected regression, v3.5 -> next-20120724: PCI PM causes USB hotplug failure Jassi Brar
2012-07-29 21:44 ` Alan Stern
2012-07-25 19:51 ` [PATCH] PCI / PM: Fix messages printed by acpi_pci_set_power_state() Rafael J. Wysocki
2012-07-25 20:02 ` Alan Stern
2012-07-25 20:48 ` [PATCH][update] " Rafael J. Wysocki
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