From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> To: Conor Dooley <conor@kernel.org> Cc: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Heiko Stuebner <heiko@sntech.de>, Conor Dooley <conor.dooley@microchip.com>, Guo Ren <guoren@kernel.org>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@rivosinc.com>, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC Date: Sun, 30 Oct 2022 22:37:01 +0000 [thread overview] Message-ID: <CA+V-a8uKQ8QvYi5qLC9O=QAQN5CxNB7cOTmw4vk+ndB2R8d3nQ@mail.gmail.com> (raw) In-Reply-To: <Y17BWPuEcmY7Bba3@spud> Hi Conor, On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote: > > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Hi All, > > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as > > entry-class social infrastructure gateway control and industrial gateway > > control. > > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK: > > - AX45MP CPU > > - CPG > > - PINCTRL > > Hey, > Looks like you've got a pair of warnings here from dtbs_check. I tested > this on top of 20221028's next, with the three branches below merged in, > hopefully my merges aren't the source of them: > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > Thanks for the review and test. The warnings above are coming from [0] as support for IRQC is missing, once that is added the warnings should go away. > With this sorted, whatever wasn't already is now: > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Thanks for putting up with my messing around re: kconfig symbols and I > am glad that we ended up being able to share the dts across archs in the > end, so thanks to everyone involved in that :) > :-) [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi Cheers, Prabhakar
WARNING: multiple messages have this Message-ID (diff)
From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> To: Conor Dooley <conor@kernel.org> Cc: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Heiko Stuebner <heiko@sntech.de>, Conor Dooley <conor.dooley@microchip.com>, Guo Ren <guoren@kernel.org>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@rivosinc.com>, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC Date: Sun, 30 Oct 2022 22:37:01 +0000 [thread overview] Message-ID: <CA+V-a8uKQ8QvYi5qLC9O=QAQN5CxNB7cOTmw4vk+ndB2R8d3nQ@mail.gmail.com> (raw) In-Reply-To: <Y17BWPuEcmY7Bba3@spud> Hi Conor, On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote: > > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Hi All, > > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as > > entry-class social infrastructure gateway control and industrial gateway > > control. > > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK: > > - AX45MP CPU > > - CPG > > - PINCTRL > > Hey, > Looks like you've got a pair of warnings here from dtbs_check. I tested > this on top of 20221028's next, with the three branches below merged in, > hopefully my merges aren't the source of them: > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property > From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property > From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml > Thanks for the review and test. The warnings above are coming from [0] as support for IRQC is missing, once that is added the warnings should go away. > With this sorted, whatever wasn't already is now: > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Thanks for putting up with my messing around re: kconfig symbols and I > am glad that we ended up being able to share the dts across archs in the > end, so thanks to everyone involved in that :) > :-) [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi Cheers, Prabhakar _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-10-30 22:37 UTC|newest] Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-10-28 16:59 [PATCH v5 0/7] Add support for Renesas RZ/Five SoC Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-28 16:59 ` [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:20 ` Guo Ren 2022-10-29 4:20 ` Guo Ren 2022-10-28 16:59 ` [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:20 ` Guo Ren 2022-10-29 4:20 ` Guo Ren 2022-10-28 16:59 ` [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:18 ` Guo Ren 2022-10-29 4:18 ` Guo Ren 2022-11-08 15:37 ` Geert Uytterhoeven 2022-11-08 15:37 ` Geert Uytterhoeven 2022-10-28 16:59 ` [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:25 ` Guo Ren 2022-10-29 4:25 ` Guo Ren 2022-10-29 19:10 ` Lad, Prabhakar 2022-10-29 19:10 ` Lad, Prabhakar 2022-10-30 0:02 ` Guo Ren 2022-10-30 0:02 ` Guo Ren 2022-10-30 18:16 ` Conor Dooley 2022-10-30 18:16 ` Conor Dooley 2022-10-30 22:27 ` Lad, Prabhakar 2022-10-30 22:27 ` Lad, Prabhakar 2022-10-30 22:39 ` Conor Dooley 2022-10-30 22:39 ` Conor Dooley 2022-10-31 1:11 ` Guo Ren 2022-10-31 1:11 ` Guo Ren 2022-10-31 0:45 ` Guo Ren 2022-10-31 0:45 ` Guo Ren 2022-10-30 22:23 ` Lad, Prabhakar 2022-10-30 22:23 ` Lad, Prabhakar 2022-11-08 15:43 ` Geert Uytterhoeven 2022-11-08 15:43 ` Geert Uytterhoeven 2022-10-28 16:59 ` [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:26 ` Guo Ren 2022-10-29 4:26 ` Guo Ren 2022-10-29 19:14 ` Lad, Prabhakar 2022-10-29 19:14 ` Lad, Prabhakar 2022-11-08 15:44 ` Geert Uytterhoeven 2022-11-08 15:44 ` Geert Uytterhoeven 2022-10-28 16:59 ` [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:27 ` Guo Ren 2022-10-29 4:27 ` Guo Ren 2022-10-28 16:59 ` [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:28 ` Guo Ren 2022-10-29 4:28 ` Guo Ren 2022-11-08 15:51 ` Geert Uytterhoeven 2022-11-08 15:51 ` Geert Uytterhoeven 2022-11-08 16:06 ` Lad, Prabhakar 2022-11-08 16:06 ` Lad, Prabhakar 2022-11-08 16:12 ` Geert Uytterhoeven 2022-11-08 16:12 ` Geert Uytterhoeven 2022-11-08 17:22 ` Lad, Prabhakar 2022-11-08 17:22 ` Lad, Prabhakar 2022-11-08 19:19 ` Geert Uytterhoeven 2022-11-08 19:19 ` Geert Uytterhoeven 2022-11-08 22:01 ` Lad, Prabhakar 2022-11-08 22:01 ` Lad, Prabhakar 2022-11-09 7:46 ` Geert Uytterhoeven 2022-11-09 7:46 ` Geert Uytterhoeven 2022-11-09 9:16 ` Lad, Prabhakar 2022-11-09 9:16 ` Lad, Prabhakar 2022-10-30 18:24 ` [PATCH v5 0/7] Add support for " Conor Dooley 2022-10-30 18:24 ` Conor Dooley 2022-10-30 22:37 ` Lad, Prabhakar [this message] 2022-10-30 22:37 ` Lad, Prabhakar 2022-10-30 22:45 ` Conor Dooley 2022-10-30 22:45 ` Conor Dooley 2022-10-30 23:01 ` Lad, Prabhakar 2022-10-30 23:01 ` Lad, Prabhakar 2022-11-07 18:03 ` Lad, Prabhakar 2022-11-07 18:03 ` Lad, Prabhakar 2022-11-07 18:17 ` Conor Dooley 2022-11-07 18:17 ` Conor Dooley 2022-11-08 16:02 ` Geert Uytterhoeven 2022-11-08 16:02 ` Geert Uytterhoeven 2022-11-08 19:29 ` Conor Dooley 2022-11-08 19:29 ` Conor Dooley 2022-11-09 19:55 ` Palmer Dabbelt 2022-11-09 19:55 ` Palmer Dabbelt 2022-11-09 21:21 ` Conor Dooley 2022-11-09 21:21 ` Conor Dooley 2022-11-10 16:17 ` Geert Uytterhoeven 2022-11-10 16:17 ` Geert Uytterhoeven
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