From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> To: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Magnus Damm <magnus.damm@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Heiko Stuebner <heiko@sntech.de>, Conor Dooley <conor.dooley@microchip.com>, Guo Ren <guoren@kernel.org>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@rivosinc.com>, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC Date: Tue, 8 Nov 2022 17:22:47 +0000 [thread overview] Message-ID: <CA+V-a8vCGDHL1SUTEnD-WvoUGKSVL=xzDeQxy77=1vFJdk+fYg@mail.gmail.com> (raw) In-Reply-To: <CAMuHMdWTJf24XR+KR8yVJOnfpgs-PkUf9b8B=PX9Dd4mfawD5Q@mail.gmail.com> Hi Geert, On Tue, Nov 8, 2022 at 4:12 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Tue, Nov 8, 2022 at 5:07 PM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > On Tue, Nov 8, 2022 at 3:52 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > > On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > Enable Renesas RZ/Five SoC config in defconfig. It allows the default > > > > upstream kernel to boot on RZ/Five SMARC EVK board. > > > > > > > > Alongside enable SERIAL_SH_SCI config so that the serial driver used by > > > > RZ/Five SoC is built-in. > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > > > --- > > > > v4 -> v5 > > > > * No change > > > > > > > > v3 -> v4 > > > > * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB > > > > tags with this change) > > > > * Used riscv instead of RISC-V in subject line > > > > > > Thanks for the update! > > > > > > > --- a/arch/riscv/configs/defconfig > > > > +++ b/arch/riscv/configs/defconfig > > > > @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y > > > > CONFIG_SOC_SIFIVE=y > > > > CONFIG_SOC_STARFIVE=y > > > > CONFIG_SOC_VIRT=y > > > > +CONFIG_ARCH_RENESAS=y > > > > +CONFIG_ARCH_R9A07G043=y > > > > > > You forgot to refresh after moving ARCH_RENESAS in v5 of "riscv: > > > Kconfig.socs: Add ARCH_RENESAS kconfig option", and after relying on > > > ARCH_R9A07G043 in drivers/soc/renesas/Kconfig. > > > > > Sorry I missed your point here, could you please elaborate. > > I mean that the options have moved, so you should update > your patch like this: > Ouch got that. > --- a/arch/riscv/configs/defconfig > +++ b/arch/riscv/configs/defconfig > @@ -26,11 +26,10 @@ CONFIG_EXPERT=y > # CONFIG_SYSFS_SYSCALL is not set > CONFIG_PROFILING=y > CONFIG_SOC_MICROCHIP_POLARFIRE=y > +CONFIG_ARCH_RENESAS=y > CONFIG_SOC_SIFIVE=y > CONFIG_SOC_STARFIVE=y > CONFIG_SOC_VIRT=y > -CONFIG_ARCH_RENESAS=y > -CONFIG_ARCH_R9A07G043=y > CONFIG_SMP=y > CONFIG_HOTPLUG_CPU=y > CONFIG_PM=y > @@ -163,6 +159,7 @@ CONFIG_MAILBOX=y > CONFIG_RPMSG_CHAR=y > CONFIG_RPMSG_CTRL=y > CONFIG_RPMSG_VIRTIO=y > +CONFIG_ARCH_R9A07G043=y > CONFIG_EXT4_FS=y > CONFIG_EXT4_FS_POSIX_ACL=y > CONFIG_EXT4_FS_SECURITY=y > > > > > CONFIG_SMP=y > > > > CONFIG_HOTPLUG_CPU=y > > > > CONFIG_PM=y > > > > > > PM and GPIOLIB are auto-selected by ARCH_R9A07G043 (through ARCH_RZG2L) > > > resp. SOC_RENESAS, so they can be dropped. But it's better to do this > > > after the release of v6.2-rc1, when all pieces have fallen together. > > > > > Are you suggesting dropping it from defconfig? > > Yes, but not right now, as that would make it depend on my > renesas-drivers-for-v6.2 branch to keep them enabled. > I was wondering if that's required by other platforms though. CONFIG_PM was added for VIRT machine and GPIOLIB for HiFive. Cheers, Prabhakar
WARNING: multiple messages have this Message-ID (diff)
From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> To: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Magnus Damm <magnus.damm@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Heiko Stuebner <heiko@sntech.de>, Conor Dooley <conor.dooley@microchip.com>, Guo Ren <guoren@kernel.org>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@rivosinc.com>, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: Re: [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC Date: Tue, 8 Nov 2022 17:22:47 +0000 [thread overview] Message-ID: <CA+V-a8vCGDHL1SUTEnD-WvoUGKSVL=xzDeQxy77=1vFJdk+fYg@mail.gmail.com> (raw) In-Reply-To: <CAMuHMdWTJf24XR+KR8yVJOnfpgs-PkUf9b8B=PX9Dd4mfawD5Q@mail.gmail.com> Hi Geert, On Tue, Nov 8, 2022 at 4:12 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Tue, Nov 8, 2022 at 5:07 PM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > On Tue, Nov 8, 2022 at 3:52 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > > On Fri, Oct 28, 2022 at 6:59 PM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > Enable Renesas RZ/Five SoC config in defconfig. It allows the default > > > > upstream kernel to boot on RZ/Five SMARC EVK board. > > > > > > > > Alongside enable SERIAL_SH_SCI config so that the serial driver used by > > > > RZ/Five SoC is built-in. > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > > > --- > > > > v4 -> v5 > > > > * No change > > > > > > > > v3 -> v4 > > > > * Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB > > > > tags with this change) > > > > * Used riscv instead of RISC-V in subject line > > > > > > Thanks for the update! > > > > > > > --- a/arch/riscv/configs/defconfig > > > > +++ b/arch/riscv/configs/defconfig > > > > @@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y > > > > CONFIG_SOC_SIFIVE=y > > > > CONFIG_SOC_STARFIVE=y > > > > CONFIG_SOC_VIRT=y > > > > +CONFIG_ARCH_RENESAS=y > > > > +CONFIG_ARCH_R9A07G043=y > > > > > > You forgot to refresh after moving ARCH_RENESAS in v5 of "riscv: > > > Kconfig.socs: Add ARCH_RENESAS kconfig option", and after relying on > > > ARCH_R9A07G043 in drivers/soc/renesas/Kconfig. > > > > > Sorry I missed your point here, could you please elaborate. > > I mean that the options have moved, so you should update > your patch like this: > Ouch got that. > --- a/arch/riscv/configs/defconfig > +++ b/arch/riscv/configs/defconfig > @@ -26,11 +26,10 @@ CONFIG_EXPERT=y > # CONFIG_SYSFS_SYSCALL is not set > CONFIG_PROFILING=y > CONFIG_SOC_MICROCHIP_POLARFIRE=y > +CONFIG_ARCH_RENESAS=y > CONFIG_SOC_SIFIVE=y > CONFIG_SOC_STARFIVE=y > CONFIG_SOC_VIRT=y > -CONFIG_ARCH_RENESAS=y > -CONFIG_ARCH_R9A07G043=y > CONFIG_SMP=y > CONFIG_HOTPLUG_CPU=y > CONFIG_PM=y > @@ -163,6 +159,7 @@ CONFIG_MAILBOX=y > CONFIG_RPMSG_CHAR=y > CONFIG_RPMSG_CTRL=y > CONFIG_RPMSG_VIRTIO=y > +CONFIG_ARCH_R9A07G043=y > CONFIG_EXT4_FS=y > CONFIG_EXT4_FS_POSIX_ACL=y > CONFIG_EXT4_FS_SECURITY=y > > > > > CONFIG_SMP=y > > > > CONFIG_HOTPLUG_CPU=y > > > > CONFIG_PM=y > > > > > > PM and GPIOLIB are auto-selected by ARCH_R9A07G043 (through ARCH_RZG2L) > > > resp. SOC_RENESAS, so they can be dropped. But it's better to do this > > > after the release of v6.2-rc1, when all pieces have fallen together. > > > > > Are you suggesting dropping it from defconfig? > > Yes, but not right now, as that would make it depend on my > renesas-drivers-for-v6.2 branch to keep them enabled. > I was wondering if that's required by other platforms though. CONFIG_PM was added for VIRT machine and GPIOLIB for HiFive. Cheers, Prabhakar _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-11-08 17:23 UTC|newest] Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-10-28 16:59 [PATCH v5 0/7] Add support for Renesas RZ/Five SoC Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-28 16:59 ` [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:20 ` Guo Ren 2022-10-29 4:20 ` Guo Ren 2022-10-28 16:59 ` [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:20 ` Guo Ren 2022-10-29 4:20 ` Guo Ren 2022-10-28 16:59 ` [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:18 ` Guo Ren 2022-10-29 4:18 ` Guo Ren 2022-11-08 15:37 ` Geert Uytterhoeven 2022-11-08 15:37 ` Geert Uytterhoeven 2022-10-28 16:59 ` [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:25 ` Guo Ren 2022-10-29 4:25 ` Guo Ren 2022-10-29 19:10 ` Lad, Prabhakar 2022-10-29 19:10 ` Lad, Prabhakar 2022-10-30 0:02 ` Guo Ren 2022-10-30 0:02 ` Guo Ren 2022-10-30 18:16 ` Conor Dooley 2022-10-30 18:16 ` Conor Dooley 2022-10-30 22:27 ` Lad, Prabhakar 2022-10-30 22:27 ` Lad, Prabhakar 2022-10-30 22:39 ` Conor Dooley 2022-10-30 22:39 ` Conor Dooley 2022-10-31 1:11 ` Guo Ren 2022-10-31 1:11 ` Guo Ren 2022-10-31 0:45 ` Guo Ren 2022-10-31 0:45 ` Guo Ren 2022-10-30 22:23 ` Lad, Prabhakar 2022-10-30 22:23 ` Lad, Prabhakar 2022-11-08 15:43 ` Geert Uytterhoeven 2022-11-08 15:43 ` Geert Uytterhoeven 2022-10-28 16:59 ` [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:26 ` Guo Ren 2022-10-29 4:26 ` Guo Ren 2022-10-29 19:14 ` Lad, Prabhakar 2022-10-29 19:14 ` Lad, Prabhakar 2022-11-08 15:44 ` Geert Uytterhoeven 2022-11-08 15:44 ` Geert Uytterhoeven 2022-10-28 16:59 ` [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:27 ` Guo Ren 2022-10-29 4:27 ` Guo Ren 2022-10-28 16:59 ` [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:28 ` Guo Ren 2022-10-29 4:28 ` Guo Ren 2022-11-08 15:51 ` Geert Uytterhoeven 2022-11-08 15:51 ` Geert Uytterhoeven 2022-11-08 16:06 ` Lad, Prabhakar 2022-11-08 16:06 ` Lad, Prabhakar 2022-11-08 16:12 ` Geert Uytterhoeven 2022-11-08 16:12 ` Geert Uytterhoeven 2022-11-08 17:22 ` Lad, Prabhakar [this message] 2022-11-08 17:22 ` Lad, Prabhakar 2022-11-08 19:19 ` Geert Uytterhoeven 2022-11-08 19:19 ` Geert Uytterhoeven 2022-11-08 22:01 ` Lad, Prabhakar 2022-11-08 22:01 ` Lad, Prabhakar 2022-11-09 7:46 ` Geert Uytterhoeven 2022-11-09 7:46 ` Geert Uytterhoeven 2022-11-09 9:16 ` Lad, Prabhakar 2022-11-09 9:16 ` Lad, Prabhakar 2022-10-30 18:24 ` [PATCH v5 0/7] Add support for " Conor Dooley 2022-10-30 18:24 ` Conor Dooley 2022-10-30 22:37 ` Lad, Prabhakar 2022-10-30 22:37 ` Lad, Prabhakar 2022-10-30 22:45 ` Conor Dooley 2022-10-30 22:45 ` Conor Dooley 2022-10-30 23:01 ` Lad, Prabhakar 2022-10-30 23:01 ` Lad, Prabhakar 2022-11-07 18:03 ` Lad, Prabhakar 2022-11-07 18:03 ` Lad, Prabhakar 2022-11-07 18:17 ` Conor Dooley 2022-11-07 18:17 ` Conor Dooley 2022-11-08 16:02 ` Geert Uytterhoeven 2022-11-08 16:02 ` Geert Uytterhoeven 2022-11-08 19:29 ` Conor Dooley 2022-11-08 19:29 ` Conor Dooley 2022-11-09 19:55 ` Palmer Dabbelt 2022-11-09 19:55 ` Palmer Dabbelt 2022-11-09 21:21 ` Conor Dooley 2022-11-09 21:21 ` Conor Dooley 2022-11-10 16:17 ` Geert Uytterhoeven 2022-11-10 16:17 ` Geert Uytterhoeven
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