From: Guo Ren <guoren@kernel.org> To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> Cc: Conor Dooley <conor@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Heiko Stuebner <heiko@sntech.de>, Conor Dooley <conor.dooley@microchip.com>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@rivosinc.com>, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Date: Mon, 31 Oct 2022 09:11:42 +0800 [thread overview] Message-ID: <CAJF2gTRrLOxZt0qhcpC9_fx4bFc1Rj9TDyQVBXdKbwboh-ZGyQ@mail.gmail.com> (raw) In-Reply-To: <CA+V-a8vCNx-bqjeOa13LewaEJOGW-0ypqJTvZo7om6XcM4T7UA@mail.gmail.com> On Mon, Oct 31, 2022 at 6:27 AM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > Hi Conor, > > On Sun, Oct 30, 2022 at 6:16 PM Conor Dooley <conor@kernel.org> wrote: > > > > On Sun, Oct 30, 2022 at 08:02:10AM +0800, Guo Ren wrote: > > > On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar > > > <prabhakar.csengg@gmail.com> wrote: > > > > > > > > Hi Guo, > > > > > > > > Thank you for the review. > > > > > > > > On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote: > > > > > > > > > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > > > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > > > > > > Single). > > > > > > > > > > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we > > > > > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's. > > > > > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks. > > > > > > > > > > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which > > > > > > can be used to boot via initramfs on RZ/Five SMARC EVK: > > > > > > - AX45MP CPU > > > > > > - PLIC > > > > > > > > > > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi > > > > > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > --- > > > > > > v4 -> v5 > > > > > > * Fixed riscv,ndev value (should be 511) > > > > > > * Reworked completely (sort of new patch) > > > > > > > > > > > > v3 -> v4 > > > > > > * No change > > > > > > > > > > > > v2 -> v3 > > > > > > * Fixed clock entry for CPU core > > > > > > * Fixed timebase frequency to 12MHz > > > > > > * Fixed sorting of the nodes > > > > > > * Included RB tags > > > > > > > > > > > > v1 -> v2 > > > > > > * Dropped including makefile change > > > > > > * Updated ndev count > > > > > > --- > > > > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++ > > > > > > 1 file changed, 57 insertions(+) > > > > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > > > > > > > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > > > new file mode 100644 > > > > > > index 000000000000..50134be548f5 > > > > > > --- /dev/null > > > > > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > > > @@ -0,0 +1,57 @@ > > > > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > > > +/* > > > > > > + * Device Tree Source for the RZ/Five SoC > > > > > > + * > > > > > > + * Copyright (C) 2022 Renesas Electronics Corp. > > > > > > + */ > > > > > > + > > > > > > +#include <dt-bindings/interrupt-controller/irq.h> > > > > > > + > > > > > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) > > > > > > + > > > > > > +#include <arm64/renesas/r9a07g043.dtsi> > > > > > The initial patch shouldn't be broken. Combine them together with the > > > > > minimal components and add others late. Don't separate the DTS files. > > > > > > > > > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is > > > > shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two > > > > more patches [1] which are required and are currently queued up in the > > > > Renesas tree for v6.2 (Ive mentioned the dependencies in the cover > > > > letter). > > > > > > You could just move the below part to the second dtsi patch. Then > > > compile won't be broken. > > > > > > clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; > > > power-domains = <&cpg>; > > > resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; > > > > The makefile for this directory is not added until the next patch right? > > The compile shouldn't be broken here since it therefore cannot be > > compiled? > > > These nodes are already present in the kernel [0] so the makefile > change in the next patch if made here still won't break the > compilation alone of SoC DTSI (included in dts). Oh... Sorry, I screwed up. The arch/arm64/boot/dts/renesas/r9a07g043.dtsi is not belonged to the patch series. > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=next-20221028#n563 > > Cheers, > Prabhakar -- Best Regards Guo Ren
WARNING: multiple messages have this Message-ID (diff)
From: Guo Ren <guoren@kernel.org> To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com> Cc: Conor Dooley <conor@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Geert Uytterhoeven <geert+renesas@glider.be>, Magnus Damm <magnus.damm@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Heiko Stuebner <heiko@sntech.de>, Conor Dooley <conor.dooley@microchip.com>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@rivosinc.com>, Heinrich Schuchardt <heinrich.schuchardt@canonical.com>, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das <biju.das.jz@bp.renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: Re: [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Date: Mon, 31 Oct 2022 09:11:42 +0800 [thread overview] Message-ID: <CAJF2gTRrLOxZt0qhcpC9_fx4bFc1Rj9TDyQVBXdKbwboh-ZGyQ@mail.gmail.com> (raw) In-Reply-To: <CA+V-a8vCNx-bqjeOa13LewaEJOGW-0ypqJTvZo7om6XcM4T7UA@mail.gmail.com> On Mon, Oct 31, 2022 at 6:27 AM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > > Hi Conor, > > On Sun, Oct 30, 2022 at 6:16 PM Conor Dooley <conor@kernel.org> wrote: > > > > On Sun, Oct 30, 2022 at 08:02:10AM +0800, Guo Ren wrote: > > > On Sun, Oct 30, 2022 at 3:11 AM Lad, Prabhakar > > > <prabhakar.csengg@gmail.com> wrote: > > > > > > > > Hi Guo, > > > > > > > > Thank you for the review. > > > > > > > > On Sat, Oct 29, 2022 at 5:25 AM Guo Ren <guoren@kernel.org> wrote: > > > > > > > > > > On Sat, Oct 29, 2022 at 12:59 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > > > > > > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > > > > > > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP > > > > > > Single). > > > > > > > > > > > > RZ/Five SoC is almost identical to RZ/G2UL Type-1 SoC (ARM64) hence we > > > > > > will be reusing r9a07g043.dtsi [0] as a base DTSI for both the SoC's. > > > > > > r9a07g043f.dtsi includes RZ/Five SoC specific blocks. > > > > > > > > > > > > Below are the RZ/Five SoC specific blocks added in the initial DTSI which > > > > > > can be used to boot via initramfs on RZ/Five SMARC EVK: > > > > > > - AX45MP CPU > > > > > > - PLIC > > > > > > > > > > > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi > > > > > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > --- > > > > > > v4 -> v5 > > > > > > * Fixed riscv,ndev value (should be 511) > > > > > > * Reworked completely (sort of new patch) > > > > > > > > > > > > v3 -> v4 > > > > > > * No change > > > > > > > > > > > > v2 -> v3 > > > > > > * Fixed clock entry for CPU core > > > > > > * Fixed timebase frequency to 12MHz > > > > > > * Fixed sorting of the nodes > > > > > > * Included RB tags > > > > > > > > > > > > v1 -> v2 > > > > > > * Dropped including makefile change > > > > > > * Updated ndev count > > > > > > --- > > > > > > arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 57 +++++++++++++++++++++ > > > > > > 1 file changed, 57 insertions(+) > > > > > > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > > > > > > > > > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > > > new file mode 100644 > > > > > > index 000000000000..50134be548f5 > > > > > > --- /dev/null > > > > > > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi > > > > > > @@ -0,0 +1,57 @@ > > > > > > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > > > > +/* > > > > > > + * Device Tree Source for the RZ/Five SoC > > > > > > + * > > > > > > + * Copyright (C) 2022 Renesas Electronics Corp. > > > > > > + */ > > > > > > + > > > > > > +#include <dt-bindings/interrupt-controller/irq.h> > > > > > > + > > > > > > +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) > > > > > > + > > > > > > +#include <arm64/renesas/r9a07g043.dtsi> > > > > > The initial patch shouldn't be broken. Combine them together with the > > > > > minimal components and add others late. Don't separate the DTS files. > > > > > > > > > r9a07g043.dtsi [0] already exists in the kernel. r9a07g043.dtsi is > > > > shared with the RZ/G2UL SoC (ARM64) and the RZ/Five SoC. There are two > > > > more patches [1] which are required and are currently queued up in the > > > > Renesas tree for v6.2 (Ive mentioned the dependencies in the cover > > > > letter). > > > > > > You could just move the below part to the second dtsi patch. Then > > > compile won't be broken. > > > > > > clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; > > > power-domains = <&cpg>; > > > resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; > > > > The makefile for this directory is not added until the next patch right? > > The compile shouldn't be broken here since it therefore cannot be > > compiled? > > > These nodes are already present in the kernel [0] so the makefile > change in the next patch if made here still won't break the > compilation alone of SoC DTSI (included in dts). Oh... Sorry, I screwed up. The arch/arm64/boot/dts/renesas/r9a07g043.dtsi is not belonged to the patch series. > > [0] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r9a07g043.dtsi?h=next-20221028#n563 > > Cheers, > Prabhakar -- Best Regards Guo Ren _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-10-31 1:12 UTC|newest] Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-10-28 16:59 [PATCH v5 0/7] Add support for Renesas RZ/Five SoC Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-28 16:59 ` [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:20 ` Guo Ren 2022-10-29 4:20 ` Guo Ren 2022-10-28 16:59 ` [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:20 ` Guo Ren 2022-10-29 4:20 ` Guo Ren 2022-10-28 16:59 ` [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:18 ` Guo Ren 2022-10-29 4:18 ` Guo Ren 2022-11-08 15:37 ` Geert Uytterhoeven 2022-11-08 15:37 ` Geert Uytterhoeven 2022-10-28 16:59 ` [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:25 ` Guo Ren 2022-10-29 4:25 ` Guo Ren 2022-10-29 19:10 ` Lad, Prabhakar 2022-10-29 19:10 ` Lad, Prabhakar 2022-10-30 0:02 ` Guo Ren 2022-10-30 0:02 ` Guo Ren 2022-10-30 18:16 ` Conor Dooley 2022-10-30 18:16 ` Conor Dooley 2022-10-30 22:27 ` Lad, Prabhakar 2022-10-30 22:27 ` Lad, Prabhakar 2022-10-30 22:39 ` Conor Dooley 2022-10-30 22:39 ` Conor Dooley 2022-10-31 1:11 ` Guo Ren [this message] 2022-10-31 1:11 ` Guo Ren 2022-10-31 0:45 ` Guo Ren 2022-10-31 0:45 ` Guo Ren 2022-10-30 22:23 ` Lad, Prabhakar 2022-10-30 22:23 ` Lad, Prabhakar 2022-11-08 15:43 ` Geert Uytterhoeven 2022-11-08 15:43 ` Geert Uytterhoeven 2022-10-28 16:59 ` [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:26 ` Guo Ren 2022-10-29 4:26 ` Guo Ren 2022-10-29 19:14 ` Lad, Prabhakar 2022-10-29 19:14 ` Lad, Prabhakar 2022-11-08 15:44 ` Geert Uytterhoeven 2022-11-08 15:44 ` Geert Uytterhoeven 2022-10-28 16:59 ` [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:27 ` Guo Ren 2022-10-29 4:27 ` Guo Ren 2022-10-28 16:59 ` [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC Prabhakar 2022-10-28 16:59 ` Prabhakar 2022-10-29 4:28 ` Guo Ren 2022-10-29 4:28 ` Guo Ren 2022-11-08 15:51 ` Geert Uytterhoeven 2022-11-08 15:51 ` Geert Uytterhoeven 2022-11-08 16:06 ` Lad, Prabhakar 2022-11-08 16:06 ` Lad, Prabhakar 2022-11-08 16:12 ` Geert Uytterhoeven 2022-11-08 16:12 ` Geert Uytterhoeven 2022-11-08 17:22 ` Lad, Prabhakar 2022-11-08 17:22 ` Lad, Prabhakar 2022-11-08 19:19 ` Geert Uytterhoeven 2022-11-08 19:19 ` Geert Uytterhoeven 2022-11-08 22:01 ` Lad, Prabhakar 2022-11-08 22:01 ` Lad, Prabhakar 2022-11-09 7:46 ` Geert Uytterhoeven 2022-11-09 7:46 ` Geert Uytterhoeven 2022-11-09 9:16 ` Lad, Prabhakar 2022-11-09 9:16 ` Lad, Prabhakar 2022-10-30 18:24 ` [PATCH v5 0/7] Add support for " Conor Dooley 2022-10-30 18:24 ` Conor Dooley 2022-10-30 22:37 ` Lad, Prabhakar 2022-10-30 22:37 ` Lad, Prabhakar 2022-10-30 22:45 ` Conor Dooley 2022-10-30 22:45 ` Conor Dooley 2022-10-30 23:01 ` Lad, Prabhakar 2022-10-30 23:01 ` Lad, Prabhakar 2022-11-07 18:03 ` Lad, Prabhakar 2022-11-07 18:03 ` Lad, Prabhakar 2022-11-07 18:17 ` Conor Dooley 2022-11-07 18:17 ` Conor Dooley 2022-11-08 16:02 ` Geert Uytterhoeven 2022-11-08 16:02 ` Geert Uytterhoeven 2022-11-08 19:29 ` Conor Dooley 2022-11-08 19:29 ` Conor Dooley 2022-11-09 19:55 ` Palmer Dabbelt 2022-11-09 19:55 ` Palmer Dabbelt 2022-11-09 21:21 ` Conor Dooley 2022-11-09 21:21 ` Conor Dooley 2022-11-10 16:17 ` Geert Uytterhoeven 2022-11-10 16:17 ` Geert Uytterhoeven
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