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From: Ley Foon Tan <lftan.linux@gmail.com>
To: Greentime Hu <greentime.hu@sifive.com>
Cc: linux-riscv@lists.infradead.org,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	aou@eecs.berkeley.edu, Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	vincent.chen@sifive.com
Subject: Re: [RFC PATCH v8 11/21] riscv: Add sigcontext save/restore for vector
Date: Thu, 30 Sep 2021 10:37:39 +0800	[thread overview]
Message-ID: <CAFiDJ5_Lp8ejFiNpZw=YvneyEFRj-PD9667Jv_hHy_-7xGf+FQ@mail.gmail.com> (raw)
In-Reply-To: <82fe07af09d223b33c8d4b8986939bcc0d7180a1.1631121222.git.greentime.hu@sifive.com>

On Thu, Sep 9, 2021 at 1:49 AM Greentime Hu <greentime.hu@sifive.com> wrote:
>
> This patch adds sigcontext save/restore for vector. The vector registers
> will be saved in datap pointer. The datap pointer will be allocated
> dynamically when the task needs in kernel space. The datap pointer will
> be set right after the __riscv_v_state data structure to save all the
> vector registers in the signal handler stack.
>
> Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> ---
>  arch/riscv/include/uapi/asm/sigcontext.h |  24 ++++
>  arch/riscv/kernel/asm-offsets.c          |   2 +
>  arch/riscv/kernel/setup.c                |   4 +
>  arch/riscv/kernel/signal.c               | 164 ++++++++++++++++++++++-
>  4 files changed, 190 insertions(+), 4 deletions(-)
>

[....]


> +
> +static size_t cal_rt_frame_size(void)
> +{
> +       struct rt_sigframe __user *frame;
> +       static size_t frame_size;
> +       size_t total_context_size = 0;
> +       size_t sc_reserved_size = sizeof(frame->uc.uc_mcontext.__reserved);
> +
> +       if (frame_size)
> +               goto done;
> +
> +       frame_size = sizeof(*frame);
> +
> +       if (has_vector)
> +               total_context_size += rvv_sc_size;
> +       /* Preserved a __riscv_ctx_hdr for END signal context header. */
> +       total_context_size += sizeof(struct __riscv_ctx_hdr);
> +
> +       if (total_context_size > sc_reserved_size)
> +               frame_size += (total_context_size - sc_reserved_size);
> +
> +done:
> +       return round_up(frame_size, 16);

Hi Greentime,

frame_size is static variable here, so it will preserve the value for
the next calling to cal_rt_frame_size().

I think we need update frame_size before return, example:

frame_size =  round_up(frame_size, 16);
return frame_size;


Regards
Ley Foon

WARNING: multiple messages have this Message-ID (diff)
From: Ley Foon Tan <lftan.linux@gmail.com>
To: Greentime Hu <greentime.hu@sifive.com>
Cc: linux-riscv@lists.infradead.org,
	 Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	aou@eecs.berkeley.edu, Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	vincent.chen@sifive.com
Subject: Re: [RFC PATCH v8 11/21] riscv: Add sigcontext save/restore for vector
Date: Thu, 30 Sep 2021 10:37:39 +0800	[thread overview]
Message-ID: <CAFiDJ5_Lp8ejFiNpZw=YvneyEFRj-PD9667Jv_hHy_-7xGf+FQ@mail.gmail.com> (raw)
In-Reply-To: <82fe07af09d223b33c8d4b8986939bcc0d7180a1.1631121222.git.greentime.hu@sifive.com>

On Thu, Sep 9, 2021 at 1:49 AM Greentime Hu <greentime.hu@sifive.com> wrote:
>
> This patch adds sigcontext save/restore for vector. The vector registers
> will be saved in datap pointer. The datap pointer will be allocated
> dynamically when the task needs in kernel space. The datap pointer will
> be set right after the __riscv_v_state data structure to save all the
> vector registers in the signal handler stack.
>
> Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> ---
>  arch/riscv/include/uapi/asm/sigcontext.h |  24 ++++
>  arch/riscv/kernel/asm-offsets.c          |   2 +
>  arch/riscv/kernel/setup.c                |   4 +
>  arch/riscv/kernel/signal.c               | 164 ++++++++++++++++++++++-
>  4 files changed, 190 insertions(+), 4 deletions(-)
>

[....]


> +
> +static size_t cal_rt_frame_size(void)
> +{
> +       struct rt_sigframe __user *frame;
> +       static size_t frame_size;
> +       size_t total_context_size = 0;
> +       size_t sc_reserved_size = sizeof(frame->uc.uc_mcontext.__reserved);
> +
> +       if (frame_size)
> +               goto done;
> +
> +       frame_size = sizeof(*frame);
> +
> +       if (has_vector)
> +               total_context_size += rvv_sc_size;
> +       /* Preserved a __riscv_ctx_hdr for END signal context header. */
> +       total_context_size += sizeof(struct __riscv_ctx_hdr);
> +
> +       if (total_context_size > sc_reserved_size)
> +               frame_size += (total_context_size - sc_reserved_size);
> +
> +done:
> +       return round_up(frame_size, 16);

Hi Greentime,

frame_size is static variable here, so it will preserve the value for
the next calling to cal_rt_frame_size().

I think we need update frame_size before return, example:

frame_size =  round_up(frame_size, 16);
return frame_size;


Regards
Ley Foon

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2021-09-30  2:37 UTC|newest]

Thread overview: 112+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-08 17:45 [RFC PATCH v8 00/21] riscv: Add vector ISA support Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 01/21] riscv: Separate patch for cflags and aflags Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 02/21] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 03/21] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 04/21] riscv: Add new csr defines related to vector extension Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 05/21] riscv: Add vector feature to compile Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 06/21] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 07/21] riscv: Reset vector register Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 08/21] riscv: Add vector struct and assembler definitions Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 09/21] riscv: Add task switch support for vector Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-08 20:47   ` kernel test robot
2021-09-08 20:47     ` kernel test robot
2021-09-13 12:21   ` Darius Rad
2021-09-13 12:21     ` Darius Rad
2021-09-28 14:56     ` Greentime Hu
2021-09-28 14:56       ` Greentime Hu
2021-09-29 13:28       ` Darius Rad
2021-09-29 13:28         ` Darius Rad
2021-10-01  2:46         ` Ley Foon Tan
2021-10-01  2:46           ` Ley Foon Tan
2021-10-04 12:41           ` Greentime Hu
2021-10-04 12:41             ` Greentime Hu
2021-10-05  2:12             ` Ley Foon Tan
2021-10-05  2:12               ` Ley Foon Tan
2021-10-05 15:46               ` Greentime Hu
2021-10-05 15:46                 ` Greentime Hu
2021-10-07 10:10                 ` Ley Foon Tan
2021-10-07 10:10                   ` Ley Foon Tan
2021-10-04 12:36         ` Greentime Hu
2021-10-04 12:36           ` Greentime Hu
2021-10-05 13:57           ` Darius Rad
2021-10-05 13:57             ` Darius Rad
2021-10-21  1:01             ` Paul Walmsley
2021-10-21  1:01               ` Paul Walmsley
2021-10-21 10:50               ` Darius Rad
2021-10-21 10:50                 ` Darius Rad
2021-10-22  3:52                 ` Vincent Chen
2021-10-22  3:52                   ` Vincent Chen
2021-10-22 10:40                   ` Darius Rad
2021-10-22 10:40                     ` Darius Rad
2021-10-25  4:47                     ` Greentime Hu
2021-10-25  4:47                       ` Greentime Hu
2021-10-25 16:22                       ` Darius Rad
2021-10-25 16:22                         ` Darius Rad
2021-10-26  4:44                         ` Greentime Hu
2021-10-26  4:44                           ` Greentime Hu
2021-10-27 12:58                           ` Darius Rad
2021-10-27 12:58                             ` Darius Rad
2021-11-09  9:49                             ` Greentime Hu
2021-11-09  9:49                               ` Greentime Hu
2021-11-09 19:21                               ` Darius Rad
2021-11-09 19:21                                 ` Darius Rad
2021-10-26 14:58                     ` Heiko Stübner
2021-10-26 14:58                       ` Heiko Stübner
2021-09-08 17:45 ` [RFC PATCH v8 10/21] riscv: Add ptrace vector support Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 11/21] riscv: Add sigcontext save/restore for vector Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-30  2:37   ` Ley Foon Tan [this message]
2021-09-30  2:37     ` Ley Foon Tan
2021-09-08 17:45 ` [RFC PATCH v8 12/21] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 13/21] riscv: Add support for kernel mode vector Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-09  6:17   ` Christoph Hellwig
2021-09-09  6:17     ` Christoph Hellwig
2021-09-08 17:45 ` [RFC PATCH v8 14/21] riscv: Use CSR_STATUS to replace sstatus in vector.S Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 15/21] riscv: Add vector extension XOR implementation Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-09  6:12   ` Christoph Hellwig
2021-09-09  6:12     ` Christoph Hellwig
2021-09-28  7:00     ` Greentime Hu
2021-09-28  7:00       ` Greentime Hu
2021-09-14  8:29   ` Ley Foon Tan
2021-09-14  8:29     ` Ley Foon Tan
2021-09-28  7:01     ` Greentime Hu
2021-09-28  7:01       ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 16/21] riscv: Initialize vector registers with proper vsetvli then it can work normally Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 17/21] riscv: Optimize vector registers initialization Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 18/21] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 19/21] riscv: Allocate space for vector registers in start_thread() Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 20/21] riscv: Optimize task switch codes of vector Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-15 14:29   ` Jisheng Zhang
2021-09-15 14:29     ` Jisheng Zhang
2021-10-04 14:13     ` Greentime Hu
2021-10-04 14:13       ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 21/21] riscv: Turn has_vector into a static key if VECTOR=y Greentime Hu
2021-09-08 17:45   ` Greentime Hu
2021-09-15 14:24   ` Jisheng Zhang
2021-09-15 14:24     ` Jisheng Zhang
2021-10-04 15:04     ` Greentime Hu
2021-10-04 15:04       ` Greentime Hu
2021-09-13  1:47 ` [RFC PATCH v8 00/21] riscv: Add vector ISA support Vincent Chen
2021-09-13  1:47   ` Vincent Chen
2021-09-13 17:18 ` Vineet Gupta
2021-09-13 17:18   ` Vineet Gupta

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