From: Greentime Hu <greentime.hu@sifive.com> To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu, palmer@dabbelt.com, paul.walmsley@sifive.com, vincent.chen@sifive.com Subject: [RFC PATCH v8 12/21] riscv: signal: Report signal frame size to userspace via auxv Date: Thu, 9 Sep 2021 01:45:24 +0800 [thread overview] Message-ID: <a46ba4d46419f3aff74019a177145a3732a07c99.1631121222.git.greentime.hu@sifive.com> (raw) In-Reply-To: <cover.1631121222.git.greentime.hu@sifive.com> From: Vincent Chen <vincent.chen@sifive.com> The vector register belongs to the signal context. They need to be stored and restored as entering and leaving the signal handler. According to the V-extension specification, the maximum length of the vector registers can be 2^(XLEN-1). Hence, if userspace refers to the MINSIGSTKSZ to create a sigframe, it may not be enough. To resolve this problem, this patch refers to the commit 94b07c1f8c39c ("arm64: signal: Report signal frame size to userspace via auxv") to enable userspace to know the minimum required sigframe size through the auxiliary vector and use it to allocate enough memory for signal context. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> --- arch/riscv/include/asm/elf.h | 41 +++++++++++++++++----------- arch/riscv/include/asm/processor.h | 2 ++ arch/riscv/include/uapi/asm/auxvec.h | 1 + arch/riscv/kernel/signal.c | 8 ++++++ 4 files changed, 36 insertions(+), 16 deletions(-) diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index f4b490cd0e5d..1102052aa593 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -58,22 +58,31 @@ extern unsigned long elf_hwcap; #define ELF_PLATFORM (NULL) #ifdef CONFIG_MMU -#define ARCH_DLINFO \ -do { \ - NEW_AUX_ENT(AT_SYSINFO_EHDR, \ - (elf_addr_t)current->mm->context.vdso); \ - NEW_AUX_ENT(AT_L1I_CACHESIZE, \ - get_cache_size(1, CACHE_TYPE_INST)); \ - NEW_AUX_ENT(AT_L1I_CACHEGEOMETRY, \ - get_cache_geometry(1, CACHE_TYPE_INST)); \ - NEW_AUX_ENT(AT_L1D_CACHESIZE, \ - get_cache_size(1, CACHE_TYPE_DATA)); \ - NEW_AUX_ENT(AT_L1D_CACHEGEOMETRY, \ - get_cache_geometry(1, CACHE_TYPE_DATA)); \ - NEW_AUX_ENT(AT_L2_CACHESIZE, \ - get_cache_size(2, CACHE_TYPE_UNIFIED)); \ - NEW_AUX_ENT(AT_L2_CACHEGEOMETRY, \ - get_cache_geometry(2, CACHE_TYPE_UNIFIED)); \ +#define ARCH_DLINFO \ +do { \ + NEW_AUX_ENT(AT_SYSINFO_EHDR, \ + (elf_addr_t)current->mm->context.vdso); \ + NEW_AUX_ENT(AT_L1I_CACHESIZE, \ + get_cache_size(1, CACHE_TYPE_INST)); \ + NEW_AUX_ENT(AT_L1I_CACHEGEOMETRY, \ + get_cache_geometry(1, CACHE_TYPE_INST)); \ + NEW_AUX_ENT(AT_L1D_CACHESIZE, \ + get_cache_size(1, CACHE_TYPE_DATA)); \ + NEW_AUX_ENT(AT_L1D_CACHEGEOMETRY, \ + get_cache_geometry(1, CACHE_TYPE_DATA)); \ + NEW_AUX_ENT(AT_L2_CACHESIZE, \ + get_cache_size(2, CACHE_TYPE_UNIFIED)); \ + NEW_AUX_ENT(AT_L2_CACHEGEOMETRY, \ + get_cache_geometry(2, CACHE_TYPE_UNIFIED)); \ + /* \ + * Should always be nonzero unless there's a kernel bug. \ + * If we haven't determined a sensible value to give to \ + * userspace, omit the entry: \ + */ \ + if (likely(signal_minsigstksz)) \ + NEW_AUX_ENT(AT_MINSIGSTKSZ, signal_minsigstksz); \ + else \ + NEW_AUX_ENT(AT_IGNORE, 0); \ } while (0) #define ARCH_HAS_SETUP_ADDITIONAL_PAGES struct linux_binprm; diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 1b037c69d311..62c75645c606 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -7,6 +7,7 @@ #define _ASM_RISCV_PROCESSOR_H #include <linux/const.h> +#include <linux/cache.h> #include <vdso/processor.h> @@ -74,6 +75,7 @@ int riscv_of_parent_hartid(struct device_node *node); extern void riscv_fill_hwcap(void); extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); +extern unsigned long signal_minsigstksz __ro_after_init; #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/include/uapi/asm/auxvec.h b/arch/riscv/include/uapi/asm/auxvec.h index 32c73ba1d531..6610d24e6662 100644 --- a/arch/riscv/include/uapi/asm/auxvec.h +++ b/arch/riscv/include/uapi/asm/auxvec.h @@ -33,5 +33,6 @@ /* entries in ARCH_DLINFO */ #define AT_VECTOR_SIZE_ARCH 7 +#define AT_MINSIGSTKSZ 51 #endif /* _UAPI_ASM_RISCV_AUXVEC_H */ diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 6938cfa16b45..d30a3b588156 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -470,8 +470,16 @@ asmlinkage __visible void do_notify_resume(struct pt_regs *regs, tracehook_notify_resume(regs); } +unsigned long __ro_after_init signal_minsigstksz; + void init_rt_signal_env(void); void __init init_rt_signal_env(void) { rvv_sc_size = sizeof(struct __sc_riscv_v_state) + riscv_vsize; + /* + * Determine the stack space required for guaranteed signal delivery. + * The signal_minsigstksz will be populated into the AT_MINSIGSTKSZ entry + * in the auxiliary array at process startup. + */ + signal_minsigstksz = cal_rt_frame_size(); } -- 2.31.1
WARNING: multiple messages have this Message-ID (diff)
From: Greentime Hu <greentime.hu@sifive.com> To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu, palmer@dabbelt.com, paul.walmsley@sifive.com, vincent.chen@sifive.com Subject: [RFC PATCH v8 12/21] riscv: signal: Report signal frame size to userspace via auxv Date: Thu, 9 Sep 2021 01:45:24 +0800 [thread overview] Message-ID: <a46ba4d46419f3aff74019a177145a3732a07c99.1631121222.git.greentime.hu@sifive.com> (raw) In-Reply-To: <cover.1631121222.git.greentime.hu@sifive.com> From: Vincent Chen <vincent.chen@sifive.com> The vector register belongs to the signal context. They need to be stored and restored as entering and leaving the signal handler. According to the V-extension specification, the maximum length of the vector registers can be 2^(XLEN-1). Hence, if userspace refers to the MINSIGSTKSZ to create a sigframe, it may not be enough. To resolve this problem, this patch refers to the commit 94b07c1f8c39c ("arm64: signal: Report signal frame size to userspace via auxv") to enable userspace to know the minimum required sigframe size through the auxiliary vector and use it to allocate enough memory for signal context. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> --- arch/riscv/include/asm/elf.h | 41 +++++++++++++++++----------- arch/riscv/include/asm/processor.h | 2 ++ arch/riscv/include/uapi/asm/auxvec.h | 1 + arch/riscv/kernel/signal.c | 8 ++++++ 4 files changed, 36 insertions(+), 16 deletions(-) diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index f4b490cd0e5d..1102052aa593 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -58,22 +58,31 @@ extern unsigned long elf_hwcap; #define ELF_PLATFORM (NULL) #ifdef CONFIG_MMU -#define ARCH_DLINFO \ -do { \ - NEW_AUX_ENT(AT_SYSINFO_EHDR, \ - (elf_addr_t)current->mm->context.vdso); \ - NEW_AUX_ENT(AT_L1I_CACHESIZE, \ - get_cache_size(1, CACHE_TYPE_INST)); \ - NEW_AUX_ENT(AT_L1I_CACHEGEOMETRY, \ - get_cache_geometry(1, CACHE_TYPE_INST)); \ - NEW_AUX_ENT(AT_L1D_CACHESIZE, \ - get_cache_size(1, CACHE_TYPE_DATA)); \ - NEW_AUX_ENT(AT_L1D_CACHEGEOMETRY, \ - get_cache_geometry(1, CACHE_TYPE_DATA)); \ - NEW_AUX_ENT(AT_L2_CACHESIZE, \ - get_cache_size(2, CACHE_TYPE_UNIFIED)); \ - NEW_AUX_ENT(AT_L2_CACHEGEOMETRY, \ - get_cache_geometry(2, CACHE_TYPE_UNIFIED)); \ +#define ARCH_DLINFO \ +do { \ + NEW_AUX_ENT(AT_SYSINFO_EHDR, \ + (elf_addr_t)current->mm->context.vdso); \ + NEW_AUX_ENT(AT_L1I_CACHESIZE, \ + get_cache_size(1, CACHE_TYPE_INST)); \ + NEW_AUX_ENT(AT_L1I_CACHEGEOMETRY, \ + get_cache_geometry(1, CACHE_TYPE_INST)); \ + NEW_AUX_ENT(AT_L1D_CACHESIZE, \ + get_cache_size(1, CACHE_TYPE_DATA)); \ + NEW_AUX_ENT(AT_L1D_CACHEGEOMETRY, \ + get_cache_geometry(1, CACHE_TYPE_DATA)); \ + NEW_AUX_ENT(AT_L2_CACHESIZE, \ + get_cache_size(2, CACHE_TYPE_UNIFIED)); \ + NEW_AUX_ENT(AT_L2_CACHEGEOMETRY, \ + get_cache_geometry(2, CACHE_TYPE_UNIFIED)); \ + /* \ + * Should always be nonzero unless there's a kernel bug. \ + * If we haven't determined a sensible value to give to \ + * userspace, omit the entry: \ + */ \ + if (likely(signal_minsigstksz)) \ + NEW_AUX_ENT(AT_MINSIGSTKSZ, signal_minsigstksz); \ + else \ + NEW_AUX_ENT(AT_IGNORE, 0); \ } while (0) #define ARCH_HAS_SETUP_ADDITIONAL_PAGES struct linux_binprm; diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 1b037c69d311..62c75645c606 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -7,6 +7,7 @@ #define _ASM_RISCV_PROCESSOR_H #include <linux/const.h> +#include <linux/cache.h> #include <vdso/processor.h> @@ -74,6 +75,7 @@ int riscv_of_parent_hartid(struct device_node *node); extern void riscv_fill_hwcap(void); extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); +extern unsigned long signal_minsigstksz __ro_after_init; #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/include/uapi/asm/auxvec.h b/arch/riscv/include/uapi/asm/auxvec.h index 32c73ba1d531..6610d24e6662 100644 --- a/arch/riscv/include/uapi/asm/auxvec.h +++ b/arch/riscv/include/uapi/asm/auxvec.h @@ -33,5 +33,6 @@ /* entries in ARCH_DLINFO */ #define AT_VECTOR_SIZE_ARCH 7 +#define AT_MINSIGSTKSZ 51 #endif /* _UAPI_ASM_RISCV_AUXVEC_H */ diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 6938cfa16b45..d30a3b588156 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -470,8 +470,16 @@ asmlinkage __visible void do_notify_resume(struct pt_regs *regs, tracehook_notify_resume(regs); } +unsigned long __ro_after_init signal_minsigstksz; + void init_rt_signal_env(void); void __init init_rt_signal_env(void) { rvv_sc_size = sizeof(struct __sc_riscv_v_state) + riscv_vsize; + /* + * Determine the stack space required for guaranteed signal delivery. + * The signal_minsigstksz will be populated into the AT_MINSIGSTKSZ entry + * in the auxiliary array at process startup. + */ + signal_minsigstksz = cal_rt_frame_size(); } -- 2.31.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-09-08 17:46 UTC|newest] Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-08 17:45 [RFC PATCH v8 00/21] riscv: Add vector ISA support Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 01/21] riscv: Separate patch for cflags and aflags Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 02/21] riscv: Rename __switch_to_aux -> fpu Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 03/21] riscv: Extending cpufeature.c to detect V-extension Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 04/21] riscv: Add new csr defines related to vector extension Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 05/21] riscv: Add vector feature to compile Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 06/21] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 07/21] riscv: Reset vector register Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 08/21] riscv: Add vector struct and assembler definitions Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 09/21] riscv: Add task switch support for vector Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 20:47 ` kernel test robot 2021-09-08 20:47 ` kernel test robot 2021-09-13 12:21 ` Darius Rad 2021-09-13 12:21 ` Darius Rad 2021-09-28 14:56 ` Greentime Hu 2021-09-28 14:56 ` Greentime Hu 2021-09-29 13:28 ` Darius Rad 2021-09-29 13:28 ` Darius Rad 2021-10-01 2:46 ` Ley Foon Tan 2021-10-01 2:46 ` Ley Foon Tan 2021-10-04 12:41 ` Greentime Hu 2021-10-04 12:41 ` Greentime Hu 2021-10-05 2:12 ` Ley Foon Tan 2021-10-05 2:12 ` Ley Foon Tan 2021-10-05 15:46 ` Greentime Hu 2021-10-05 15:46 ` Greentime Hu 2021-10-07 10:10 ` Ley Foon Tan 2021-10-07 10:10 ` Ley Foon Tan 2021-10-04 12:36 ` Greentime Hu 2021-10-04 12:36 ` Greentime Hu 2021-10-05 13:57 ` Darius Rad 2021-10-05 13:57 ` Darius Rad 2021-10-21 1:01 ` Paul Walmsley 2021-10-21 1:01 ` Paul Walmsley 2021-10-21 10:50 ` Darius Rad 2021-10-21 10:50 ` Darius Rad 2021-10-22 3:52 ` Vincent Chen 2021-10-22 3:52 ` Vincent Chen 2021-10-22 10:40 ` Darius Rad 2021-10-22 10:40 ` Darius Rad 2021-10-25 4:47 ` Greentime Hu 2021-10-25 4:47 ` Greentime Hu 2021-10-25 16:22 ` Darius Rad 2021-10-25 16:22 ` Darius Rad 2021-10-26 4:44 ` Greentime Hu 2021-10-26 4:44 ` Greentime Hu 2021-10-27 12:58 ` Darius Rad 2021-10-27 12:58 ` Darius Rad 2021-11-09 9:49 ` Greentime Hu 2021-11-09 9:49 ` Greentime Hu 2021-11-09 19:21 ` Darius Rad 2021-11-09 19:21 ` Darius Rad 2021-10-26 14:58 ` Heiko Stübner 2021-10-26 14:58 ` Heiko Stübner 2021-09-08 17:45 ` [RFC PATCH v8 10/21] riscv: Add ptrace vector support Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 11/21] riscv: Add sigcontext save/restore for vector Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-30 2:37 ` Ley Foon Tan 2021-09-30 2:37 ` Ley Foon Tan 2021-09-08 17:45 ` Greentime Hu [this message] 2021-09-08 17:45 ` [RFC PATCH v8 12/21] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 13/21] riscv: Add support for kernel mode vector Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-09 6:17 ` Christoph Hellwig 2021-09-09 6:17 ` Christoph Hellwig 2021-09-08 17:45 ` [RFC PATCH v8 14/21] riscv: Use CSR_STATUS to replace sstatus in vector.S Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 15/21] riscv: Add vector extension XOR implementation Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-09 6:12 ` Christoph Hellwig 2021-09-09 6:12 ` Christoph Hellwig 2021-09-28 7:00 ` Greentime Hu 2021-09-28 7:00 ` Greentime Hu 2021-09-14 8:29 ` Ley Foon Tan 2021-09-14 8:29 ` Ley Foon Tan 2021-09-28 7:01 ` Greentime Hu 2021-09-28 7:01 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 16/21] riscv: Initialize vector registers with proper vsetvli then it can work normally Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 17/21] riscv: Optimize vector registers initialization Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 18/21] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 19/21] riscv: Allocate space for vector registers in start_thread() Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 20/21] riscv: Optimize task switch codes of vector Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-15 14:29 ` Jisheng Zhang 2021-09-15 14:29 ` Jisheng Zhang 2021-10-04 14:13 ` Greentime Hu 2021-10-04 14:13 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 21/21] riscv: Turn has_vector into a static key if VECTOR=y Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-15 14:24 ` Jisheng Zhang 2021-09-15 14:24 ` Jisheng Zhang 2021-10-04 15:04 ` Greentime Hu 2021-10-04 15:04 ` Greentime Hu 2021-09-13 1:47 ` [RFC PATCH v8 00/21] riscv: Add vector ISA support Vincent Chen 2021-09-13 1:47 ` Vincent Chen 2021-09-13 17:18 ` Vineet Gupta 2021-09-13 17:18 ` Vineet Gupta
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