From: Greentime Hu <greentime.hu@sifive.com>
To: Ley Foon Tan <lftan.linux@gmail.com>
Cc: linux-riscv <linux-riscv@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Albert Ou <aou@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Vincent Chen <vincent.chen@sifive.com>
Subject: Re: [RFC PATCH v8 15/21] riscv: Add vector extension XOR implementation
Date: Tue, 28 Sep 2021 15:01:22 +0800 [thread overview]
Message-ID: <CAHCEeh+XDVEPjKhJ9OYv3xMGLRDnygA6CK_y8tDzr9RYFKC-Aw@mail.gmail.com> (raw)
In-Reply-To: <CAFiDJ59nbV_opZRxfsv2kj8ObSguT75GJUKhA6Zd3+BpQOynjw@mail.gmail.com>
Ley Foon Tan <lftan.linux@gmail.com> 於 2021年9月14日 週二 下午4:30寫道：
>
> On Thu, Sep 9, 2021 at 1:49 AM Greentime Hu <greentime.hu@sifive.com> wrote:
> >
> > This patch adds support for vector optimized XOR it is tested in spike and
> > qemu.
> >
> > Logs in spike:
> > [ 0.008365] xor: measuring software checksum speed
> > [ 0.048885] 8regs : 1719.000 MB/sec
> > [ 0.089080] 32regs : 1717.000 MB/sec
> > [ 0.129275] rvv : 7043.000 MB/sec
> > [ 0.129525] xor: using function: rvv (7043.000 MB/sec)
> >
> > Logs in qemu:
> > [ 0.098943] xor: measuring software checksum speed
> > [ 0.139391] 8regs : 2911.000 MB/sec
> > [ 0.181079] 32regs : 2813.000 MB/sec
> > [ 0.224260] rvv : 45.000 MB/sec
> > [ 0.225586] xor: using function: 8regs (2911.000 MB/sec)
> >
> > Co-developed-by: Han-Kuan Chen <hankuan.chen@sifive.com>
> > Signed-off-by: Han-Kuan Chen <hankuan.chen@sifive.com>
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > ---
> > arch/riscv/include/asm/xor.h | 74 ++++++++++++++++++++++++++++++++
> > arch/riscv/lib/Makefile | 1 +
> > arch/riscv/lib/xor.S | 81 ++++++++++++++++++++++++++++++++++++
> > 3 files changed, 156 insertions(+)
> > create mode 100644 arch/riscv/include/asm/xor.h
> > create mode 100644 arch/riscv/lib/xor.S
> >
> > diff --git a/arch/riscv/include/asm/xor.h b/arch/riscv/include/asm/xor.h
> > new file mode 100644
> > index 000000000000..60ee0224913d
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/xor.h
> > @@ -0,0 +1,74 @@
>
>
> [...]
>
> >
> > +extern bool has_vector;
> > +#undef XOR_TRY_TEMPLATES
> > +#define XOR_TRY_TEMPLATES \
> > + do { \
> > + xor_speed(&xor_block_8regs); \
> > + xor_speed(&xor_block_32regs); \
> > + if (has_vector) { \
> > + xor_speed(&xor_block_rvv);\
> > + } \
> > + } while (0)
> > +#endif
> >
> bool has_vector is changed to has_vector() function now, should this
> change as well?
That's right. Thank you, LeyFoon.
I'll merge the patch to fix the has_vector() issue in next version patchset.
WARNING: multiple messages have this Message-ID (diff)
From: Greentime Hu <greentime.hu@sifive.com>
To: Ley Foon Tan <lftan.linux@gmail.com>
Cc: linux-riscv <linux-riscv@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Albert Ou <aou@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Vincent Chen <vincent.chen@sifive.com>
Subject: Re: [RFC PATCH v8 15/21] riscv: Add vector extension XOR implementation
Date: Tue, 28 Sep 2021 15:01:22 +0800 [thread overview]
Message-ID: <CAHCEeh+XDVEPjKhJ9OYv3xMGLRDnygA6CK_y8tDzr9RYFKC-Aw@mail.gmail.com> (raw)
In-Reply-To: <CAFiDJ59nbV_opZRxfsv2kj8ObSguT75GJUKhA6Zd3+BpQOynjw@mail.gmail.com>
Ley Foon Tan <lftan.linux@gmail.com> 於 2021年9月14日 週二 下午4:30寫道：
>
> On Thu, Sep 9, 2021 at 1:49 AM Greentime Hu <greentime.hu@sifive.com> wrote:
> >
> > This patch adds support for vector optimized XOR it is tested in spike and
> > qemu.
> >
> > Logs in spike:
> > [ 0.008365] xor: measuring software checksum speed
> > [ 0.048885] 8regs : 1719.000 MB/sec
> > [ 0.089080] 32regs : 1717.000 MB/sec
> > [ 0.129275] rvv : 7043.000 MB/sec
> > [ 0.129525] xor: using function: rvv (7043.000 MB/sec)
> >
> > Logs in qemu:
> > [ 0.098943] xor: measuring software checksum speed
> > [ 0.139391] 8regs : 2911.000 MB/sec
> > [ 0.181079] 32regs : 2813.000 MB/sec
> > [ 0.224260] rvv : 45.000 MB/sec
> > [ 0.225586] xor: using function: 8regs (2911.000 MB/sec)
> >
> > Co-developed-by: Han-Kuan Chen <hankuan.chen@sifive.com>
> > Signed-off-by: Han-Kuan Chen <hankuan.chen@sifive.com>
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > ---
> > arch/riscv/include/asm/xor.h | 74 ++++++++++++++++++++++++++++++++
> > arch/riscv/lib/Makefile | 1 +
> > arch/riscv/lib/xor.S | 81 ++++++++++++++++++++++++++++++++++++
> > 3 files changed, 156 insertions(+)
> > create mode 100644 arch/riscv/include/asm/xor.h
> > create mode 100644 arch/riscv/lib/xor.S
> >
> > diff --git a/arch/riscv/include/asm/xor.h b/arch/riscv/include/asm/xor.h
> > new file mode 100644
> > index 000000000000..60ee0224913d
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/xor.h
> > @@ -0,0 +1,74 @@
>
>
> [...]
>
> >
> > +extern bool has_vector;
> > +#undef XOR_TRY_TEMPLATES
> > +#define XOR_TRY_TEMPLATES \
> > + do { \
> > + xor_speed(&xor_block_8regs); \
> > + xor_speed(&xor_block_32regs); \
> > + if (has_vector) { \
> > + xor_speed(&xor_block_rvv);\
> > + } \
> > + } while (0)
> > +#endif
> >
> bool has_vector is changed to has_vector() function now, should this
> change as well?
That's right. Thank you, LeyFoon.
I'll merge the patch to fix the has_vector() issue in next version patchset.
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next prev parent reply other threads:[~2021-09-28 7:01 UTC|newest]
Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-08 17:45 [RFC PATCH v8 00/21] riscv: Add vector ISA support Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 01/21] riscv: Separate patch for cflags and aflags Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 02/21] riscv: Rename __switch_to_aux -> fpu Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 03/21] riscv: Extending cpufeature.c to detect V-extension Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 04/21] riscv: Add new csr defines related to vector extension Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 05/21] riscv: Add vector feature to compile Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 06/21] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 07/21] riscv: Reset vector register Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 08/21] riscv: Add vector struct and assembler definitions Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 09/21] riscv: Add task switch support for vector Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-08 20:47 ` kernel test robot
2021-09-08 20:47 ` kernel test robot
2021-09-13 12:21 ` Darius Rad
2021-09-13 12:21 ` Darius Rad
2021-09-28 14:56 ` Greentime Hu
2021-09-28 14:56 ` Greentime Hu
2021-09-29 13:28 ` Darius Rad
2021-09-29 13:28 ` Darius Rad
2021-10-01 2:46 ` Ley Foon Tan
2021-10-01 2:46 ` Ley Foon Tan
2021-10-04 12:41 ` Greentime Hu
2021-10-04 12:41 ` Greentime Hu
2021-10-05 2:12 ` Ley Foon Tan
2021-10-05 2:12 ` Ley Foon Tan
2021-10-05 15:46 ` Greentime Hu
2021-10-05 15:46 ` Greentime Hu
2021-10-07 10:10 ` Ley Foon Tan
2021-10-07 10:10 ` Ley Foon Tan
2021-10-04 12:36 ` Greentime Hu
2021-10-04 12:36 ` Greentime Hu
2021-10-05 13:57 ` Darius Rad
2021-10-05 13:57 ` Darius Rad
2021-10-21 1:01 ` Paul Walmsley
2021-10-21 1:01 ` Paul Walmsley
2021-10-21 10:50 ` Darius Rad
2021-10-21 10:50 ` Darius Rad
2021-10-22 3:52 ` Vincent Chen
2021-10-22 3:52 ` Vincent Chen
2021-10-22 10:40 ` Darius Rad
2021-10-22 10:40 ` Darius Rad
2021-10-25 4:47 ` Greentime Hu
2021-10-25 4:47 ` Greentime Hu
2021-10-25 16:22 ` Darius Rad
2021-10-25 16:22 ` Darius Rad
2021-10-26 4:44 ` Greentime Hu
2021-10-26 4:44 ` Greentime Hu
2021-10-27 12:58 ` Darius Rad
2021-10-27 12:58 ` Darius Rad
2021-11-09 9:49 ` Greentime Hu
2021-11-09 9:49 ` Greentime Hu
2021-11-09 19:21 ` Darius Rad
2021-11-09 19:21 ` Darius Rad
2021-10-26 14:58 ` Heiko Stübner
2021-10-26 14:58 ` Heiko Stübner
2021-09-08 17:45 ` [RFC PATCH v8 10/21] riscv: Add ptrace vector support Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 11/21] riscv: Add sigcontext save/restore for vector Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-30 2:37 ` Ley Foon Tan
2021-09-30 2:37 ` Ley Foon Tan
2021-09-08 17:45 ` [RFC PATCH v8 12/21] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 13/21] riscv: Add support for kernel mode vector Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-09 6:17 ` Christoph Hellwig
2021-09-09 6:17 ` Christoph Hellwig
2021-09-08 17:45 ` [RFC PATCH v8 14/21] riscv: Use CSR_STATUS to replace sstatus in vector.S Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 15/21] riscv: Add vector extension XOR implementation Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-09 6:12 ` Christoph Hellwig
2021-09-09 6:12 ` Christoph Hellwig
2021-09-28 7:00 ` Greentime Hu
2021-09-28 7:00 ` Greentime Hu
2021-09-14 8:29 ` Ley Foon Tan
2021-09-14 8:29 ` Ley Foon Tan
2021-09-28 7:01 ` Greentime Hu [this message]
2021-09-28 7:01 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 16/21] riscv: Initialize vector registers with proper vsetvli then it can work normally Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 17/21] riscv: Optimize vector registers initialization Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 18/21] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 19/21] riscv: Allocate space for vector registers in start_thread() Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 20/21] riscv: Optimize task switch codes of vector Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-15 14:29 ` Jisheng Zhang
2021-09-15 14:29 ` Jisheng Zhang
2021-10-04 14:13 ` Greentime Hu
2021-10-04 14:13 ` Greentime Hu
2021-09-08 17:45 ` [RFC PATCH v8 21/21] riscv: Turn has_vector into a static key if VECTOR=y Greentime Hu
2021-09-08 17:45 ` Greentime Hu
2021-09-15 14:24 ` Jisheng Zhang
2021-09-15 14:24 ` Jisheng Zhang
2021-10-04 15:04 ` Greentime Hu
2021-10-04 15:04 ` Greentime Hu
2021-09-13 1:47 ` [RFC PATCH v8 00/21] riscv: Add vector ISA support Vincent Chen
2021-09-13 1:47 ` Vincent Chen
2021-09-13 17:18 ` Vineet Gupta
2021-09-13 17:18 ` Vineet Gupta
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