From: Greentime Hu <greentime.hu@sifive.com> To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu, palmer@dabbelt.com, paul.walmsley@sifive.com, vincent.chen@sifive.com Subject: [RFC PATCH v8 17/21] riscv: Optimize vector registers initialization Date: Thu, 9 Sep 2021 01:45:29 +0800 [thread overview] Message-ID: <e742a1ac4028694a85800d0966a9ab0c9fc1c1fe.1631121222.git.greentime.hu@sifive.com> (raw) In-Reply-To: <cover.1631121222.git.greentime.hu@sifive.com> This patch optimizes the initialization or invalidation of vector registers. It can reduce the code sizes of vector_flush_cpu_state() and reset_regs(). Co-developed-by: Han-Kuan Chen <hankuan.chen@sifive.com> Signed-off-by: Han-Kuan Chen <hankuan.chen@sifive.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> --- arch/riscv/kernel/head.S | 30 +----------------------- arch/riscv/kernel/kernel_mode_vector.c | 32 ++------------------------ 2 files changed, 3 insertions(+), 59 deletions(-) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 42eb3203fa77..8362d7458c6c 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -442,39 +442,11 @@ ENTRY(reset_regs) li t1, SR_VS csrs CSR_STATUS, t1 - vsetvli t1, x0, e8, m1 + vsetvli t1, x0, e8, m8 vmv.v.i v0, 0 - vmv.v.i v1, 0 - vmv.v.i v2, 0 - vmv.v.i v3, 0 - vmv.v.i v4, 0 - vmv.v.i v5, 0 - vmv.v.i v6, 0 - vmv.v.i v7, 0 vmv.v.i v8, 0 - vmv.v.i v9, 0 - vmv.v.i v10, 0 - vmv.v.i v11, 0 - vmv.v.i v12, 0 - vmv.v.i v13, 0 - vmv.v.i v14, 0 - vmv.v.i v15, 0 vmv.v.i v16, 0 - vmv.v.i v17, 0 - vmv.v.i v18, 0 - vmv.v.i v19, 0 - vmv.v.i v20, 0 - vmv.v.i v21, 0 - vmv.v.i v22, 0 - vmv.v.i v23, 0 vmv.v.i v24, 0 - vmv.v.i v25, 0 - vmv.v.i v26, 0 - vmv.v.i v27, 0 - vmv.v.i v28, 0 - vmv.v.i v29, 0 - vmv.v.i v30, 0 - vmv.v.i v31, 0 /* note that the caller must clear SR_VS */ #endif /* CONFIG_VECTOR */ diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c index 108cfafe7496..b84618630edf 100644 --- a/arch/riscv/kernel/kernel_mode_vector.c +++ b/arch/riscv/kernel/kernel_mode_vector.c @@ -86,39 +86,11 @@ static void vector_flush_cpu_state(void) long tmp; __asm__ __volatile__ ( - "vsetvli %0, x0, e8, m1\n" + "vsetvli %0, x0, e8, m8\n" "vmv.v.i v0, 0\n" - "vmv.v.i v1, 0\n" - "vmv.v.i v2, 0\n" - "vmv.v.i v3, 0\n" - "vmv.v.i v4, 0\n" - "vmv.v.i v5, 0\n" - "vmv.v.i v6, 0\n" - "vmv.v.i v7, 0\n" "vmv.v.i v8, 0\n" - "vmv.v.i v9, 0\n" - "vmv.v.i v10, 0\n" - "vmv.v.i v11, 0\n" - "vmv.v.i v12, 0\n" - "vmv.v.i v13, 0\n" - "vmv.v.i v14, 0\n" - "vmv.v.i v15, 0\n" "vmv.v.i v16, 0\n" - "vmv.v.i v17, 0\n" - "vmv.v.i v18, 0\n" - "vmv.v.i v19, 0\n" - "vmv.v.i v20, 0\n" - "vmv.v.i v21, 0\n" - "vmv.v.i v22, 0\n" - "vmv.v.i v23, 0\n" - "vmv.v.i v24, 0\n" - "vmv.v.i v25, 0\n" - "vmv.v.i v26, 0\n" - "vmv.v.i v27, 0\n" - "vmv.v.i v28, 0\n" - "vmv.v.i v29, 0\n" - "vmv.v.i v30, 0\n" - "vmv.v.i v31, 0\n":"=r"(tmp)::); + "vmv.v.i v24, 0\n":"=r"(tmp)::); } /* -- 2.31.1
WARNING: multiple messages have this Message-ID (diff)
From: Greentime Hu <greentime.hu@sifive.com> To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu, palmer@dabbelt.com, paul.walmsley@sifive.com, vincent.chen@sifive.com Subject: [RFC PATCH v8 17/21] riscv: Optimize vector registers initialization Date: Thu, 9 Sep 2021 01:45:29 +0800 [thread overview] Message-ID: <e742a1ac4028694a85800d0966a9ab0c9fc1c1fe.1631121222.git.greentime.hu@sifive.com> (raw) In-Reply-To: <cover.1631121222.git.greentime.hu@sifive.com> This patch optimizes the initialization or invalidation of vector registers. It can reduce the code sizes of vector_flush_cpu_state() and reset_regs(). Co-developed-by: Han-Kuan Chen <hankuan.chen@sifive.com> Signed-off-by: Han-Kuan Chen <hankuan.chen@sifive.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> --- arch/riscv/kernel/head.S | 30 +----------------------- arch/riscv/kernel/kernel_mode_vector.c | 32 ++------------------------ 2 files changed, 3 insertions(+), 59 deletions(-) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 42eb3203fa77..8362d7458c6c 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -442,39 +442,11 @@ ENTRY(reset_regs) li t1, SR_VS csrs CSR_STATUS, t1 - vsetvli t1, x0, e8, m1 + vsetvli t1, x0, e8, m8 vmv.v.i v0, 0 - vmv.v.i v1, 0 - vmv.v.i v2, 0 - vmv.v.i v3, 0 - vmv.v.i v4, 0 - vmv.v.i v5, 0 - vmv.v.i v6, 0 - vmv.v.i v7, 0 vmv.v.i v8, 0 - vmv.v.i v9, 0 - vmv.v.i v10, 0 - vmv.v.i v11, 0 - vmv.v.i v12, 0 - vmv.v.i v13, 0 - vmv.v.i v14, 0 - vmv.v.i v15, 0 vmv.v.i v16, 0 - vmv.v.i v17, 0 - vmv.v.i v18, 0 - vmv.v.i v19, 0 - vmv.v.i v20, 0 - vmv.v.i v21, 0 - vmv.v.i v22, 0 - vmv.v.i v23, 0 vmv.v.i v24, 0 - vmv.v.i v25, 0 - vmv.v.i v26, 0 - vmv.v.i v27, 0 - vmv.v.i v28, 0 - vmv.v.i v29, 0 - vmv.v.i v30, 0 - vmv.v.i v31, 0 /* note that the caller must clear SR_VS */ #endif /* CONFIG_VECTOR */ diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c index 108cfafe7496..b84618630edf 100644 --- a/arch/riscv/kernel/kernel_mode_vector.c +++ b/arch/riscv/kernel/kernel_mode_vector.c @@ -86,39 +86,11 @@ static void vector_flush_cpu_state(void) long tmp; __asm__ __volatile__ ( - "vsetvli %0, x0, e8, m1\n" + "vsetvli %0, x0, e8, m8\n" "vmv.v.i v0, 0\n" - "vmv.v.i v1, 0\n" - "vmv.v.i v2, 0\n" - "vmv.v.i v3, 0\n" - "vmv.v.i v4, 0\n" - "vmv.v.i v5, 0\n" - "vmv.v.i v6, 0\n" - "vmv.v.i v7, 0\n" "vmv.v.i v8, 0\n" - "vmv.v.i v9, 0\n" - "vmv.v.i v10, 0\n" - "vmv.v.i v11, 0\n" - "vmv.v.i v12, 0\n" - "vmv.v.i v13, 0\n" - "vmv.v.i v14, 0\n" - "vmv.v.i v15, 0\n" "vmv.v.i v16, 0\n" - "vmv.v.i v17, 0\n" - "vmv.v.i v18, 0\n" - "vmv.v.i v19, 0\n" - "vmv.v.i v20, 0\n" - "vmv.v.i v21, 0\n" - "vmv.v.i v22, 0\n" - "vmv.v.i v23, 0\n" - "vmv.v.i v24, 0\n" - "vmv.v.i v25, 0\n" - "vmv.v.i v26, 0\n" - "vmv.v.i v27, 0\n" - "vmv.v.i v28, 0\n" - "vmv.v.i v29, 0\n" - "vmv.v.i v30, 0\n" - "vmv.v.i v31, 0\n":"=r"(tmp)::); + "vmv.v.i v24, 0\n":"=r"(tmp)::); } /* -- 2.31.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-09-08 17:46 UTC|newest] Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-08 17:45 [RFC PATCH v8 00/21] riscv: Add vector ISA support Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 01/21] riscv: Separate patch for cflags and aflags Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 02/21] riscv: Rename __switch_to_aux -> fpu Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 03/21] riscv: Extending cpufeature.c to detect V-extension Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 04/21] riscv: Add new csr defines related to vector extension Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 05/21] riscv: Add vector feature to compile Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 06/21] riscv: Add has_vector/riscv_vsize to save vector features Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 07/21] riscv: Reset vector register Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 08/21] riscv: Add vector struct and assembler definitions Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 09/21] riscv: Add task switch support for vector Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 20:47 ` kernel test robot 2021-09-08 20:47 ` kernel test robot 2021-09-13 12:21 ` Darius Rad 2021-09-13 12:21 ` Darius Rad 2021-09-28 14:56 ` Greentime Hu 2021-09-28 14:56 ` Greentime Hu 2021-09-29 13:28 ` Darius Rad 2021-09-29 13:28 ` Darius Rad 2021-10-01 2:46 ` Ley Foon Tan 2021-10-01 2:46 ` Ley Foon Tan 2021-10-04 12:41 ` Greentime Hu 2021-10-04 12:41 ` Greentime Hu 2021-10-05 2:12 ` Ley Foon Tan 2021-10-05 2:12 ` Ley Foon Tan 2021-10-05 15:46 ` Greentime Hu 2021-10-05 15:46 ` Greentime Hu 2021-10-07 10:10 ` Ley Foon Tan 2021-10-07 10:10 ` Ley Foon Tan 2021-10-04 12:36 ` Greentime Hu 2021-10-04 12:36 ` Greentime Hu 2021-10-05 13:57 ` Darius Rad 2021-10-05 13:57 ` Darius Rad 2021-10-21 1:01 ` Paul Walmsley 2021-10-21 1:01 ` Paul Walmsley 2021-10-21 10:50 ` Darius Rad 2021-10-21 10:50 ` Darius Rad 2021-10-22 3:52 ` Vincent Chen 2021-10-22 3:52 ` Vincent Chen 2021-10-22 10:40 ` Darius Rad 2021-10-22 10:40 ` Darius Rad 2021-10-25 4:47 ` Greentime Hu 2021-10-25 4:47 ` Greentime Hu 2021-10-25 16:22 ` Darius Rad 2021-10-25 16:22 ` Darius Rad 2021-10-26 4:44 ` Greentime Hu 2021-10-26 4:44 ` Greentime Hu 2021-10-27 12:58 ` Darius Rad 2021-10-27 12:58 ` Darius Rad 2021-11-09 9:49 ` Greentime Hu 2021-11-09 9:49 ` Greentime Hu 2021-11-09 19:21 ` Darius Rad 2021-11-09 19:21 ` Darius Rad 2021-10-26 14:58 ` Heiko Stübner 2021-10-26 14:58 ` Heiko Stübner 2021-09-08 17:45 ` [RFC PATCH v8 10/21] riscv: Add ptrace vector support Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 11/21] riscv: Add sigcontext save/restore for vector Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-30 2:37 ` Ley Foon Tan 2021-09-30 2:37 ` Ley Foon Tan 2021-09-08 17:45 ` [RFC PATCH v8 12/21] riscv: signal: Report signal frame size to userspace via auxv Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 13/21] riscv: Add support for kernel mode vector Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-09 6:17 ` Christoph Hellwig 2021-09-09 6:17 ` Christoph Hellwig 2021-09-08 17:45 ` [RFC PATCH v8 14/21] riscv: Use CSR_STATUS to replace sstatus in vector.S Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 15/21] riscv: Add vector extension XOR implementation Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-09 6:12 ` Christoph Hellwig 2021-09-09 6:12 ` Christoph Hellwig 2021-09-28 7:00 ` Greentime Hu 2021-09-28 7:00 ` Greentime Hu 2021-09-14 8:29 ` Ley Foon Tan 2021-09-14 8:29 ` Ley Foon Tan 2021-09-28 7:01 ` Greentime Hu 2021-09-28 7:01 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 16/21] riscv: Initialize vector registers with proper vsetvli then it can work normally Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` Greentime Hu [this message] 2021-09-08 17:45 ` [RFC PATCH v8 17/21] riscv: Optimize vector registers initialization Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 18/21] riscv: Fix an illegal instruction exception when accessing vlenb without enable vector first Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 19/21] riscv: Allocate space for vector registers in start_thread() Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 20/21] riscv: Optimize task switch codes of vector Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-15 14:29 ` Jisheng Zhang 2021-09-15 14:29 ` Jisheng Zhang 2021-10-04 14:13 ` Greentime Hu 2021-10-04 14:13 ` Greentime Hu 2021-09-08 17:45 ` [RFC PATCH v8 21/21] riscv: Turn has_vector into a static key if VECTOR=y Greentime Hu 2021-09-08 17:45 ` Greentime Hu 2021-09-15 14:24 ` Jisheng Zhang 2021-09-15 14:24 ` Jisheng Zhang 2021-10-04 15:04 ` Greentime Hu 2021-10-04 15:04 ` Greentime Hu 2021-09-13 1:47 ` [RFC PATCH v8 00/21] riscv: Add vector ISA support Vincent Chen 2021-09-13 1:47 ` Vincent Chen 2021-09-13 17:18 ` Vineet Gupta 2021-09-13 17:18 ` Vineet Gupta
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